Large-size heat dissipation and double-groove waterproof MOS (Metal Oxide Semiconductor) field effect transistor chip packaging structure

Abstract

The utility model discloses a large-size heat dissipation and double-groove waterproof MOS field effect transistor chip packaging structure, which comprises a substrate and a plurality of packaging units arranged on the substrate, each packaging unit is provided with a lead frame, a base island, a connecting pin and a plastic packaging part, and the front surface of the base island is provided with two glue grooves close to a plastic packaging line; the back surface of the base island is provided with a downward step part, the area ratio of the base island to the area ratio of the plastic package area is between 0.6: 1 and 0.7: 1, the gate electrode and the source electrode are connected to the respective corresponding connecting pins in a lead bonding manner, and the connecting pins are respectively provided with a glue groove. According to the scheme, the size proportion of the base islands is increased to achieve a better heat dissipation function, the situation that the base islands are layered due to the fact that the base islands are too large is avoided, the better waterproof and glue locking functions are achieved, meanwhile, the packaging cost is low, and the technology is simpler than that of a full-copper-sheet technology.

Description

Technical Field

[0001] The utility model relates to the technical field of dust removal, in particular to a large-size heat dissipation and double-groove waterproof MOS field effect tube chip packaging structure. Background Art

[0002] Power devices and third-generation semiconductors are the hot spots pursued by the current semiconductor industry technology and one of the fields of advanced semiconductor technology in the world. With the advent of the power semiconductor era, Clip Bond (all-copper sheet bonding) packaging technology can be said to be widely used. Compared with digital integrated circuits, power semiconductors do not simply pursue the reduction of line width, but have a long life cycle and a large market space. They can be applied to almost all electronic manufacturing industries, including industrial control, communications, consumer electronics, new energy, automobiles, rail transportation, smart grids, etc. In order to improve the yield and reliability of discrete devices, discrete device packaging and testing companies are developing more advanced packaging processes and packaging technologies for new products. In the entire electronic circuit field, MOS field-effect transistors are basically used in every circuit, with a wide range and large usage.

[0003] The existing MOS field effect tube chip packaging structure using traditional technology (Clip Bond) can refer to Fig.13 As shown, the MOS field effect tube chip packaging structure includes a lead frame 91, a base island 92 and pins located on the periphery of the base island 92 are provided in a single packaging area of ​​the lead frame 91, a single groove 93 is provided on the base island 92, a crystal grain 94 is bonded on the base island 92, a gate pad 95 and a source pad 96 are provided on the crystal grain 94, and the gate 95 and the source 96 are connected to the pins by a full copper sheet 97 bonding method. In the process of realizing the utility model, the applicant found that the packaging structure and process of the existing MOS field effect tube chip have at least the following problems:

[0004] 1. The connection method of the Gate Pad (gate 95) and the Source Pad (source 96) in the MOS field effect transistor chip is clip. This bonding method is costly and complex.

[0005] 2. Due to the differences in chip design among manufacturers, the size and area of ​​the Gate Pad are uncertain. If a Gate with an extremely small area is encountered, the positioning accuracy of Clip welding during the packaging process is insufficient, which may easily cause offset or make the Clip unusable.

[0006] 3. The area occupied by the base island 92 used is generally not too large. One point is that an overly large base island 92 will cause the bonding effect between the plastic package and the lead frame 91 to deteriorate during the application process (the single groove 93 has insufficient glue locking ability), so delamination will occur, resulting in chip failure.

[0007] In view of this, how to solve the above problems existing in the prior art has become the subject to be studied and solved by the present utility model. Utility Model Content

[0008] The utility model aims to provide a large-size heat dissipation and double-slot waterproof MOS field effect tube chip packaging structure, which is used to solve the problems existing in the packaging structure and process of the existing MOS field effect tube chip.

[0009] To achieve the above-mentioned purpose, the utility model proposes a large-size heat dissipation and double-slot waterproof MOS field effect tube chip packaging structure, the MOS field effect tube chip packaging structure includes a substrate and a plurality of packaging units arranged on the substrate, each packaging unit has a lead frame, a base island, connecting pins, and a plastic sealing part;

[0010] The lead frame has a plastic sealing area, the base island is arranged in the plastic sealing area, the lead frame has a plastic sealing line, and the front of the base island is provided with two glue grooves near the plastic sealing line; the back of the base island is provided with a downward step portion;

[0011] The area ratio of the base island to the area ratio of the plastic encapsulation area is between 0.6:1 and 0.7:1; a die is placed on the base island, and the die has a gate and a source;

[0012] A plurality of connecting pins are arranged on the periphery of the base island, the gate and the source are connected to the corresponding connecting pins by wire bonding, and each connecting pin is provided with a glue groove;

[0013] The plastic sealing part covers the plastic sealing area, and the plastic sealing part enters each glue groove and the step part located on the back side of the base island.

[0014] The relevant contents of this utility model are explained as follows:

[0015] 1. In the above technical solution of the utility model, the designed large-size heat dissipation and double-groove waterproof MOS field effect tube chip packaging structure can make the area occupied by the base island relatively large by designing two glue grooves on the front side of the base island and the step portion on the back side of the base island, so that the plastic sealing part can enter each glue groove and the step portion on the back side of the base island, thereby achieving the goal of increasing the base island size ratio to have a better heat dissipation function while avoiding the situation of stratification due to the base island being too large, and having better waterproof and glue locking functions. At the same time, the gate and source are connected to each connecting pin by wire bonding, so that the packaging cost is low, and the problem of small gate area due to the difference in chip design of each company is overcome. The process is simpler than the full copper sheet process.

[0016] 2. In the above technical solution, the shape of the glue groove is V-shaped, semicircular or rectangular, so that the plastic sealing layer can enter the glue groove well to play a role in locking the glue.

[0017] 3. In the above technical solution, the shape of the glue groove is V-shaped, and the angle between the two V-shaped surfaces is 60°.

[0018] 4. In the above technical solution, the depth of the glue groove is 0.03mm to 0.06mm.

[0019] 5. In the above technical solution, the bottom surface of the base island is a rough surface, so as to improve the adhesion of the adhesive and further avoid delamination.

[0020] 6. In the above technical solution, the plastic sealing lines are arranged on the periphery of the plastic sealing area in the horizontal and vertical directions.

[0021] 7. In the above technical solution, when the gate and source are connected by wire bonding, a local silver-plated area is provided in the area where the connecting pin is located, so as to improve the connection stability and reliability.

[0022] 8. In this utility model, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0023] 9. In the present utility model, the orientation or position relationship indicated by the terms "upper", "lower", "bottom", "inside", "outside", etc. is based on the orientation or position assembly relationship shown in the drawings, which is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application.

[0024] 10. In addition, in the description of the present invention, it should be noted that if the words "first", "second" and so on are used in this document to limit the components, those skilled in the art should know that the use of the words "first", "second" and so on is only for the convenience of describing the present invention and simplifying the description. If not otherwise stated, the above words have no special meaning.

[0025] Due to the application of the above scheme, the utility model has the following advantages and effects compared with the prior art:

[0026] 1. In the present invention, wire bonding is used to replace the original all-copper sheet bonding method, which has low packaging cost, overcomes the problem of chip design differences / small gate area among various companies, and is simpler in process than the all-copper sheet process.

[0027] 2. In the utility model, a double-groove waterproof design with two glue grooves is designed on the base island, which has better waterproof and glue locking functions.

[0028] 3. In the utility model, the area ratio of the designed base island to the area ratio of the plastic sealing area is between 0.6:1 and 0.7:1, and the size ratio is large. Under the premise of having the above-mentioned good glue locking function, the purpose of having a better heat dissipation function is achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 This is a schematic diagram of a MOS field effect transistor chip packaging structure according to an embodiment of the utility model;

[0030] Figure 2 This is a schematic diagram of a packaging unit in an embodiment of the utility model;

[0031] Figure 3 It is a three-dimensional schematic diagram of the base island, connecting pins and plastic sealing part in the embodiment of the utility model;

[0032] Figure 4 It is a plan view of the base island, connecting pins and plastic sealing part in the embodiment of the utility model;

[0033] Figure 5 for Figure 4 Schematic diagram of the AA section;

[0034] Figure 6 for Figure 5 A local enlarged schematic diagram in FIG.

[0035] Figure 7 It is a plan view of the base island and the connecting pins in the embodiment of the utility model;

[0036] Figure 8 It is a schematic diagram showing the invisible base island and connecting pins after the plastic sealing part is plastic sealed in the embodiment of the utility model;

[0037] Fig. 9 It is a three-dimensional schematic diagram of the base island and the connecting pins in the embodiment of the utility model;

[0038] Fig.10 It is a three-dimensional schematic diagram of the base island, connecting pins, and the back of the plastic sealing part in the embodiment of the utility model;

[0039] Fig.11 It is a three-dimensional schematic diagram of the back side of the base island and the connecting pins in the embodiment of the utility model;

[0040] Fig.12 This is a schematic diagram of a glue tank in an embodiment of the utility model;

[0041] Fig.13 This is a schematic diagram of the packaging structure of a MOS field effect transistor chip packaged using the traditional process (Clip Bond).

[0042] The various parts of the above drawings are shown as follows:

[0043] 100. Substrate;

[0044] 200, packaging unit;

[0045] 1. Lead frame;

[0046] 11. Plastic sealing area;

[0047] 12. Plastic sealing line;

[0048] 2. Base Island;

[0049] 21. Step part;

[0050] 3. Grain;

[0051] 31. Gate;

[0052] 32. Source;

[0053] 4. Connect the pins;

[0054] 5. Plastic sealing department;

[0055] 6. Lead wire;

[0056] 7. Glue slot;

[0057] 8. Partial silver-plated area;

[0058] 91. Lead frame;

[0059] 92. Key Island;

[0060] 93. Single slot;

[0061] 94. Grain;

[0062] 95. Gate;

[0063] 96. Source;

[0064] 97. Copper sheet. DETAILED DESCRIPTION

[0065] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are described in detail below in conjunction with the accompanying drawings. In the following description, many specific details are set forth to facilitate a full understanding of the present application. However, the present application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar improvements without violating the connotation of the present application, so the present application is not limited by the specific embodiments disclosed below.

[0066] The utility model discloses a large-size heat dissipation and double-slot waterproof MOS field effect tube chip packaging structure, such as Figure 1 As shown, the MOS field effect transistor chip packaging structure includes a substrate 100 and a plurality of packaging units 200 disposed on the substrate 100. Figure 2 As shown, each packaging unit 200 has a lead frame 1, a base island 2, connecting pins 4, and a plastic sealing portion 5;

[0067] The lead frame 1 has a plastic sealing area 11, the base island 2 is arranged in the plastic sealing area 11, the lead frame 1 has a plastic sealing line 12, and the front of the base island 2 is provided with two glue grooves 7 near the plastic sealing line 12; the back of the base island 2 is provided with a downward step portion 21;

[0068] The area ratio of the base island 2 to the area ratio of the plastic encapsulation area 11 is between 0.6:1 and 0.7:1; a die 3 is placed on the base island 2, and the die 3 has a gate 31 and a source 32;

[0069] A plurality of connecting pins 4 are arranged on the periphery of the base island 2, and the gate 31 and the source 32 are connected to the corresponding connecting pins 4 by wire bonding 6, and each connecting pin 4 is provided with a glue groove 7;

[0070] The plastic sealing portion 5 covers the plastic sealing area 11 , and the plastic sealing portion 5 enters each glue groove 7 and the step portion 21 located on the back side of the base island 2 .

[0071] In the embodiment of the utility model, the shape of the glue groove 7 is V-shaped, semicircular or rectangular, so that the plastic sealing layer can enter the glue groove 7 well to play a role in locking the glue. Specifically, the shape of the glue groove 7 is V-shaped, and the angle between the two V-shaped surfaces is 60°. Furthermore, the depth of the glue groove 7 is 0.03mm to 0.06mm.

[0072] In the embodiment of the present invention, the bottom surface of the base island 2 is a rough surface, so as to improve the adhesive adhesion and further avoid delamination.

[0073] In the embodiment of the utility model, the plastic sealing line 12 is arranged on the peripheral side of the plastic sealing area 11 in the horizontal direction and the vertical direction.

[0074] In the embodiment of the utility model, the gate 31 and the source 32 are connected by wire bonding 6 , and a local silver-plated area 8 is provided in the area where the connecting pin 4 is located, so as to improve the connection stability and reliability.

[0075] Through the implementation of the embodiment of the utility model, the designed large-size heat dissipation and double-groove waterproof MOS field effect tube chip packaging structure can make the base island 2 occupy a relatively large area by designing two glue grooves 7 on the front side of the base island 2 and the step portion 21 on the back side of the base island 2, so that the plastic sealing part 5 can enter the glue grooves 7 and the step portion 21 on the back side of the base island 2, thereby achieving the goal of increasing the size ratio of the base island 2 to have a better heat dissipation function while avoiding the situation where the base island 2 is too large and delamination occurs, and has better waterproof and glue locking functions. At the same time, the gate 31 and the source 32 are connected to each connecting pin 4 by wire bonding, so that the packaging cost is cheap, and the problem of small gate area due to the difference in chip design of each company is overcome. The process is simpler than the full copper sheet process.

[0076] Next, the structures of the embodiments of the present utility model will be described in detail according to the accompanying drawings.

[0077] like Figure 1 As shown, a large-size heat dissipation and double-slot waterproof MOS field effect tube chip packaging structure of the embodiment of the utility model comprises a substrate 100, and a plurality of packaging units 200 are arranged on the substrate 100. Figure 1 Only a portion of the packaging unit 200 is shown.

[0078] like Figure 2As shown, the package unit 200 of the embodiment of the utility model has a lead frame 1, a base island 2, a connecting pin 4, and a plastic sealing part 5. The lead frame 1 has a plastic sealing area 11, the base island 2 is arranged in the plastic sealing area 11, the lead frame 1 has a plastic sealing line 12, and the front of the base island 2 is provided with two glue grooves 7 near the plastic sealing line 12; the area occupied by the base island 2 accounts for more than 60% of the area occupied by the plastic sealing area 11, the base island 2 is placed on the die 3, and the die 3 has a gate 31 and a source 32; a plurality of the connecting pins 4 are arranged on the peripheral side of the base island 2, and the gate 31 and the source 32 are connected to the corresponding connecting pins 4 by wire bonding, and each of the connecting pins 4 is provided with a glue groove 7. The large area occupied by the base island 2 is used to improve heat dissipation, and the double groove design is used to ensure glue locking and avoid stratification.

[0079] like Figure 3 As shown, this is a schematic diagram of the packaging unit after plastic sealing, and the plastic sealing part 5 enters each glue groove 7 and the step part 21 located on the back side of the base island 2.

[0080] like Figure 4 , Figure 5 , Figure 6 As shown, after the plastic sealing is completed, the plastic sealing part 5 enters each glue groove 7 and the step part 21 located on the back of the base island 2 to ensure the glue locking. The step part 21 serves as a further guarantee measure to make the plastic sealing part 5 firm and reliable.

[0081] like Figure 7 As shown, two glue grooves 7 are provided on the front side of the base island 2 near the plastic sealing line 12, and each of the connecting pins 4 is provided with a glue groove 7. At the same time, the gate 31 and the source 32 are connected to the corresponding connecting pins 4 by bonding with wires 6. With this bonding method, the packaging cost is cheap and the process is simpler than the full copper sheet process. Even the problem of extremely small gate area can be overcome.

[0082] like Figure 8 , Fig. 9 As shown, Figure 8 1 is a schematic diagram showing the interior of the packaging unit after the plastic sealing part 5 is plastic sealed to the plastic sealing area 11 of the packaging unit with dotted lines. Fig. 9 It is a schematic diagram of the interior of the packaging unit after the plastic sealing part 5 is removed.

[0083] like Fig.10 and Fig.11 As shown, a downward step portion 21 is provided on the back side of the base island 2, so that the plastic sealing portion 5 can enter the facing surface of the step portion 21 after plastic sealing, so as to improve the glue locking ability.

[0084] like Fig.12As shown, the shape of the glue groove 7 is V-shaped, and the angle between the two V-shaped surfaces is 60°. The depth of the glue groove 7 is 0.03mm-0.06mm, and can be 0.03mm, 0.04mm, 0.05mm or 0.06mm.

[0085] The above embodiments are only for illustrating the technical concept and features of the utility model, and their purpose is to enable people familiar with the technology to understand the content of the utility model and implement it accordingly, and they cannot be used to limit the protection scope of the utility model. Any equivalent changes or modifications made according to the spirit of the utility model should be included in the protection scope of the utility model.

Claims

1. A large-size heat dissipation and double-slot waterproof MOS field effect tube chip packaging structure, characterized in that: The MOS field effect tube chip packaging structure comprises a substrate (100) and a plurality of packaging units (200) arranged on the substrate (100), each packaging unit (200) having a lead frame (1), a base island (2), a connecting pin (4), and a plastic sealing portion (5); The lead frame (1) has a plastic sealing area (11), the base island (2) is arranged in the plastic sealing area (11), the lead frame (1) has a plastic sealing line (12), and the front side of the base island (2) is provided with two glue grooves (7) at a position close to the plastic sealing line (12); the back side of the base island (2) is provided with a downward step portion (21); The area ratio of the base island (2) to the area ratio of the plastic sealing area (11) is between 0.6:1 and 0.7:1; a crystal grain (3) is placed on the base island (2), and the crystal grain (3) has a gate (31) and a source (32); A plurality of connecting pins (4) are arranged on the periphery of the base island (2); the gate (31) and the source (32) are connected to the corresponding connecting pins (4) by wire bonding; and each connecting pin (4) is provided with a glue groove (7); The plastic sealing part (5) covers the plastic sealing area (11), and the plastic sealing part (5) enters each glue groove (7) and the step part (21) located on the back side of the base island (2).

2. The large-size heat dissipation and double-slot waterproof MOS field effect tube chip packaging structure according to claim 1 is characterized in that: The shape of the glue groove (7) is V-shaped, semicircular or rectangular.

3. The large-size heat dissipation and double-slot waterproof MOS field effect tube chip packaging structure according to claim 1 is characterized in that: The shape of the glue groove (7) is V-shaped, and the angle at which two V-shaped surfaces intersect is 60°.

4. The large-size heat dissipation and double-slot waterproof MOS field effect tube chip packaging structure according to claim 3 is characterized in that: The depth of the glue groove (7) is 0.03 mm to 0.06 mm.

5. The large-size heat dissipation and double-slot waterproof MOS field effect tube chip packaging structure according to claim 1 is characterized in that: The bottom surface of the base island (2) is a rough surface.

6. The large-size heat dissipation and double-slot waterproof MOS field effect tube chip packaging structure according to claim 1 is characterized in that: The plastic sealing lines (12) are arranged on the periphery of the plastic sealing area (11) in the transverse direction and the vertical direction.

7. The large-size heat dissipation and double-slot waterproof MOS field effect tube chip packaging structure according to claim 1 is characterized in that: The area where the connecting pin (4) is located is connected to the gate (31) and the source (32) by wire bonding, and a local silver-plated area (8) is provided.

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