Protection circuit and fault detection circuit

Abstract

The utility model discloses a protection circuit and a fault detection circuit. The protection circuit and the fault detection circuit comprise an LM393 comparator, an SR latch CD4044B and a digital controller MCU. Four paths of input signals to be sampled of the LM393 comparator, namely bus input voltage, high-frequency input current, output voltage and inductive current, are respectively connected to the inverted input ends of the corresponding comparators; the in-phase input end of the LM393 comparator is provided with a reference signal input port, and the output end of the LM393 comparator is provided with an output port of a comparison result of a sampling signal and a reference signal threshold value. Under the condition that the circuit cost is not increased, circuit protection testing and fault detection are realized, so that the working reliability of the switching power supply is improved. The circuit is simple, low in cost and easy to implement; the multi-path protection effect can be effectively achieved, and the working reliability of the power supply is improved.

Description

Technical Field

[0001] The utility model relates to a protection and fault detection technology for a switching power supply, in particular to a protection circuit and a fault detection circuit. Background Art

[0002] With the continuous development of power electronics technology, switching power supplies have been widely used in a variety of industrial scenarios such as communications, aerospace, and car charging piles. In addition to meeting various indicators and basic electrical performance of the power supply, the protection and fault detection circuits of the switching power supply are also very important. At the same time, the development of digital power supplies is in the ascendant, and its position in the field of switching power supplies is becoming increasingly prominent. For digital power supplies, the functional scheduling of the control processor can further reliably protect the entire circuit and realize functions such as fault detection and recovery.

[0003] At present, the existing protection technology in switching power supplies mainly relies on the relevant pins of integrated IC chips to achieve overvoltage, overcurrent, overtemperature and other protection functions, which increases the difficulty of circuit parameter design. Another way is to rely on comparators to achieve protection and detection, but when the input signal is a high-frequency signal, its change cycle is very short, and the output of the comparator cannot be long-lasting.

[0004] There are two main methods for switching power supply protection and fault detection in the prior art:

[0005] Method 1: Use the relevant pins of the integrated IC chip and the peripheral circuit parameter design provided in the data sheet to achieve overvoltage, overcurrent, overtemperature and other protection functions. The overvoltage protection function is implemented by using the chip's voltage loop circuit and voltage feedback pin, and the overcurrent protection and overtemperature protection functions are implemented by detecting the voltage across the sampling resistor and thermistor of the relevant pins.

[0006] Method 2: The input signal is amplified through conditioning or voltage divider circuit, connected to the input of the comparator, and compared with the threshold voltage at the other end of the comparator. When it is higher than the threshold voltage, the comparator outputs a low level, and the comparator output is connected to the enable pin of the driver chip, thereby blocking PWM. At the same time, the control chip processor is used to detect the comparator output level to determine what kind of fault has occurred in the circuit.

[0007] The main disadvantages of the existing technology solutions are:

[0008] Regarding method 1: This method increases the circuit cost, and has relatively high requirements on the specific parameter design of circuit components, and the circuit design is also relatively complicated.

[0009] Regarding method 2: For high-frequency signals, the cycle of change is very short. When the circuit is protected, the comparator output becomes low, but when the input signal recovers to a level below the threshold, the comparator output will also become high. At this time, it may be impossible to completely block PWM, effectively protect the circuit, and detect what kind of fault has occurred in the circuit in time, thereby reducing the reliability of the power supply.

[0010] In view of this, the present utility model is proposed. Utility Model Content

[0011] The purpose of the utility model is to provide a protection circuit and a fault detection circuit to solve the above technical problems existing in the prior art.

[0012] The purpose of this utility model is achieved through the following technical solutions:

[0013] The protection circuit and fault detection circuit of the utility model include LM393 comparator, SR latch CD4044B, and digital controller MCU;

[0014] The four input signals to be sampled by the LM393 comparator: bus input voltage, high-frequency input current, output voltage, and inductor current are connected to the inverting input terminals of the corresponding comparators respectively;

[0015] The non-inverting input terminal of the LM393 comparator is provided with a reference signal input port, and the output terminal is provided with an output port for comparing the sampling signal with the reference signal threshold value.

[0016] Compared with the prior art, the protection circuit and fault detection circuit provided by the utility model are simple in circuit, low in cost and easy to implement; they can more effectively play a multi-channel protection role and improve the reliability of the power supply operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1a , Figure 1b , Figure 1c They are respectively a schematic diagram of the internal structure of CD4044B, a truth table of CD4044B, and a packaging diagram of CD4044B according to an embodiment of the utility model;

[0018] Figure 2 A schematic diagram of the protection circuit and fault detection circuit structure provided in an embodiment of the utility model. DETAILED DESCRIPTION

[0019] The following is a clear and complete description of the technical solutions in the embodiments of the utility model in conjunction with the drawings in the embodiments of the utility model; it is obvious that the described embodiments are only part of the embodiments of the utility model, not all of the embodiments, which does not constitute a limitation of the utility model. Based on the embodiments of the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the protection scope of the utility model.

[0020] First, the terms that may be used in this article are explained as follows:

[0021] The term “and / or” means that either or both of them can be realized at the same time. For example, X and / or Y means both “X” or “Y” and “X and Y”.

[0022] The terms "include", "comprises", "contains", "has" or other descriptions with similar semantics should be interpreted as non-exclusive inclusion. For example, including certain technical feature elements (such as raw materials, components, ingredients, carriers, dosage forms, materials, dimensions, parts, components, mechanisms, devices, steps, procedures, methods, reaction conditions, processing conditions, parameters, algorithms, signals, data, products or products, etc.) should be interpreted as including not only certain technical feature elements explicitly listed, but also other technical feature elements known in the art that are not explicitly listed.

[0023] The term "consisting of..." means excluding any technical feature elements not explicitly listed. If this term is used in a claim, it will make the claim closed, so that it does not contain technical feature elements other than those explicitly listed, except for conventional impurities related to them. If this term only appears in a clause of a claim, it only limits the elements explicitly listed in that clause, and the elements recorded in other clauses are not excluded from the overall claim.

[0024] The contents not described in detail in the examples of the present utility model belong to the prior art known to professionals in the field. If no specific conditions are specified in the examples of the present utility model, the conditions are carried out according to the conventional conditions in the field or the conditions recommended by the manufacturer. If the manufacturers of the reagents or instruments used in the examples of the present utility model are not specified, they are all conventional products that can be purchased commercially.

[0025] The protection circuit and fault detection circuit of the utility model include LM393 comparator, SR latch CD4044B, and digital controller MCU;

[0026] The four input signals to be sampled by the LM393 comparator: bus input voltage, high-frequency input current, output voltage, and inductor current are connected to the inverting input terminals of the corresponding comparators respectively;

[0027] The non-inverting input terminal of the LM393 comparator is provided with a reference signal input port, and the output terminal is provided with an output port for comparing the sampling signal with the reference signal threshold value.

[0028] The output ends of the LM393 comparator are connected to the reset ends R1, R2, R3, and R4 of the SR latch CD4044B respectively, and the corresponding output ends Q1, Q2, Q3, and Q4 of the SR latch CD4044B are connected to the output ends of the diode and the GPIO detection pins of the digital controller MCU respectively.

[0029] The four set terminals S1, S2, S3, and S4 of the SR latch CD4044B are connected to a GPIO pin of the digital controller MCU, and the anode of the diode is connected to the enable pin of the driver chip and the protection pin of the digital controller MCU.

[0030] In summary, the protection circuit and fault detection circuit of the embodiment of the utility model provide a more reliable and sensitive circuit protection test and realize fault detection without increasing the circuit cost, thereby improving the reliability of the switching power supply. The circuit is simple, low cost, and easy to implement; it can more effectively play a multi-channel protection role and improve the reliability of the power supply operation.

[0031] In order to more clearly demonstrate the technical solution and technical effects provided by the present invention, the embodiments of the present invention are described in detail with specific embodiments below.

[0032] Example 1

[0033] like Figure 1a , Figure 1b , Figure 1c As shown, this scheme adopts SR latch CD4044B. The internal structure of the latch (taking S1, R1, Q1 as an example) consists of two inverters and two NOR gates. When the reset terminal R1=1 and the set terminal S1=0, the NOR gate and the inverter work logic, and the output Q1 is 1; when the reset terminal R1=0 and the set terminal S1=1, the output Q1 is 0; when the reset terminal R1=1 and the set terminal S1=1, the output Q1 maintains the level of the previous moment; and when the reset terminal R1=0 and the set terminal S1=0, the output state is uncertain, so this situation should be avoided. From the above analysis, the truth table of SR latch CD4044B can be obtained as follows Figure 1a , Figure 1b , Figure 1c ), where E represents the enable pin of the latch, which is high effective. Q is the output state of the latch, Q* is the next state of the latch, that is, the state at the next moment, and NC represents "NO Change", that is, keeping the state unchanged. The schematic package of the SR latch CD4044B is shown as follows Figure 1a , Figure 1b , Figure 1c ), we can see that there are 4 outputs in a latch, so 4 signals can be controlled.

[0034] like Figure 2 As shown, the protection and detection circuit of this scheme sampling is mainly composed of LM393 comparator, SR latch CD4044B and digital controller MCU.

[0035] The function of the comparator LM393 is to connect the four input signals to be sampled: bus input voltage, high-frequency input current, output voltage, and inductor current to the inverting input of the corresponding comparator (one comparator is drawn in the figure, and the other comparators are of the same model and connection method, so they are omitted), and compare them with the reference signal at the inverting input of the corresponding comparator. If the sampled signal is lower than the reference signal threshold, the comparator outputs a high level. Similarly, if the sampled signal is higher than the reference signal threshold, the comparator outputs a low level. The output of the comparator is connected to the reset terminals R1, R2, R3, and R4 of the latch respectively, and the corresponding outputs Q1, Q2, Q3, and Q4 of the latch are connected to the output of the diode and the GPIO detection pin of the digital controller MCU respectively. The four set terminals S1, S2, S3, and S4 of the latch are connected to a GPIO pin of the MCU together, and the anode of the diode is connected to the enable pin of the driver chip and the protection pin of the MCU.

[0036] The circuit working principle and timing are as follows:

[0037] When the system is powered on, the set terminals S1, S2, S3, and S4 of the latch are initially at a high level due to the pull-up resistors, and the reset terminals R1, R2, R3, and R4 of the latch are also at a high level because the sampled input signal is lower than the reference signal threshold. At this time, the output terminals Q1, Q2, Q3, and Q4 of the latch are in a high-impedance state due to the uncertainty at the initial moment.

[0038] After the system MCU is initialized, Q1, Q2, Q3, and Q4 are configured as input pins, and S1, S2, S3, and S4 are set to low level. According to the truth table, the outputs of Q1, Q2, Q3, and Q4 are high level at this time. Use the MCU to detect whether Q1, Q2, Q3, and Q4 are all high level. If they are all high level, set S1, S2, S3, and S4 to high level, then the latch outputs Q1, Q2, Q3, and Q4 will maintain the high level output unchanged. If not all are high level, it means that the circuit has overcurrent or overvoltage protection, then the timing 3 (overcurrent protection) or timing 4 (overvoltage protection) operation is performed.

[0039] If the circuit has overcurrent protection at a certain moment, here taking high-frequency input current protection as an example, the comparator output R1 corresponding to the overcurrent protection becomes low. According to the truth table, Q1 output is also low. At this time, no matter how R1 changes, Q1 always outputs a low level. Figure 1a , Figure 1b , Figure 1c As shown, the anode of the diode will also be pulled low, and the protection pin of the MCU or the enable pin of the driver chip will be activated, blocking the PWM, and the switch tube will be cut off to play a protective role. After that, the MCU will enter the interrupt triggered by the protection, generate a fault flag, delay for a period of time, and clear the interrupt flag. At this time, R1 has recovered to a high level, and S1 is set to a low level, then the latch output Q1 is a high level, detect whether Q1 is a high level, set S1 to a high level, reset PWM, and restart the circuit.

[0040] If the circuit is over-voltage protected at a certain moment, here we take the DC bus input voltage protection as an example, then the comparator output R2 corresponding to the over-voltage protection becomes low, and according to the truth table, the Q2 output is also low, and the protection pin of the MCU or the driver chip enable pin is activated, blocking the PWM, and the switch tube is cut off, which plays a protective role. After that, the MCU will enter the interrupt triggered by the protection, generate an input voltage fault flag, delay for a period of time, clear the interrupt flag, detect the input voltage, if the input voltage is lower than the protection threshold, R2 has recovered to a high level, set S2 to a low level, and the latch output Q2 is a high level. Detect whether Q2 is a high level, set S2 to a high level, reset PWM, and restart the circuit.

[0041] The mechanisms of the other two protections are the same as those analyzed above and will not be elaborated here. From the above analysis, it can be seen that this scheme can play an effective role in circuit protection and detection.

[0042] The above is only a preferred specific implementation of the utility model, but the protection scope of the utility model is not limited thereto. Any changes or substitutions that can be easily thought of by any technician familiar with the technical field within the technical scope disclosed in the utility model should be included in the protection scope of the utility model. Therefore, the protection scope of the utility model should be based on the protection scope of the claims. The information disclosed in the background technology section of this article is only intended to deepen the understanding of the overall background technology of the utility model, and should not be regarded as an admission or in any form that the information constitutes prior art known to those skilled in the art.

Claims

1. A protection circuit and a fault detection circuit, characterized in that: Including LM393 comparator, SR latch CD4044B, digital controller MCU; The four input signals to be sampled by the LM393 comparator: bus input voltage, high-frequency input current, output voltage, and inductor current are connected to the inverting input terminals of the corresponding comparators respectively; The non-inverting input terminal of the LM393 comparator is provided with a reference signal input port, and the output terminal is provided with an output port for comparing the sampling signal with the reference signal threshold value.

2. The protection circuit and fault detection circuit according to claim 1, characterized in that: The output ends of the LM393 comparator are connected to the reset ends R1, R2, R3, and R4 of the SR latch CD4044B respectively, and the corresponding output ends Q1, Q2, Q3, and Q4 of the SR latch CD4044B are connected to the output ends of the diode and the GPIO detection pins of the digital controller MCU respectively.

3. The protection circuit and fault detection circuit according to claim 2, characterized in that: The four set terminals S1, S2, S3, and S4 of the SR latch CD4044B are connected to a GPIO pin of the digital controller MCU, and the anode of the diode is connected to the enable pin of the driver chip and the protection pin of the digital controller MCU.

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