Level shifter

Abstract

The utility model discloses a level shifter, which comprises a level shifter main body circuit and an RS latch circuit, the level shifter main body circuit is electrically connected with the RS latch circuit, the level shifter main body circuit comprises transistors P1-P6, transistors N1-N8, triodes B1-B2 and parasitic capacitors C1-C2, and the RS latch circuit is electrically connected with the transistors P1-P6, the transistors N1-N8, the triodes B1-B2 and the parasitic capacitors C1-C2. One path of the signal HSDRLV is connected with the grid electrode of the transistor N1 through the phase inverter, the other path of the signal HSDRLV is directly connected with the grid electrode of the transistor N2, and the source electrode of the transistor N1 and the source electrode of the transistor N2 are both connected with GND; the level shifter disclosed by the utility model realizes the conversion from a low-voltage signal in a fixed power supply domain to a high-voltage high-speed clock power supply domain, so that a correct signal is more correct, an error signal cannot enter a final control signal, the abnormal working of the whole circuit is avoided, and particularly, the switching error of a power tube is avoided; and the high-end power tube and the low-end power tube are communicated.

Description

Technical Field

[0001] The utility model belongs to the technical field of level conversion, and in particular relates to a level converter. Background Art

[0002] In recent years, the demand for power IC has skyrocketed, especially the need for domestic substitution. Many domestic companies have launched power chips. These power chips often contain switch tubes, and almost all of these switch tubes involve the design of high-end tubes. High-end tubes will use pmos or nmos. Since the electron mobility of nmos is greater than the mobility of pmos, the area of ​​nmos will be smaller under the same on-resistance. Under the same area, the on-resistance of nmos will be smaller, and the efficiency of the power chip will be higher. Therefore, most products tend to use nmos tubes. However, when the nmos tube is switched, the source end is often a high-voltage pulse, and the drain end is the input power supply. Then the gate end needs to generate a higher voltage than the source to conduct. Therefore, the gate end voltage is generally based on the source voltage to achieve self-bootstrapping. When the source voltage is high, the gate needs to be higher to fully open the nmos. When the source is low, the gate is also low, so that the nmos is cut off.

[0003] Therefore, a high-voltage and high-speed clock power domain is required at the gate end. In the process of switching such power domains, error signals are often sent, causing the power switch to enter an abnormal state, which may cause abnormal operation at the least or burn out due to the high- and low-end power tubes being connected.

[0004] Therefore, further improvements are made to the above problems. Utility Model Content

[0005] The main purpose of the utility model is to provide a level converter, which is designed with a compensation (offset) level converter to achieve the conversion from a low-voltage signal in a fixed power domain to a high-voltage and high-speed clock power domain, so that the correct signal is more correct, and the wrong signal cannot enter the final control signal, thereby avoiding the abnormal operation of the entire circuit, especially avoiding the risk of power tube switching errors, resulting in the high-end and low-end power tube penetration.

[0006] To achieve the above object, the utility model provides a level converter, including a level conversion main circuit and an RS latch circuit, wherein the level conversion main circuit and the RS latch circuit are electrically connected, and the level conversion main circuit includes transistors P1-P6, transistors N1-N8, triodes B1-B2 and parasitic capacitors C1-C2, wherein:

[0007] The signal HS_DR_LV is connected to the gate of the transistor N1 through an inverter and directly connected to the gate of the transistor N2 in another way. The source of the transistor N1 and the source of the transistor N2 are both connected to GND; the drain of the transistor N1 is connected to the source of the transistor N3 and the drain of the transistor N2 is connected to the source of the transistor N4. The gate of the transistor N3 and the gate of the transistor N4 are both connected to VDD;

[0008] The collectors of transistors B1 and B2 and the sources of transistors P1-P6 are all connected to BST, the base of transistor B1 and the base of transistor B2 are all connected to SW, the drain of transistor P2, the emitter of transistor B1 and one end of parasitic capacitor C1 are respectively connected to the drain of transistor N4, the drain of transistor P1, the emitter of transistor B2 and one end of parasitic capacitor C2 are respectively connected to the drain of transistor N3; the gate of transistor P3 and the gate of transistor P6 are respectively connected to the drain of transistor N3, the gate of transistor P4 and the gate of transistor P5 are respectively connected to the drain of transistor N4, the drain of transistor P3 is connected to the drain of transistor N5, the drain of transistor P4 is connected to the drain of transistor N6, the drain of transistor P5 is connected to the drain of transistor N7, and the drain of transistor P6 is connected to the drain of transistor N8;

[0009] The transistor P4 includes a transistor P4.1 and a transistor P4.2 connected in parallel, and the transistor P6 includes a transistor P6.1 and a transistor P6.2 connected in parallel;

[0010] The gate of transistor N5 is connected to the gate of transistor N6, the gate of transistor N7 is connected to the gate of transistor N8, the sources of transistors N5-N8 are connected to SW respectively, the drain of transistor N6 is connected to the output terminal HS_DR_PRE and the drain of transistor N8 is connected to the output terminal HS_DRB_PRE;

[0011] The output terminal HS_DR_PRE is connected to a first input terminal of the RS latch circuit and the output terminal HS_DRB_PRE is connected to a second input terminal of the RS latch circuit. The output terminal of the RS latch circuit is connected to the signal HS_DR_HV.

[0012] As a further preferred technical solution of the above technical solution, the gate and drain of the transistor P1 are connected, and the gate and drain of the transistor P2 are connected.

[0013] As a further preferred technical solution of the above technical solution, the other end of the parasitic capacitor C1 and the other end of the parasitic capacitor C2 are both connected to GND.

[0014] As a further preferred technical solution of the above technical solution, the gate and drain of the transistor N5 are connected, and the gate and drain of the transistor N7 are connected.

[0015] As a further preferred technical solution of the above technical solution, the drain of transistor N3 is connected to node A, and the drain of transistor N4 is connected to node B. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 The utility model discloses a level conversion main circuit diagram of a level converter.

[0017] Figure 2 The utility model discloses an RS latch circuit diagram of a level converter.

[0018] Figure 3 This is the application circuit diagram of the level converter.

[0019] Figure 4 This is a timing diagram of a level converter of the utility model. DETAILED DESCRIPTION

[0020] The following description is used to disclose the utility model so that those skilled in the art can implement the utility model. The preferred embodiments described below are only examples, and those skilled in the art can think of other obvious variations. The basic principles of the utility model defined in the following description can be applied to other embodiments, variations, improvements, equivalents, and other technical solutions that do not deviate from the spirit and scope of the utility model.

[0021] The utility model discloses a level converter. The specific embodiments of the utility model are further described below in conjunction with preferred embodiments.

[0022] In the embodiments of the present invention, those skilled in the art note that the GND and the like involved in the present invention may be regarded as prior art.

[0023] Preferred embodiments.

[0024] The utility model discloses a level converter, comprising a level conversion main circuit and an RS latch circuit, wherein the level conversion main circuit and the RS latch circuit are electrically connected, and the level conversion main circuit comprises transistors P1-P6, transistors N1-N8, triodes B1-B2 and parasitic capacitors C1-C2, wherein:

[0025] The signal HS_DR_LV is connected to the gate of the transistor N1 through an inverter and directly connected to the gate of the transistor N2 in another way. The source of the transistor N1 and the source of the transistor N2 are both connected to GND; the drain of the transistor N1 is connected to the source of the transistor N3 and the drain of the transistor N2 is connected to the source of the transistor N4. The gate of the transistor N3 and the gate of the transistor N4 are both connected to VDD;

[0026] The collectors of transistors B1 and B2 and the sources of transistors P1-P6 are all connected to BST, the base of transistor B1 and the base of transistor B2 are all connected to SW, the drain of transistor P2, the emitter of transistor B1 and one end of parasitic capacitor C1 are respectively connected to the drain of transistor N4, the drain of transistor P1, the emitter of transistor B2 and one end of parasitic capacitor C2 are respectively connected to the drain of transistor N3; the gate of transistor P3 and the gate of transistor P6 are respectively connected to the drain of transistor N3, the gate of transistor P4 and the gate of transistor P5 are respectively connected to the drain of transistor N4, the drain of transistor P3 is connected to the drain of transistor N5, the drain of transistor P4 is connected to the drain of transistor N6, the drain of transistor P5 is connected to the drain of transistor N7, and the drain of transistor P6 is connected to the drain of transistor N8;

[0027] The transistor P4 includes a transistor P4.1 and a transistor P4.2 connected in parallel, and the transistor P6 includes a transistor P6.1 and a transistor P6.2 connected in parallel;

[0028] The gate of transistor N5 is connected to the gate of transistor N6, the gate of transistor N7 is connected to the gate of transistor N8, the sources of transistors N5-N8 are connected to SW respectively, the drain of transistor N6 is connected to the output terminal HS_DR_PRE and the drain of transistor N8 is connected to the output terminal HS_DRB_PRE;

[0029] The output terminal HS_DR_PRE is connected to a first input terminal of the RS latch circuit and the output terminal HS_DRB_PRE is connected to a second input terminal of the RS latch circuit. The output terminal of the RS latch circuit is connected to the signal HS_DR_HV.

[0030] Specifically, the gate and drain of the transistor P1 are connected, and the gate and drain of the transistor P2 are connected.

[0031] More specifically, the other end of the parasitic capacitor C1 and the other end of the parasitic capacitor C2 are both connected to GND.

[0032] Furthermore, the gate and drain of the transistor N5 are connected, and the gate and drain of the transistor N7 are connected.

[0033] Furthermore, the drain of the transistor N3 is connected to the node A, and the drain of the transistor N4 is connected to the node B.

[0034] For this utility model:

[0035] like Figure 3 As shown in the figure, the gate power domain of the high-side tube (HS for short) is BST-SW, and the gate power domain of the low-side tube (LS for short) is VDD-GND.

[0036] When LS is turned on, HS is turned off, and when HS is turned on, LS is turned off. It can be understood as a single-pole double-throw switch.

[0037] When LS is turned on, SW is pulled down to GND, and 5V VDD charges the charging capacitor Ccharge through the Schottky diode Sdio. The voltage drop of Sdio is very low and can be considered close to 0V, so the upper plate BST of Ccharge is also 5V. When LS is turned off and HS is turned on, SW is charged from 0V to VIN 100V. Since the voltage across the capacitor cannot change suddenly, the upper plate BST of Ccharge becomes 105V. Since Sdio is reversely cut off at this time, BST will not be backflowed to VDD. This is a simple bootstrap circuit that bootstraps BST based on the SW signal. The actual bootstrap circuit implementation may be more complicated, which is not the focus of the present invention. This part is only explained in principle. Therefore, the BST power supply is a jumping clock power supply, but the voltage difference between BST and SW is maintained at 5V, and the low-voltage part VDD is a stable 5V power supply. Then only the driving part of HS is the high-voltage and high-speed clock power domain BST-SW, and the front-stage signal processing part must be a fixed low-voltage power domain. A level converter level shift must be used between these two power domains.

[0038] like Figure 1-2As shown in the figure, the main structure of the designed level converter with offset comparison is shown. The HS low-voltage drive signal is HS_DR_LV, and its power domain is VDD-GND, for example, VDD is a fixed 5V level. HS_DR_LV directly controls N2, and HS_DR_LV controls N1 through an inverter. N1 and N2 are low-voltage 5V NMOS tubes, and the number of transistors N1:N2=1:1. N3 and N4 are high-voltage NMOS tubes, and the gate is connected to VDD. Because their drains are in the BST-SW power domain, the drains must withstand high voltages, and the number of transistors N3:N4=1:1. P1 and P2 are low-voltage 5V PMOS tubes, because when only considering the gate-source-drain three-terminal device, their ports are both in the BST-SW power domain, and although BST and SW are high-voltage and high-speed clock power supplies, the voltage difference between BST and SW is fixed at 5V, and the number of transistors P1:P2=1:1. B1 and B2 are NPN transistors, which mainly clamp the voltage of the AB nodes to not be lower than SW. At the same time, they also have the function of quickly pulling up to BST, because when AB is low, B1 and B2 will be turned on. C1 and C2 are parasitic capacitors during layout implementation, including parasitic capacitance of the connection and capacitance of the device port, and the main parasitic capacitance comes from the drain of N3 and N4. The drain of such high-voltage devices often has a large parasitic capacitance to the ground, that is, a large high-voltage capacitance of the high-voltage signal to the ground. It is precisely because of the existence of such capacitance that the entire level shift may be abnormal, which is also the problem to be solved in this design. The AB node enters the post-stage comparison stage, P3, P4, P5, and P6 are 5V PMOS, N5, N6, N7, and N8 are 5V NMOS, and the power domain is already BST-SW. Under normal circumstances, only the number of transistors P3: P4: P5: P6 = 1: 1: 1: 1 is needed, and as a current mirror N5: N6: N7: N8 = 1: 1: 1: 1, the nmos current mirror is generally fixed. Then HS_DR_PRE can be used as HS_DR_HV, but there are huge risks.

[0039] When HS_DR_LV is high, N2 is turned on, and its drain is pulled down close to GND. Then the gate of N4 is connected to VDD, so N4 will also be turned on, pulling the B node down to SW. The lowest voltage is clamped by B1, and N1 is not turned on, so naturally N3 is not turned on, and the A node is close to BST. Therefore, HS_DR_PRE is high and HS_DRB_PRE is low, both relative to SW, because this is already the BST-SW power domain. It seems to work normally in principle. However, it is ignored that BST is a jumping clock power supply, and C1 and C2 may not be naturally equal. When BST rises or falls quickly, due to the presence of high-voltage large capacitors C1 and C2, BST does not charge the AB node in time. The higher the BST voltage, the faster the rise and fall, the larger the parasitic C1 and C2 capacitors, and the greater the risk of sending an erroneous signal.

[0040] Therefore, the present invention sets the number of transistors to P3:P4:P5:P6=1:2:1:2; in general, the high-level HS_DR_LV generates a high-level HS_DR_HV through level shift, and then generates a high-level HS_DR through driving, and then the HS is turned on, and the SW is then increased. The voltage difference between BST and SW remains fixed, so BST also increases accordingly. In this synchronous relationship, the relationship between HS_DR_LV and BST is synchronous, and the timing is also determined. Then analyze this situation first, such as Figure 3 That is, when the high level of HS_DR_LV encounters the rising edge of BST, and when the low level of HS_DR_LV encounters the falling edge of BST.

[0041] like Figure 1 , the pmos input pair of the final comparator of the level shift is offset, and P3:P4:P5:P6=1:2:1:2 is set, and the nmos current mirror is proportional. Under normal circumstances, the rising edge of BST comes after HS_DR_LV becomes high. Due to the parasitic capacitance of both AB nodes, node B is pulled low, and node A cannot keep up with the rapid rise of BST, resulting in node A being at a low level relative to SW when it should be at a high level relative to SW. In this case, the comparator without offset may produce an erroneous signal. Now the circuit is offset (that is, P3:P4:P5:P6=1:2:1:2 is set), HS_DR_PRE is more likely to remain at a high level in this case, but HS_DRB_PRE is more likely to cause erroneous spike pulses. The falling edge of SW comes after HS_DR_LV becomes low, point B is still at a high level, and point A is still pulled low, so HS_DR_PRE is kept at a low level and HS_DRB_PRE is kept at a high level. Then the erroneous state of HS_DRB_PRE is filtered by the subsequent RS latch. When the inputs are all 1, that is, HS_DR_PRE and HS_DRB_PRE are both in the high level state, the LS_DR_HV output by the RS latch is in the hold state, and the erroneous state will not enter the final HS_DR, thereby affecting the switching of HS.

[0042] However, the above synchronization relationship is based on the rising edge of SW being controlled by HS_DR, resulting in a synchronization relationship between HS_DR_LV and BST in terms of timing. In some special applications, SW is not controlled by HS_DR, such as light-load FPWM applications. At this time, the inductor current can flow in reverse. LS is turned on at the beginning, and SW is low. When LS is turned off, due to the dead time setting of anti-shoot-through, HS is also turned off. Since the inductor current cannot change suddenly, the body diode of HS will turn on, and SW will be one diode drop higher than VIN. Therefore, SW is not controlled by HS_DR_LV at this time, and the previous synchronization timing relationship has changed.

[0043] According to the above description, the low level of HS_DR_LV will also encounter the rising edge of BST. This phenomenon is actually consistent with the synchronous BOOST DCDC application. This part is only a theoretical explanation. This timing analysis is similar to the above. The waveform and Figure 4 It is a similar deduction, except that the relationship between points AB is swapped. When HS_DR_LV is at a low level, node A is pulled low and node B is close to BST. When encountering the rising edge of BST at this time, node A is stably pulled low, and node B cannot keep up with the rapid rise of BST, resulting in a low level relative to SW. The offset of the subsequent stage is more inclined to cause HS_DR_PRE to change from low to high, and the offset makes HS_DRB_PRE easier to stabilize at a high level. Therefore, the direction is swapped with the previous one, and HS_DR_PRE is more susceptible to interference and sends out an error signal. However, due to the existence of the subsequent RS latch, when the input is at a high level at the same time, the RS latch is in a held state, and the wrong state will not enter the final HS_DR, thereby affecting the switching of HS.

[0044] In summary, the designed level converter with offset realizes the conversion from the fixed power domain low voltage signal to the high voltage and high speed clock power domain, making the correct signal more correct, and the wrong signal cannot enter the final control signal, avoiding the abnormal operation of the entire circuit, especially avoiding the risk of power tube switch error leading to the high and low end power tube through. The utility model is illustrated on the synchronous BUCK, but the same design method can be extended to various power tube control designs.

[0045] It is worth mentioning that the technical features such as GND involved in this utility model patent application should be regarded as prior art. The specific structure, working principle and possible control method and spatial layout method of these technical features can be selected by conventional methods in the field and should not be regarded as the invention point of this utility model patent. This utility model patent will not be further elaborated.

[0046] For those skilled in the art, it is still possible to modify the technical solutions described in the aforementioned embodiments, or to make equivalent substitutions for some of the technical features therein. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present utility model should be included in the protection scope of the present utility model.

Claims

1. A level converter, characterized in that: It includes a level conversion main circuit and an RS latch circuit, the level conversion main circuit and the RS latch circuit are electrically connected, the level conversion main circuit includes transistors P1-P6, transistors N1-N8, triodes B1-B2 and parasitic capacitors C1-C2, wherein: The signal HS_DR_LV is connected to the gate of the transistor N1 through an inverter and directly connected to the gate of the transistor N2 in another way. The source of the transistor N1 and the source of the transistor N2 are both connected to GND; the drain of the transistor N1 is connected to the source of the transistor N3 and the drain of the transistor N2 is connected to the source of the transistor N4. The gate of the transistor N3 and the gate of the transistor N4 are both connected to VDD; The collectors of transistors B1 and B2 and the sources of transistors P1-P6 are all connected to BST, the base of transistor B1 and the base of transistor B2 are all connected to SW, the drain of transistor P2, the emitter of transistor B1 and one end of parasitic capacitor C1 are respectively connected to the drain of transistor N4, the drain of transistor P1, the emitter of transistor B2 and one end of parasitic capacitor C2 are respectively connected to the drain of transistor N3; the gate of transistor P3 and the gate of transistor P6 are respectively connected to the drain of transistor N3, the gate of transistor P4 and the gate of transistor P5 are respectively connected to the drain of transistor N4, the drain of transistor P3 is connected to the drain of transistor N5, the drain of transistor P4 is connected to the drain of transistor N6, the drain of transistor P5 is connected to the drain of transistor N7, and the drain of transistor P6 is connected to the drain of transistor N8; The transistor P4 includes a transistor P4.1 and a transistor P4.2 connected in parallel, and the transistor P6 includes a transistor P6.1 and a transistor P6.2 connected in parallel; The gate of transistor N5 is connected to the gate of transistor N6, the gate of transistor N7 is connected to the gate of transistor N8, the sources of transistors N5-N8 are connected to SW respectively, the drain of transistor N6 is connected to the output terminal HS_DR_PRE and the drain of transistor N8 is connected to the output terminal HS_DRB_PRE; The output terminal HS_DR_PRE is connected to a first input terminal of the RS latch circuit and the output terminal HS_DRB_PRE is connected to a second input terminal of the RS latch circuit. The output terminal of the RS latch circuit is connected to the signal HS_DR_HV.

2. A level converter according to claim 1, characterized in that: The gate and drain of the transistor P1 are connected, and the gate and drain of the transistor P2 are connected.

3. A level converter according to claim 2, characterized in that: The other end of the parasitic capacitor C1 and the other end of the parasitic capacitor C2 are both connected to GND.

4. A level converter according to claim 3, characterized in that: The gate and drain of the transistor N5 are connected, and the gate and drain of the transistor N7 are connected.

5. A level converter according to claim 4, characterized in that: The drain of the transistor N3 is connected to the node A, and the drain of the transistor N4 is connected to the node B.

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