IGBT (Insulated Gate Bipolar Translator) testing device

Abstract

The utility model relates to an IGBT testing device, the testing device comprises a control panel, a DC power supply 1, a DC power supply 2 and a touch screen, the DC power supply 1 is used for supplying power to the control panel and the touch screen, the DC power supply 2 is used for supplying power to a unit to be tested, and the control panel comprises an FPGA 1, a driving chip 1, a driving chip 2, an optical fiber interface and an RS485 chip. The first FPGA is connected with the RS485 chip through a corresponding pin, and the RS485 chip is used for being connected with a touch screen through a port. The utility model has the advantages that the power unit does not need to be disassembled, only the POF optical fiber interface or the ST optical fiber interface in the control panel is needed to be connected with the three-level power unit or the IGBT module provided by a manufacturer, the control panel is connected with the touch screen through the RS485 chip, and a tester can check test data at any time through the touch screen visually and conveniently; the direct current side of the APF is connected in series through the switches K1 and K2, and the alternating current side of the APF is connected with the center taps of the switches K1 and K2 through the corresponding switches, so that the safety of the unit to be tested is improved.

Description

Technical Field

[0001] The utility model relates to the field of power electronic device testing devices, in particular to an IGBT testing device. Background Art

[0002] With the development of power electronics technology, IGBT modules in the power units of SVG and APF control devices have been widely used. However, the parameters in the IGBT module specification are test data under specific conditions and may not represent the actual performance in actual applications. To combine with actual application conditions, it is necessary to test the performance of IGBT.

[0003] In the power unit of the existing SVG and APF control devices, the IGBT and the unit control board are installed and integrated. The workshop test is to disassemble the power unit, take out some IGBTs in the power unit for pulse testing in a random sampling manner, and then restore the power unit after the test. The operation is cumbersome and misconnection is prone to occur during the power unit restoration process. In addition, for the IGBT modules directly provided by the manufacturer, since the IGBT modules are already packaged, it is not convenient to disassemble them. The parameters in the manufacturer's technical manual also need to be further confirmed and tested. Therefore, an IGBT testing device is urgently needed. Summary of the invention

[0004] The utility model aims to provide an IGBT testing device, which does not require disassembling a power unit, improves testing safety, is simple to operate, and is easy to move.

[0005] To achieve the above purpose, the utility model is implemented through the following technical solutions:

[0006] An IGBT test device, the test device is connected to a unit to be tested, the test device comprises a control board, a DC power supply 1, a DC power supply 2, and a touch screen, the DC power supply 1 is used to supply power to the control board and the touch screen, the DC power supply 2 is used to supply power to the unit to be tested, the control board comprises an FPGA 1, a driver chip 1, a driver chip 2, an optical fiber interface, and an RS485 chip, the FPGA 1 is connected to the RS485 chip through corresponding pins, and the RS485 chip is used to connect to the touch screen through a port;

[0007] FPGA 1 is connected to the unit under test through an optical fiber interface, and the optical fiber interface includes a receiving optical fiber seat 1, a transmitting optical fiber seat 1, a receiving optical fiber seat 2, and a transmitting optical fiber seat 2. FPGA 1 is connected to the receiving optical fiber seat 1 through corresponding pins, FPGA 1 is connected to the input end of the driver chip 1 through corresponding pins, the output end of the driver chip 1 is connected to the transmitting optical fiber seat 1, FPGA 1 is connected to the input end of the driver chip 2 through corresponding pins, and the output end of the driver chip 2 is respectively connected to the receiving optical fiber seat 2 and the transmitting optical fiber seat 2 through corresponding pins.

[0008] The unit to be tested includes a three-level power unit, the three-level power unit includes a power unit board and a power unit, and the power unit board is connected to the power unit.

[0009] The power unit board includes DSP, FPGA2, ADC chip, and several gate drive chips. The DSP is connected to FPGA2 through corresponding pins, the control board is connected to FPGA2 through an optical fiber interface, the output end of the ADC chip is connected to FPGA2 through corresponding pins, the input end of the ADC chip is used to collect the voltage / current signal of the PWM modulated output of the IGBT, the input end of the gate drive chip is connected to FPGA2 through corresponding pins, and the output end of the gate drive chip is respectively connected to the PWM control end of the corresponding IGBT.

[0010] The power unit includes a diode midpoint clamped APF composed of multiple IGBTs and multiple diodes. The DC side of the APF is connected in series through capacitors C1 and C2. The DC side of the APF is also connected in series through switches K1 and K2. The APF is connected to the middle tap of capacitors C1 and C2 through the midpoint of the series connection. The AC side of the APF is connected to the middle tap of switches K1 and K2 through corresponding inductors and corresponding switches connected in series. DC power supply 2 is used to power the DC side of the APF.

[0011] The unit under test also includes an IGBT module, which includes a driver core board, a driver adapter board, and an IGBT. The driver core board is connected to the input end of the driver adapter board, and the output end of the driver adapter board is connected to the IGBT. DC power supply 2 is used to power the IGBT. An optical fiber interface is provided on the driver core board, and the control board is connected to FPGA 1 through the optical fiber interface.

[0012] The FPGA chip model is 10CL016YE144I7, the driver chip model is 74LCX00, and the driver chip model is SN74LVC2T245.

[0013] The FPGA chip model is AG10KL144H, the DSP chip model is ADSP21488, and the gate drive chip model is IR2184SPBF.

[0014] Compared with the prior art, the beneficial effects of the utility model are:

[0015] 1. No need to disassemble the power unit, just connect it to the three-level power unit or the IGBT module provided by the manufacturer through the POF fiber optic interface or ST fiber optic interface in the control board. The control board is connected to the touch screen through the RS485 chip. The tester can view the test data at any time through the touch screen, which is intuitive and convenient.

[0016] 2. The DC side of the APF is connected in series through switches K1 and K2, and the AC side of the APF is connected in series through the corresponding reactors and the corresponding switches connected to the middle taps of switches K1 and K2. The switch is used to disconnect the DC side from the unit under test, which improves the safety of the unit under test and ensures the personal safety of the tester;

[0017] 3. The FPGA in the control board is equipped with a POF optical fiber interface and an ST optical fiber interface. On the basis of isolating the control board and the unit, it can be connected to any IGBT in the three-level power unit for testing after photoelectric conversion. The operation is simple and easy to implement.

[0018] 4. FPGA is connected to the input end of the ST driver chip, and the output end of the ST driver chip is connected to the ST transmitting fiber holder. FPGA is connected to the input end of the POF driver chip, and the output end of the POF driver chip is respectively connected to the POF receiving fiber holder and the POF transmitting fiber holder. The test interface of ST fiber and POF fiber is provided for the power modules of other manufacturers with IGBT package, and the IGBT finished modules are tested. The structure is simple and easy to promote. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 It is a structural diagram of the IGBT test device.

[0020] Figure 2 It is a schematic diagram of the structure of the control board and the three-level power unit test device.

[0021] Figure 3 It is a schematic diagram of the structure of the control board and IGBT module test device.

[0022] Figure 4 It is a schematic diagram of the control panel structure.

[0023] Figure 5 It is a schematic diagram of the structure of a three-level power unit board. DETAILED DESCRIPTION

[0024] The present invention is described in detail below in conjunction with the accompanying drawings of the specification, but it should be noted that the implementation of the present invention is not limited to the following embodiments.

[0025] The following examples are implemented based on the technical solution of the utility model, and provide detailed implementation methods and specific operation processes, but the protection scope of the utility model is not limited to the following examples. The methods used in the following examples are conventional methods unless otherwise specified.

[0026] [Example 1]

[0027] See Figure 1 ,See Figure 4, an IGBT test device, the test device is connected to a unit to be tested, the test device includes a control board, a DC power supply 1, a DC power supply 2, and a touch screen, the test device is arranged on a test bench, the DC power supply 1 is used to power the control board and the touch screen, the DC power supply 2 is 0-8000V, and is used to power the unit to be tested, the control board includes an FPGA 1, an ST driver chip, a POF driver chip, an optical fiber interface, and an RS485 chip, the FPGA 1 chip model is 10CL016YE144I7, the FPGA 1 is connected to the RS485 chip through corresponding pins, the RS485 chip is used to connect to the touch screen through a port, and the parameters of the control board can be monitored through the touch screen; the FPGA 1 in the control board can be connected to the three-level power unit to be tested through the POF optical fiber or the ST optical fiber, and can be connected to the manufacturer's finished IGBT module to be tested through the ST optical fiber.

[0028] FPGA is connected to the unit under test through an optical fiber interface. The optical fiber interface includes an ST receiving optical fiber seat, an ST transmitting optical fiber seat, a POF receiving optical fiber seat, and a POF transmitting optical fiber seat. FPGA is connected to the ST receiving optical fiber seat through corresponding pins. FPGA is connected to the input end of the ST driver chip through corresponding pins. The output end of the ST driver chip is connected to the ST transmitting optical fiber seat. FPGA is connected to the input end of the POF driver chip through corresponding pins. The output end of the POF driver chip is respectively connected to the POF receiving optical fiber seat and the POF transmitting optical fiber seat through corresponding pins. The ST driver chip model is 74LCX00, and the POF driver chip model is SN74LVC2T245. The pins of the ST and POF optical fiber sockets are shown in Table 1.

[0029] Table 1 shows the ST and POF fiber optic socket pins.

[0030]

[0031] [Example 2]

[0032] In this embodiment, an IGBT test device is the same as that in Embodiment 1, and a unit to be tested is added thereto: a three-level power unit, see Figure 2 , the three-level power unit includes a power unit board and a power unit.

[0033] See Figure 5The power unit board includes DSP, FPGA II, ADC chip, and twelve gate drive chips. The FPGA II chip model is AG10KL144H, the DSP chip model is ADSP21488, and the gate drive chip model is IR2184SPBF. The DSP chip power supply is 3.3V and 1.1V, and the FPGA chip power supply is 3.3V, 2.5V, and 1.2V. The DSP chip realizes RS485 communication through ADM2687, and the DSP chip realizes CAN communication through MCP2515. The cascade communication between the unit modules is carried out through the optical fiber interface, RS485 interface, and CAN interface. The DSP is connected to the FPGA II through the corresponding pins, and the control board is connected to the FPGA II through the optical fiber interface. The FPGA II is used to drive the IGBT through the gate drive chip to complete various pulse tests and verify the performance of the IGBT; the FPGA II is connected to the ADC chip through the SPI bus, which is used for high-speed timing cycle sampling of the voltage and current data in the 16-way power grid; the input end of the ADC chip is used to collect the voltage / current signal output by the PWM modulation of the IGBT, and compensate the power grid after passing through the reactor. The signal collected by ADC is the grid current signal which is filtered and scaled down to 0-10V, collected by AD7616 and then input into FPGA and DSP; the input end of the gate drive chip is connected to FPGA 2 through the corresponding pin; the input end of the gate drive chip is connected to FPGA 2 through the corresponding pin, and the output end of the gate drive chip is respectively connected to the PWM control end of the corresponding IGBT: the output ends PWM-A1 to PWMA4 of gate drive chips 1 to 4 are respectively connected to the control ends of A-phase IGBT1 to IGBT4, the output ends PWM-B1 to PWMB4 of gate drive chips 5 to 8 are respectively connected to the control ends of B-phase IGBT5 to IGBT8, and the output ends PWM-C1 to PWMC4 of gate drive chips 9 to 12 are respectively connected to the control ends of C-phase IGBT9 to IGBT12.

[0034] The power unit includes a diode midpoint clamped APF composed of multiple IGBTs and multiple diodes. The DC side of the APF is connected in series through capacitors C1 and C2. The DC side of the APF is also connected in series through switches K1 and K2. The capacitors C1 and C2 connected in series are branch a, and the capacitors C1 and C2 connected in series are branch b. Branch a is connected in parallel with branch b. The IGBT of the APF is an I-shaped structure topology, and the midpoint is connected to the middle tap of capacitors C1 and C2. The A-phase AC side of the APF is connected to the middle tap of switches K1 and K2 through a series-connected inductor L1 and switch K3. The B-phase AC side of the APF is connected to the middle tap of switches K1 and K2 through a series-connected inductor L2 and switch K4. The C-phase AC side of the APF is connected to the middle tap of switches K1 and K2 through a series-connected inductor L3 and switch K5. DC power supply 2 is used to power the DC side of the APF.

[0035] The working process is:

[0036] When testing the driving pulses of IGBT1, IGBT2, IGBT5, IGBT6, IGBT9, and IGBT10, switch K1 is turned on and switch K2 is turned off. Similarly, when testing the driving pulses of IGBT3, IGBT4, IGBT7, IGBT8, IGBT11, and IGBT12, switch K2 is turned on and switch K1 is turned off. When testing the performance of IGBT1-IGBT4, switch K3 is turned on and switch K4 and switch K5 are turned off. When testing the performance of IGBT5-IGBT8, switch K4 is turned on and switch K3 and switch K5 are turned off. When testing the performance of IGBT9-IGBT12, switch K5 is turned on and switch K3 and switch K4 are turned off. One end of the adjustable reactor L1, L2, and L3 is connected between switches K1 and K2, and the other end is connected to the middle part of the I-shaped three-level IGBT topology through the corresponding AC side copper busbar. During the test, only the three-level topology pulse test corresponding to the two IGBTs in the corresponding tube is turned on, and the pulses of the other 10 IGBTs are all turned off.

[0037] [Example 3]

[0038] In this embodiment, an IGBT test device is the same as that in Embodiment 1, and a unit to be tested is added thereto: an IGBT module, see Figure 3 The interior of the IGBT module is a half-bridge structure of IGBT1 and IGBT2. The connection between IGBT1 and IGBT2 is connected to the middle tap of switches K1 and K2 through a reactor L. The IGBT module adopts the announcement number CN103199678B, and the patent name is "A compact IGBT module drive unit". Other models can also be used. The IGBT module includes a driver core board, a driver adapter board, and IGBT. The driver core board is connected to the input end of the driver adapter board, and the output end of the driver adapter board is connected to the IGBT. DC power supply 2 is used to power the IGBT. An optical fiber interface is provided on the driver core board, and the control board is connected to FPGA 1 through the optical fiber interface.

[0039] Working process:

[0040] When testing the driving pulse of IGBT1, switch K1 is turned on and switch K2 is turned off. Similarly, when testing the driving pulse of IGBT2, switch K2 is turned on and switch K1 is turned off. During the test, only the IGBT corresponding to the pulse test of the half-bridge structure of the IGBT module is turned on, and the pulse of the other IGBT is turned off.

[0041] The utility model does not need to disassemble the power unit, but only needs to be connected to the three-level power unit or the IGBT module provided by the manufacturer through the POF optical fiber interface or ST optical fiber interface in the control board. The control board is connected to the touch screen through the RS485 chip, and the test personnel can view the test data at any time through the touch screen, which is intuitive and convenient; the DC side of the APF is connected in series through switches K1 and K2, and the AC side of the APF is connected to the middle tap of switches K1 and K2 through the corresponding reactors connected in series and the corresponding switches, and the DC side is disconnected from the unit to be tested by the switch, which improves the safety of the unit to be tested and ensures the personal safety of the test personnel; the FPGA in the control board is provided with The POF fiber optic interface and the ST fiber optic interface, on the basis of isolating the control board and the unit, are connected to any IGBT in the three-level power unit for testing after photoelectric conversion. The operation is simple and easy to implement. The FPGA is connected to the input end of the ST driver chip, and the output end of the ST driver chip is connected to the ST transmitting fiber optic holder. The FPGA is connected to the input end of the POF driver chip, and the output end of the POF driver chip is respectively connected to the POF receiving fiber optic holder and the POF transmitting fiber optic holder. The ST fiber optic and POF fiber optic test interfaces are provided for the power modules of other manufacturers that have completed IGBT packaging, and the IGBT finished modules are tested. The structure is simple and easy to promote.

Claims

1. An IGBT testing device, the testing device is connected to a unit to be tested, characterized in that: The test device includes a control board, a DC power supply 1, a DC power supply 2, and a touch screen. The DC power supply 1 is used to power the control board and the touch screen, and the DC power supply 2 is used to power the unit to be tested. The control board includes an FPGA 1, a driver chip 1, a driver chip 2, an optical fiber interface, and an RS485 chip. The FPGA 1 is connected to the RS485 chip through corresponding pins, and the RS485 chip is used to connect to the touch screen through a port; FPGA 1 is connected to the unit under test through an optical fiber interface, and the optical fiber interface includes a receiving optical fiber seat 1, a transmitting optical fiber seat 1, a receiving optical fiber seat 2, and a transmitting optical fiber seat 2. FPGA 1 is connected to the receiving optical fiber seat 1 through corresponding pins, FPGA 1 is connected to the input end of the driver chip 1 through corresponding pins, the output end of the driver chip 1 is connected to the transmitting optical fiber seat 1, FPGA 1 is connected to the input end of the driver chip 2 through corresponding pins, and the output end of the driver chip 2 is respectively connected to the receiving optical fiber seat 2 and the transmitting optical fiber seat 2 through corresponding pins.

2. An IGBT testing device according to claim 1, characterized in that: The unit to be tested comprises a three-level power unit, the three-level power unit comprises a power unit board and a power unit, and the power unit board is connected to the power unit.

3. An IGBT testing device according to claim 2, characterized in that: The power unit board includes a DSP, a second FPGA, an ADC chip, and several gate drive chips. The DSP is connected to the second FPGA through corresponding pins. The control board is connected to the second FPGA through an optical fiber interface. The output end of the ADC chip is connected to the second FPGA through corresponding pins. The input end of the ADC chip is used to collect the voltage / current signal output by the PWM modulation of the IGBT. The input end of the gate drive chip is connected to the second FPGA through corresponding pins, and the output end of the gate drive chip is respectively connected to the PWM control end of the corresponding IGBT.

4. An IGBT testing device according to claim 2, characterized in that: The power unit includes a diode midpoint clamped APF composed of multiple IGBTs and multiple diodes. The DC side of the APF is connected in series through capacitors C1 and C2. The DC side of the APF is also connected in series through switches K1 and K2. The APF is connected to the middle tap of capacitors C1 and C2 through the midpoint of the series connection. The AC side of the APF is connected to the middle tap of switches K1 and K2 through corresponding inductors and corresponding switches connected in series. The DC power supply 2 is used to power the DC side of the APF.

5. An IGBT testing device according to claim 1, characterized in that: The unit under test also includes an IGBT module, which includes a driver core board, a driver adapter board, and an IGBT. The driver core board is connected to the input end of the driver adapter board, and the output end of the driver adapter board is connected to the IGBT. The DC power supply 2 is used to power the IGBT. An optical fiber interface is provided on the driver core board, and the control board is connected to FPGA 1 through the optical fiber interface.

6. An IGBT testing device according to claim 1, characterized in that: The FPGA chip model 1 is 10CL016YE144I7, the driver chip model 1 is 74LCX00, and the driver chip model 2 is SN74LVC2T245.

7. An IGBT testing device according to claim 3, characterized in that: The FPGA chip model is AG10KL144H, the DSP chip model is ADSP21488, and the gate drive chip model is IR2184SPBF.

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