Communication interface chip and display device

Abstract

The utility model provides a communication interface chip and a display device, and relates to the technical field of communication, the communication interface chip is applied to an LED module, a first interface module is integrated with a decoding module and a row control module to form an independent communication interface chip, and the communication interface chip can be used for displaying the LED module. The communication interface chip has the functions of signal analysis, decoding, display control and the like. Through integration of the multifunctional modules, the whole LED module is smaller in size, higher in integration level, higher in reliability and simple in design, the design cost is saved, and the problems that the number of chips on a single LED module is too large, the design of the module becomes more and more complex, and meanwhile the reliability is reduced along with increase of the number of the chips are solved.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and in particular to a communication interface chip and a display device. Background Art

[0002] LED (Light Emitting Diode) display is a flat panel display composed of small LED modules. As a new display technology, LED display technology is gradually accepted by the market for its advantages of energy saving, environmental protection, and high brightness, and is widely used in urban media, urban transportation and other fields.

[0003] With the evolution of the LED industry and the improvement of LED display resolution, the number of chips on a single LED module continues to increase, including interface chips, driver chips, row control chips, decoding chips, etc. This causes the design of the module to become more and more complex, and the reliability also decreases with the increase in the number of chips.

[0004] Therefore, improving the integration of chips on LED modules is a technical problem that needs to be solved urgently in the future LED display industry. Summary of the invention

[0005] The present application provides a communication interface chip and a display device, which solve the problem in the prior art that a single LED module becomes increasingly complex and reliability decreases as the number of chips increases.

[0006] In order to achieve the above objectives, this application adopts the following technical solutions:

[0007] In a first aspect, the present application provides a communication interface chip, which includes a first interface module, a decoding module and a row control module; the first output end of the first interface module is connected to the input end of the decoding module, and the output end of the decoding module is connected to the input end of the row control module.

[0008] The first interface module is used to receive a first signal and generate a line feed encoding signal based on the first signal.

[0009] The decoding module is used for receiving the line feed coding signal output by the first interface module, and decoding the line feed coding signal to obtain a line feed level signal.

[0010] The line control module is used for receiving the line-break level signal output by the decoding module.

[0011] The communication interface chip provided in the present application is applied to the LED module. By integrating the first interface module with the decoding module and the row control module, a communication interface chip with functions such as signal analysis, decoding and display control is formed, so that the entire LED module is smaller in size, more integrated and more reliable, which solves the problem that there are too many chips on a single LED module, resulting in the design of the module becoming more and more complicated, and the reliability also decreases with the increase in the number of chips.

[0012] In some possible implementations, the first signal may be a low voltage differential signal (LVDS), referred to as an LVDS signal. For example, in actual implementation, the first interface module may receive an LVDS signal and generate a line feed encoding signal transmitted in the form of a transistor-transistor logic level TTL signal based on the LVDS signal. For ease of explanation, the first signal is taken as an example of an LVDS signal in the embodiment. Among them, the first signal includes two parts: a data signal and a control signal. Accordingly, the LVDS signal includes an LVDS data signal and a control signal.

[0013] In some other possible implementations, the first signal may be a SerDes signal. For example, in actual implementation, the first interface module may receive the SerDes signal and generate a line feed encoding signal transmitted in the form of a TTL signal based on the SerDes signal. SerDes is the abbreviation of SERializer (serializer) / DESerializer (deserializer), which is a mainstream time-division multiplexing, point-to-point serial communication technology.

[0014] It should be noted that the first signal may also be in any other possible signal form, and this application does not limit this.

[0015] In some possible implementations, the output end of the row control module is connected to the display unit array. The row control module is also used to control the display unit array to change rows based on the row change level signal. Through this solution, the communication interface chip is connected to the display unit array, and the display unit array can be controlled to change rows based on the row change level signal. The communication interface chip provided in this application not only has a signal parsing function, but also has a display control function, with more functions and stronger compatibility.

[0016] In some possible implementations, the second output terminal of the first interface module is connected to the display driver chip, and the display driver chip is connected to the display unit array. The first interface module is also used to convert the LVDS data signal into a display drive signal transmitted in the form of a TTL signal. The display driver chip is used to receive the display drive signal output by the first interface module, and drive the display unit array to light up or extinguish based on the display drive signal. Through this solution, the communication interface chip is connected to the display driver chip to provide the display driver chip with a display drive signal, and the reliability is strong.

[0017] In some possible implementations, the row control module includes 2 n MOS tubes (Metal-Oxide-Semiconductor Field-Effect Transistor, field effect tube). The line break coding signal is an n-bit coding signal, and the line break level signal is 2 n High / low level signal. 2 n The high / low level signals are transmitted to 2 n The communication interface chip provided by the present application has not only a signal analysis function, but also a decoding function, with more functions and stronger compatibility.

[0018] In the embodiment of the present application, the decoding module is n-line-2 n The decoder outputs each input line feed coded signal as a high / low level signal. n Among the output terminals, one output terminal is at a valid level and the other output terminals are at an invalid level.

[0019] In some possible implementations, an input end of the first interface module is connected to a front-end controller. The front-end controller is used to transmit LVDS data signals and control signals to the first interface module. The first interface module obtains error information of the communication interface chip according to the LVDS data signals and control signals. The first interface module is also used to return LVDS return data to the front-end controller, and the LVDS return data includes error information, detection information and status information of the communication interface chip.

[0020] Exemplarily, the detection information may include parameters such as voltage and / or temperature.

[0021] Exemplarily, the status information may include a response packet for reading and writing a register, and / or some access-related timeout retransmission data packets, etc.

[0022] The front-end controller is, for example, a receiving card or a scanning card in an LED display screen control system, and the front-end controller can also be called a display control card. The receiving card or the scanning card can also be provided with a hub adapter board. This embodiment does not limit the front-end controller to only a receiving card or a scanning card in an LED display screen control system, and it can also be a sending card in an LED display screen control system, or other video devices that can process video sources and output LVDS data signals.

[0023] For example, the front-end controller includes a programmable logic device and a memory electrically connected to the programmable logic device, as well as a network port and other devices. The programmable logic device is, for example, an FPGA (Field-Programmable Gate Array) or other similar logic devices. Alternatively, the programmable logic device can also be an MCU (Microcontroller Unit), also known as a single-chip microcomputer (Single Chip Microcomputer) or a single-chip microcomputer; or other microprocessors with certain data processing and computing capabilities, such as an ARM (Advanced RISC Machine) processor and a digital signal processing (Digital Signal Processing, DSP) processor. The memory is, for example, a double data rate (Double Data Rate, DDR) memory.

[0024] Through the solution of the present application, the front-end controller can be directly connected to receive the LVDS data signal, thereby greatly reducing the IO pin consumption of the front-end controller. The LVDS data signal has high and stable quality, can be transmitted over long distances, and has good electromagnetic compatibility (EMC) effect.

[0025] In some possible implementations, the communication interface chip is a cascade combination of communication interface chips, and the cascade combination of communication interface chips includes M communication interface chips, and the M communication interface chips are connected in series. Wherein, M can be an integer greater than 1.

[0026] Among them, the communication interface chip cascade combination can receive the LVDS data signal and control signal transmitted by the front-end controller, and the LVDS data signal and control signal are transmitted sequentially through each communication interface chip in the communication interface chip cascade combination, that is, each communication interface chip can receive the LVDS data signal and control signal, and based on the LVDS data signal and control signal, the error information of each communication interface chip can be obtained, and the error information of each communication interface chip will be transmitted and accumulated step by step. In addition, the detection information and status information of each communication interface chip will also be transmitted and accumulated step by step. In other words, the communication interface chip cascade combination can eventually obtain the error information, detection information and status information of all communication interface chips, and can return this information to the front-end controller.

[0027] In one possible implementation, the communication interface chip cascade combination includes a first communication interface chip and a second communication interface chip connected in series.

[0028] The first communication interface chip receives the LVDS data signal and the control signal transmitted by the front-end controller, and obtains the bit error information of the first communication interface chip according to the LVDS data signal and the control signal; then the first communication interface chip transmits the LVDS data signal and the control signal, as well as the bit error information, detection information and status information of the first communication interface chip to the second communication interface chip;

[0029] The second communication interface chip obtains the bit error information of the second communication interface chip according to the LVDS data signal and the control signal; the second communication interface chip returns the LVDS cascade return data to the front-end controller, and the LVDS cascade return data includes the bit error information, detection information and status information of the first communication interface chip, and the bit error information, detection information and status information of the second communication interface chip.

[0030] In another possible implementation, the communication interface chip cascade combination includes a first communication interface chip, a second communication interface chip, and a third communication interface chip, wherein the first communication interface chip is connected to the second communication interface chip, and the second communication interface chip is connected to the third communication interface chip.

[0031] The first communication interface chip is used to receive the LVDS data signal and the control signal transmitted by the front-end controller, and obtain the error information of the first communication interface chip according to the LVDS data signal and the control signal; the first communication interface chip is also used to transmit the LVDS data signal and the control signal, as well as the error information, detection information and status information of the first communication interface chip to the second communication interface chip;

[0032] a second communication interface chip, used to obtain the bit error information of the second communication interface chip according to the LVDS data signal and the control signal; the second communication interface chip is also used to transmit the LVDS data signal and the control signal, as well as the bit error information, detection information and status information of the first communication interface chip, and the bit error information, detection information and status information of the second communication interface chip to the third communication interface chip;

[0033] The third communication interface chip is used to obtain the bit error information of the third communication interface chip according to the LVDS data signal and the control signal; the third communication interface chip is also used to return LVDS cascade return data to the front-end controller, and the LVDS cascade return data includes the bit error information, detection information and status information of the first communication interface chip, the bit error information, detection information and status information of the second communication interface chip, and the bit error information, detection information and status information of the third communication interface chip.

[0034] The present application solution can realize the cascading and backhaul functions of the communication interface chips, and increase the application scenarios of the communication interface chips. Among them, the front-end controller (such as FPGA) can perform status detection on multiple cascaded communication interface chips.

[0035] In a second aspect, the present application provides a display device, comprising a display driver chip, a display unit array, and the communication interface chip provided in the first aspect, wherein an input end of the communication interface chip is connected to a front-end controller, an output end of the communication interface chip is connected to the display unit array, another output end of the communication interface chip is connected to an input end of the display driver chip, and an output end of the display driver chip is connected to the display unit array.

[0036] In some possible implementations, the display device includes multiple cascaded communication interface chips, display driver chips, and display unit arrays, and each communication interface chip is connected to a display driver chip, and each display driver chip is electrically connected to a display unit array. A front-end controller (such as an FPGA) can perform status detection on multiple cascaded communication interface chips. The present application solution can realize the cascading and feedback functions of the communication interface chip, expanding the application scenarios of the communication interface chip.

[0037] The display device (or LED module) provided in the present application includes a display driver chip, a display unit array and a communication interface chip. By integrating the first interface module with the decoding module and the row control module, a communication interface chip with functions such as signal analysis, decoding and display control is formed, so that the entire LED module is smaller in size, more integrated and more reliable, which solves the problem that there are too many chips on a single LED module, resulting in the design of the module becoming more and more complicated, and the reliability also decreases with the increase in the number of chips.

[0038] In a third aspect, the present application provides a communication interface chip, which includes a first interface module and a decoding module; the first output end of the first interface module is connected to the input end of the decoding module. The first interface module is used to receive a first signal and generate a line feed coding signal based on the first signal. The decoding module is used to receive the line feed coding signal output by the first interface module, and decode the line feed coding signal to obtain a line feed level signal.

[0039] The first signal may be an LVDS signal, or a SerDes signal, or any other possible signal. Furthermore, the first signal includes a data signal and a control signal. Accordingly, the LVDS signal includes an LVDS data signal and a control signal.

[0040] The communication interface chip provided in the present application is applied to the LED module. By integrating the first interface module with the decoding module to form a communication interface chip with functions such as signal analysis and decoding, the entire LED module is smaller in size, more integrated, and more reliable. This solves the problem that there are too many chips on a single LED module, which causes the design of the module to become increasingly complex, and the reliability also decreases as the number of chips increases.

[0041] In some possible implementations, the output of the decoding module is connected to the input of the row control chip, and the output of the row control chip is connected to the display unit array. The row control chip is used to receive the row-break level signal output by the decoding module and control the display unit array to change rows based on the row-break level signal.

[0042] In some possible implementations, the second output terminal of the first interface module is connected to a display driver chip, and the display driver chip is connected to the display unit array. The first interface module is also used to convert the LVDS data signal into a display drive signal transmitted in the form of a TTL signal. The display driver chip is used to receive the display drive signal output by the first interface module, and drive the display unit array to light up or turn off based on the display drive signal.

[0043] In some possible implementations, an input end of the first interface module is connected to a front-end controller. The front-end controller is used to output LVDS data signals and control signals to the first interface module. The first interface module is used to obtain error information of the communication interface chip according to the LVDS data signals and control signals. The first interface module is also used to return error information, detection information, and status information of the communication interface chip to the front-end controller.

[0044] In some possible implementations, the communication interface chip is a cascade combination of communication interface chips, and the cascade combination of communication interface chips includes M communication interface chips, and the M communication interface chips are connected in series. Wherein, M can be an integer greater than 1.

[0045] Among them, the communication interface chip cascade combination can receive the LVDS data signal and control signal transmitted by the front-end controller, and the LVDS data signal and control signal are transmitted sequentially through each communication interface chip in the communication interface chip cascade combination, that is, each communication interface chip can receive the LVDS data signal and control signal, and based on the LVDS data signal and control signal, the error information of each communication interface chip can be obtained, and the error information of each communication interface chip will be transmitted and accumulated step by step. In addition, the detection information and status information of each communication interface chip will also be transmitted and accumulated step by step. In other words, the communication interface chip cascade combination can eventually obtain the error information, detection information and status information of all communication interface chips, and can return this information to the front-end controller.

[0046] In one possible implementation, the communication interface chip cascade combination includes a first communication interface chip and a second communication interface chip connected in series.

[0047] The first communication interface chip receives the LVDS data signal and the control signal transmitted by the front-end controller, and obtains the bit error information of the first communication interface chip according to the LVDS data signal and the control signal; then the first communication interface chip transmits the LVDS data signal and the control signal, as well as the bit error information, detection information and status information of the first communication interface chip to the second communication interface chip;

[0048] The second communication interface chip obtains the bit error information of the second communication interface chip according to the LVDS data signal and the control signal; the second communication interface chip returns the LVDS cascade return data to the front-end controller, and the LVDS cascade return data includes the bit error information, detection information and status information of the first communication interface chip, and the bit error information, detection information and status information of the second communication interface chip.

[0049] In another possible implementation, the communication interface chip cascade combination includes a first communication interface chip, a second communication interface chip, and a third communication interface chip, wherein the first communication interface chip is connected to the second communication interface chip, and the second communication interface chip is connected to the third communication interface chip.

[0050] The first communication interface chip is used to receive the LVDS data signal and the control signal transmitted by the front-end controller, and obtain the error information of the first communication interface chip according to the LVDS data signal and the control signal; the first communication interface chip is also used to transmit the LVDS data signal and the control signal, as well as the error information, detection information and status information of the first communication interface chip to the second communication interface chip;

[0051] a second communication interface chip, used to obtain the bit error information of the second communication interface chip according to the LVDS data signal and the control signal; the second communication interface chip is also used to transmit the LVDS data signal and the control signal, as well as the bit error information, detection information and status information of the first communication interface chip, and the bit error information, detection information and status information of the second communication interface chip to the third communication interface chip;

[0052] The third communication interface chip is used to obtain the bit error information of the third communication interface chip according to the LVDS data signal and the control signal; the third communication interface chip is also used to return LVDS cascade return data to the front-end controller, and the LVDS cascade return data includes the bit error information, detection information and status information of the first communication interface chip, the bit error information, detection information and status information of the second communication interface chip, and the bit error information, detection information and status information of the third communication interface chip.

[0053] It can be understood that the beneficial effects of the third aspect mentioned above can be found in the relevant description of the first aspect mentioned above, and will not be repeated here.

[0054] In a fourth aspect, the present application provides a display device, comprising a display driver chip, a display unit array, a row control chip, and the communication interface chip provided in the third aspect. The input end of the communication interface chip is connected to the front-end controller, one output end of the communication interface chip is connected to the input end of the row control chip, the other output end of the communication interface chip is connected to the input end of the display driver chip, and the output end of the row control chip and the output end of the display driver chip are respectively connected to the display unit array.

[0055] The display device (LED module) provided in the present application includes a display driver chip, a display unit array, a row control chip and a communication interface chip. By integrating the first interface module with the decoding module to form a communication interface chip with functions such as signal analysis and decoding, the entire LED module is smaller in size, more integrated, and more reliable. This solves the problem that there are too many chips on a single LED module, which makes the design of the module increasingly complex, and the reliability decreases as the number of chips increases. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] Figure 1 A schematic diagram of the structure of the communication interface chip disclosed in the embodiment of the present application;

[0057] Figure 2 A schematic diagram of the structure of a first interface module disclosed in an embodiment of the present application;

[0058] Figure 3 A schematic diagram of the structure of a communication interface chip disclosed in an embodiment of the present application;

[0059] Figure 4 A schematic diagram of the structure of the LVDS interface circuit disclosed in the embodiment of the present application;

[0060] Figure 5 A schematic diagram of the structure of a data analysis circuit disclosed in an embodiment of the present application;

[0061] Figure 6 A schematic diagram of the structure of a data identification unit disclosed in an embodiment of the present application;

[0062] Figure 7 A schematic diagram of the structure of a data distribution unit disclosed in an embodiment of the present application;

[0063] Figure 8 A schematic diagram of the structure of a driving timing recovery circuit disclosed in an embodiment of the present application;

[0064] Fig. 9 A schematic diagram of the structure of a TTL output signal control circuit disclosed in an embodiment of the present application;

[0065] Fig.10 This is a schematic diagram of the structure of another first interface module disclosed in an embodiment of the present application;

[0066] Fig.11 A schematic diagram of the structure of another first interface module disclosed in an embodiment of the present application;

[0067] Fig.12 A schematic diagram of the structure of a cascade chip disclosed in an embodiment of the present application;

[0068] Fig.13 A schematic diagram of the structure of an NMOS tube disclosed in an embodiment of the present application;

[0069] Fig.14 A schematic diagram of the structure of a PMOS tube disclosed in an embodiment of the present application;

[0070] Fig.15 A schematic diagram of the structure of another communication interface chip disclosed in an embodiment of the present application;

[0071] Fig.16A schematic diagram of the structure of a display device N disclosed in an embodiment of the present application;

[0072] Fig.17 It is a schematic diagram of the structure of a display device M disclosed in an embodiment of the present application. DETAILED DESCRIPTION

[0073] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0074] The term "and / or" in this article is a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The symbol " / " in this article indicates that the associated objects are in an or relationship, for example, A / B means A or B.

[0075] The terms "first" and "second" in the specification and claims herein are used to distinguish different objects rather than to describe a specific order of objects. In the description of the embodiments of the present application, unless otherwise specified, the meaning of "multiple" refers to two or more than two, for example, multiple processing units refer to two or more processing units, etc.; multiple elements refer to two or more elements, etc.

[0076] In the embodiments of the present application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0077] To facilitate understanding of the embodiments of the present application, some terms used in the embodiments of the present application are explained below to facilitate understanding by those skilled in the art.

[0078] LVDS (Low-Voltage Differential Signaling) is a differential signal technology with low power consumption, low bit error rate, low crosstalk and low radiation. This transmission technology can reach more than 155Mbps. The core of LVDS technology is the use of extremely low voltage swing high-speed differential transmission data, which can achieve point-to-point or point-to-multipoint connection. Its transmission medium can be copper PCB connection or balanced cable.

[0079] TTL (Transistor-Transistor Logic): TTL level signal stipulates that +5V is equivalent to logic "1" and 0V is equivalent to logic "0" (when binary is used to represent data). This data communication and level specification method is called TTL (Transistor-Transistor Logic Level) signal system, which is the standard technology for communication between various parts of the device controlled by the computer processor. Most general electronic devices use TTL level, but its driving ability and anti-interference ability are very poor, and it is not suitable as an external communication standard. Some communication methods such as RS232, RS485, USB, etc. do not use TTL level on the transmission line, so the signals on these communication lines must be converted at the electronic device end to communicate normally.

[0080] At present, when designing LED light boards, all chips that perform different functions are placed on the light boards, resulting in too many chips on the LED modules, complex designs, and reduced reliability as the number of chips increases.

[0081] Based on this, the embodiment of the present application provides a digital decoding communication interface chip and display device based on low voltage differential signal LVDS protocol analysis. By integrating a first interface module, a decoding module and a row control module, it can receive the LVDS data signal output by the front-end controller to generate a driving signal transmitted in the form of a TTL signal, which solves the problem of too many chips on a single LED module and the reliability decreasing with the increase in the number of chips. It saves design costs and makes the entire LED module smaller, more integrated and more reliable.

[0082] In order to better understand the embodiments of the present application, the embodiments of the present application are briefly described below:

[0083] See also Figure 1 The embodiment of the present application discloses a digital decoding communication interface chip based on low voltage differential signal LVDS protocol analysis, such as Figure 1As shown, the communication interface chip 100 includes, for example: a first interface module 10, a decoding module 20 and a row control module 30, wherein the first output end of the first interface module is connected to the input end of the decoding module, and the output end of the decoding module is connected to the input end of the row control module;

[0084] The first interface module 10 is, for example, an ASIC (Application Specific Integrated Circuits) chip, which is used to receive the LVDS data signal ( Figure 1 The LVDS data signal is converted into a line-feed coding signal and a display driving signal.

[0085] It should be noted that, in addition to receiving the LVDS data signal, the first interface module 10 also receives a control signal associated with the LVDS data signal, and the control signal includes control information for the LVDS data signal.

[0086] On the one hand, the first interface module 10 outputs a line feed coding signal. The first interface module 10 outputs the line feed coding signal to the decoding module 20. The decoding module 20 is n-line-2 n The decoder 20 is also called a line decoding chip. The decoder outputs each input line-break coded signal as a line-break level signal. n There are two output terminals, and only one output terminal is at a valid level. n -1 output terminal is an invalid level. Optionally, the valid output logic level can be set to 1 (i.e. high level, called high level active) or 0 (i.e. low level, called low level active). The row control module is 2 n MOS tubes, such as enhanced NMOS (Negative channel-Metal-Oxide-Semiconductor) tubes and enhanced PMOS (Positive channel-Metal-Oxide-Semiconductor) tubes. Among them, the line break coding signal is n-way binary value, and the line break level signal is 2 n Road high / low level, row control signal is 2 n Road, Control 2 n The row display cell array wraps.

[0087] On the other hand, the first interface module 10 outputs a display drive signal, which is used to light up the display unit array. The display drive signal may include a grayscale clock signal (denoted as GCLK), a data clock signal (denoted as DCLK), a latch signal (denoted as LATCH) and a display data signal (denoted as DATA).

[0088] On the other hand, the first interface module 10 can also output LVDS return data ( Figure 1 In addition, in a scenario where multiple communication interface chips are cascaded, the first interface module 10 can output LVDS cascade return data. The LVDS cascade return data is used to represent the status information of the multiple cascaded communication interface chips.

[0089] from Figure 1 It can be seen that after receiving the LVDS data signal, the communication interface chip provided in the embodiment of the present application can process the LVDS data signal to obtain the row control signal and display drive signal transmitted in the form of TTL signal, as well as the LVDS cascade return data. Then, the communication interface chip can output the row control signal and display drive signal in the form of TTL signal, and output the LVDS return data in the form of LVDS signal.

[0090] like Figure 2 As shown, a first interface module 10 disclosed in an embodiment of the present application, for example, includes: an LVDS interface circuit 101, a data analysis circuit 102, a drive timing recovery circuit 103, and a TTL output signal control circuit 104. Among them, the data analysis circuit 102 is electrically connected to the LVDS interface circuit 101, the drive timing recovery circuit 103 is electrically connected to the data analysis circuit 102, and the TTL output signal control circuit 104 is electrically connected to the drive timing recovery circuit 103.

[0091] The LVDS interface circuit 101 is used to electrically connect to the front-end controller to receive the LVDS data signal output by the front-end controller, and to recover and convert the LVDS data signal to obtain a parallel data signal and an accompanying clock signal. The data analysis circuit 102 is used to analyze and process the parallel data signal based on the accompanying clock signal to obtain a first data signal. The drive timing recovery circuit 103 is used to perform timing recovery processing on the first data signal based on the accompanying clock signal to obtain a drive signal transmitted in the form of a TTL signal, and the TTL output signal control circuit is used to adjust the drive signal and output a display drive signal and a line feed coding signal.

[0092] Among them, the driving signal can be understood as an LED driving signal. For example, the driving signal is, for example, a quasi-SPI signal, including: a data clock signal DCLK, a latch signal LAT, a grayscale clock signal GCLK, a line feed coding signal ABCDE, and an RGB data signal, etc. Alternatively, the driving signal is, for example, an SPI signal, for example, including: an SPI data input signal SPI_mosi, an SPI data output signal SPI_miso, an SPI clock signal SPI_clk, and an SPI chip select signal SPI_cs, etc. Alternatively, the driving signal includes the aforementioned quasi-SPI signal and SPI signal, that is, including: a data clock signal DCLK, a latch signal LAT, a grayscale clock signal GCLK, a line feed coding signal ABCDE, an RGB data signal, an SPI data input signal SPI_mosi, an SPI data output signal SPI_miso, an SPI clock signal SPI_clk, and an SPI chip select signal SPI_cs.

[0093] Among them, the LVDS data signal is, for example, at least one pair of LVDS data signals. The LVDS data signal, the parallel data signal and the first data signal, for example, all include: the generation information of the LED drive signal, such as the generation information of the aforementioned SPI-like signal, or the generation information of the aforementioned SPI signal, or the generation information of the aforementioned SPI-like signal and the generation information of the SPI signal. For example, the generation information of the SPI-like signal includes: clock signal generation information for generating a data clock signal DCLK and a grayscale clock signal GCLK, control signal generation information for generating a latch signal LAT and a line feed encoding signal ABCDE, and RGB data signal information for recovering an RGB data signal. The generation information of the SPI signal is, for example: SPI signal generation information for generating an SPI data input signal SPI_mosi, an SPI data output signal SPI_miso, an SPI clock signal SPI_clk, and an SPI chip select signal SPI_cs, etc.

[0094] In the present application, the first interface module can receive a first signal and generate a line feed encoding signal based on the first signal. The first signal can be in any possible signal form, which is not limited in the present application.

[0095] In a possible implementation, the first signal is an LVDS signal, the first interface module can receive the LVDS signal, and convert the LVDS signal into a line feed coded signal transmitted in the form of a TTL signal based on the LVDS protocol.

[0096] In another possible implementation, the first signal is a SerDes signal, and the first interface module can receive the SerDes signal and convert the SerDes signal into a line feed encoding signal transmitted in the form of a TTL signal.

[0097] For the convenience of explanation, the following embodiments are exemplified by taking the first signal being an LVDS signal as an example.

[0098] Embodiment 1: Communication interface chip 100A integrating LVDS interface module, decoding module and row control module

[0099] like Figure 3 In the first embodiment, the communication interface chip 100A is an interface chip integrating three modules: a first interface module 10 , a decoding module 20 and a row control module 30 . The first output end of the first interface module is connected to the input end of the decoding module, and the output end of the decoding module is connected to the input end of the row control module; the first interface module receives the LVDS data signal output by the front-end controller, and the first interface module converts the LVDS data signal into a line break coding signal and a display drive signal transmitted in the form of a TTL signal; the first interface module transmits the line break coding signal to the decoding module, the decoding module receives the line break coding signal, and converts the line break coding signal into a line break level signal, the decoding module outputs the line break level signal to the row control module, and the row control module receives the line break level signal, wherein the line break level signal is used to control the display unit array to break, and here the decoding module is a 5-32 row decoding chip as an example for exemplary description, ABCDE is a 5-way line break coding signal, Y0~Y31 is a 32-way line break level signal, and R-0~R-31 is a 32-way row control signal; the display drive signal is used to light up the display unit array, and the display drive signal includes: a grayscale clock signal, a data clock signal, a latch signal and a display data signal.

[0100] The first interface module 10 includes: an LVDS interface circuit 101 , a data analysis circuit 102 , a drive timing recovery circuit 103 , and a TTL output signal control circuit 104 .

[0101] Specifically, the input end of the LVDS interface circuit 101 is connected to the front-end controller, the LVDS interface circuit 101 receives the LVDS data signal output by the front-end controller, and recovers and converts the LVDS data signal to output a parallel data signal and an accompanying clock signal; the output end of the LVDS interface circuit 101 is connected to the input end of the data analysis circuit 102, the data analysis circuit 102 is used to analyze and process the parallel data signal based on the accompanying clock signal, and output a first data signal; the output end of the data analysis circuit 102 is connected to the input end of the drive timing recovery circuit 103, the drive timing recovery circuit 103 is used to perform timing recovery processing on the first data signal based on the accompanying clock signal, and output a drive signal transmitted in the form of a TTL signal, and the output end of the drive timing recovery circuit 103 is connected to the input end of the TTL output signal control circuit 104, the TTL output signal control circuit 104 is used to adjust the drive signal, and output a display drive signal and a line feed coding signal.

[0102] Among them, Figure 4 As shown, the LVDS interface circuit 101 includes: a clock data recovery unit 1011, a serial-to-parallel conversion unit 1012;

[0103] Specifically, the input end of the clock data recovery unit 1011 is connected to the front-end controller, and the clock data recovery unit 1011 is used to receive the LVDS data signal output by the front-end controller, and perform data clock recovery processing to obtain a serial data signal and a serial clock signal; the output end of the clock data recovery unit is connected to the input end of the serial-to-parallel conversion unit, and the output end of the serial-to-parallel conversion unit is connected to the data analysis circuit 102; the serial-to-parallel conversion unit 1012 is used to perform serial-to-parallel conversion on the serial data signal and the serial clock signal, obtain a parallel data signal and an accompanying clock signal, and output them to the data analysis circuit 102.

[0104] Among them, the clock data recovery unit 1011 is a CDR (Clock Data Recovery) unit, and the CDR unit can be understood as a circuit using CDR technology. For example, the clock data recovery unit 1011 includes: a gain unit for receiving an LVDS data signal, a phase detector and a frequency detector connected to the gain unit, a filter connected to the phase detector and the frequency detector, and a voltage-controlled oscillator (VOC) connected to the filter. In addition, the voltage-controlled oscillator is also connected to the gain unit, and the voltage-controlled oscillator can output a serial clock signal, and the gain unit can output a serial data signal. Among them, the serial clock signal and the serial data signal are transmitted in the form of LVDS signals, for example. Among them, the gain unit is an existing circuit structure that can realize the signal enhancement function. It should be noted that this embodiment does not limit the specific structure of the clock data recovery unit 1011, and the existing CDR circuit can realize data recovery processing of the LVDS data signal to obtain a serial data signal and a serial clock signal, which are all applicable to this embodiment.

[0105] The serial-to-parallel conversion unit 1012 includes, for example, a shift register to convert a serial data signal into a parallel data signal and to convert a serial clock signal into a parallel clock signal output. It should be noted that the present embodiment does not limit the specific structure of the serial-to-parallel conversion unit 1012, and any existing circuit that can realize the serial-to-parallel conversion function is applicable to the present embodiment. For example, the serial-to-parallel conversion unit 1012 may also include a plurality of delay units connected in series and a D-type flip-flop (data flip-flop / delay flip-flop) connected in series with each delay unit, wherein the delay unit is an existing circuit that can realize time delay.

[0106] like Figure 5 As shown, the data analysis circuit 102 includes: a data identification unit 1021, a decoding processing unit 1022, and a data distribution unit 1023.

[0107] Specifically, the input end of the data identification unit 1021 is connected to the output end of the LVDS interface circuit 101, and the data identification unit 1021 is used to identify the parallel data signal based on the accompanying clock signal to obtain an identified data signal; the output end of the data identification unit 1021 is connected to the input end of the decoding processing unit 1022, and the decoding processing unit 1022 is used to decode the identified data signal based on the accompanying clock signal to obtain a second data signal, and output it to the data distribution unit, wherein the second data signal includes the first data signal; the output end of the decoding processing unit 1022 is connected to the input end of the data distribution unit 1023, and the output end of the data distribution unit 1023 is connected to the driving timing recovery circuit 103, and the data distribution unit 1023 is used to parse the second data signal to obtain a target data signal and a cascade data signal, and obtain the first data signal based on the target data signal, and output it to the driving timing recovery circuit 103.

[0108] The data identification unit 1021, for example, accurately matches the start position and end position of the parallel data signal through a specific 8B / 10B coding sequence, thereby aligning the parallel data signal and outputting it so that the subsequent unit can process it.

[0109] For example, Figure 6 As shown, the data identification unit 1021 includes: a receiving subunit a, a comparing subunit b, and a delaying subunit c;

[0110] Specifically, the receiving subunit a is connected to the output end of the serial-to-parallel conversion unit 1012, and the receiving subunit a is used to receive and cache parallel data signals; the receiving subunit a is connected to the comparing subunit b, and the comparing subunit b is used to receive parallel data signals and compare the parallel data signals with the local fixed sequence to output a delay control instruction when the two are compared to be the same; the delay subunit c is connected to the comparing subunit b, the receiving subunit a and the decoding processing unit 1022 respectively, and the delay subunit c is used to receive the delay control instruction and the parallel data signal, and delay the parallel data signal based on the delay control instruction to obtain a header-aligned identification data signal and output it to the decoding processing unit 1022.

[0111] Among them, the local fixed sequence can be understood as a preset fixed number. For example, the local fixed sequence is a fixed number of 30 bits. The parallel data signal can be understood as multiple parallel data packets. Comparing the parallel data signal with the local fixed sequence can be understood as comparing the header code of each data packet with the local fixed sequence. The delay control instruction can be understood as a control pulse signal accompanying the path, which is used to guide the data alignment of the delay subunit c, so that a controlled aligned data stream can be formed. Alignment mainly aligns the position of the first 7 bits in the parallel data, and adjusts the position of the input data stream through the bit / offset when aligning the header code and the local fixed sequence to achieve the alignment effect.

[0112] For example, the receiving subunit a includes a shift register composed of a plurality of D-type flip-flops connected in series, the comparing subunit b includes a comparator, and the delay subunit c is composed of an existing RC delay circuit. It should be noted that this embodiment does not limit the specific structure of the data identification unit 1021, and any existing circuit that can realize the data packet header alignment function is applicable to this embodiment.

[0113] Among them, the decoding processing unit 1022 is, for example, an existing 8B / 10B decoder. It can be understood here that the LVDS data signal is 8B / 10B encoded by the front-end controller, that is, 8Bit data is encoded into 10Bit data transmission, and the decoding processing unit 1022 performs 8B / 10B decoding processing on the received data, that is, the aforementioned decoding processing is 8B / 10B decoding processing, and the 10Bit data is restored to 8Bit data.

[0114] By setting the data identification unit 1021 and the decoding processing unit 1022 in the data analysis circuit 102, the data identification and decoding functions can be completed, and 8B / 10B data decoding can be realized.

[0115] For example, Figure 7 As shown, the data distribution unit 1023 includes: a counting subunit d, a selecting subunit e, and a judging subunit f; the counting subunit d, the selecting subunit e, and the judging subunit f are connected in pairs; the input end of the judging subunit f is connected to the decoding processing unit 1022, the judging subunit f is used to receive the second data signal, and determine whether the second data signal is a target data signal, if it is a target data signal, the counting subunit d counts the target data signal, the selecting subunit e selects the first data signal from the target data signal, the output end of the selecting subunit e is connected to the driving timing recovery circuit 103, and the selecting subunit e outputs the first data signal to the driving timing recovery circuit 103.

[0116] Wherein, the second data signal is, for example, a plurality of data packets, and the judging subunit f confirms whether it is the target data by identifying the identification code of the data packet header one by one. When the identification code is the same as its own identification code, it is the data required by itself, i.e., the target data. When the identification code is different from its own identification code, it is the data not required by itself, i.e., the cascade data. The cascade data is directly output to the encoding processing circuit. For the data required by itself, the counting subunit d starts to count its own second data signal, i.e., the target data packet, from the beginning, and informs the selecting subunit e after counting to the end of the header data. The selecting subunit e reads the part without the header data from the judging subunit f as the first data signal and outputs it to the driving timing recovery circuit. The counting subunit d includes, for example, a counter. The judging subunit f is, for example, an existing circuit structure, for example, including: a trigger, a comparator, and a timing circuit. The selecting subunit e includes, for example, a multiplexer. It should be noted that this embodiment does not limit the specific structure of the data distribution unit 1023, and other circuit structures that can realize the data packet identification and data distribution functions are applicable to the data distribution unit 1023.

[0117] For example, Figure 8 As shown, the driving timing recovery circuit 103 includes: a clock signal generating unit g, a control signal generating unit h, and a data signal recovery unit i. The input end of the clock signal generating unit g is connected to the output end of the data analysis circuit 102, and the clock signal generating unit g is used to receive the clock signal generating information in the accompanying clock signal and the first data signal, and generate a gray clock signal and a data clock signal based on the clock signal generating information and the accompanying clock signal; the input end of the control signal generating unit h is connected to the output end of the data analysis circuit 102, and the control signal generating unit is used to receive the control signal generating information in the accompanying clock signal and the first data signal, and generate a latch signal and a line feed encoding signal based on the control signal generating information and the accompanying clock signal; the input end of the data signal recovery unit i is connected to the data analysis circuit 102, and the data signal recovery unit i is used to receive the data signal generating information in the accompanying clock signal and the first data signal, and obtain a display data signal based on the accompanying clock signal and the data signal generating information.

[0118] Wherein, the driving signal includes: a grayscale clock signal, a data clock signal, a latch signal, a line feed encoding signal and a display data signal. The data signal generation information is, for example, RGB signal information and / or SPI signal generation information, and correspondingly, the display data signal is, for example, an RGB signal and / or an SPI signal. Wherein, the RGB signal generation information is, for example, grayscale data content, and the SPI signal generation information is, for example, correction data generation information, control signal generation information or interactive signal generation information, that is, the SPI signal is, for example, correction data, control signal and interactive signal, etc. The various signal generation information mentioned above can be understood as indicating at what time a rising edge is generated and at what time a falling edge is generated, so as to generate corresponding signals.

[0119] For example, the clock signal generating unit g includes: a frequency division and multiplication subunit, a multiplexer connected to the frequency division and multiplication subunit, and a gating subunit connected to the multiplexer, wherein the input end of the frequency division and multiplication subunit is connected to the data analysis circuit 102, such as the decoding processing unit 1022, for receiving the clock signal input by the decoding processing unit 1022, and performing frequency division and multiplication processing on the accompanying clock signal to obtain multiple clock signals and output them to the multiplexer, the multiplexer selects the target clock signal from the multiple clock signals and outputs it to the clock input end of the gating subunit, the data input end of the gating subunit is connected to the data analysis circuit 102, such as the decoding processing unit 1022, to receive clock signal generation information such as data clock signal generation information DCLK EN (characterizing the opening period of the data clock signal) and / or grayscale clock signal generation information GCLK EN (characterizing the opening period of the grayscale clock signal), so that the gating subunit can generate the data clock signal DCLK and / or the grayscale clock signal GCLK. The frequency division and multiplication subunit includes, for example, a frequency divider and a frequency multiplier. The gated subunit includes, for example, an AND gate. In addition, the data clock signal DCLK may also involve phase adjustment when it is generated. At this time, the register can be configured to set the phase of the data clock signal DCLK. In some application scenarios, DCLK needs to support different frequencies and modes such as continuous output and single and double edge output. Corresponding operations need to be performed, which can be achieved by configuring registers and matching frequency division circuits and phase adjustment circuits. The grayscale clock signal GCLK can be used as an external reference clock for the display driver chip, or it can be directly used as a display circuit clock. However, in some special cases, the grayscale clock signal also needs to be processed by GCLK pulse width modulation. For example, when it involves compensation circuits and blanking circuits, the last clock of the grayscale clock signal usually needs to extend the pulse width.

[0120] For example, the control signal generating unit h includes: a multiplexer MUX, a counter and a D-type flip-flop DFF, the input end of the multiplexer MUX is connected to the data analysis circuit 102, such as a decoding processing unit, to receive the latch signal generation information DIN[0]-DIN[3], the output end of the multiplexer MUX is connected to the data input end D of the DFF, the input end of the counter is connected to the data analysis circuit 102, such as the decoding processing unit 1022, to receive the accompanying clock signal SCLK, the output end of the counter is connected to the control end of the multiplexer MUX, and the counter is connected to the control end of the multiplexer MUX. The counter counts the accompanying clock signal SCLK and outputs the counting signal to the multiplexer MUX. The multiplexer MUX selects an output from the latch signal generation information DIN[0]-DIN[3] according to the counting signal. For example, when the counting signal is 0, the DIN[0] output is selected, when the counting signal is 1, the DIN[1] output is selected, and so on. The clock input terminal CK of the DFF is connected to the decoding processing unit 1022 to receive the accompanying clock signal SCLK, so that the DFF can generate the latch signal LAT based on the accompanying clock signal and the latch signal generation information. When generating the line feed coding signal, it is only necessary to replace the latch signal generation information with the corresponding line feed coding signal generation information.

[0121] For example, the data signal recovery unit i includes: a counter, a comparator, a multiplexer MUX and a D-type flip-flop DFF, wherein the input end of the counter is connected to the data analysis circuit 102, such as the decoding processing unit 1022, to receive the accompanying clock signal SCLK, the output end of the counter is connected to the input end of the comparator, the counter counts the accompanying clock signal SCLK and outputs a counting signal to the comparator, the other input end of the comparator is connected to the decoding processing unit 1022 to receive the phase information PHASE in the RGB signal information, the output end of the comparator is connected to the control end of the multiplexer MUX, the comparator compares the phase information PHASE with the counting signal and outputs a comparison signal to the multiplexer MUX, when the two are the same, the comparison signal "1" is output, when the two are different, the comparison signal "0" is output, the input end of the multiplexer is connected to the decoding processing unit 1022 to receive the RGB signal information RGB_D ATA[2:0], the output of the multiplexer is connected to the data input D of the DFF, and when the comparison signal received by the multiplexer MUX is "1", the input RGB_DATA[2:0] is output to the DFF, and the clock input CK of the DFF is connected to the decoding processing unit 1022 to receive the accompanying clock signal SCLK, so that the DFF generates the RGB data signal TTL_RGB[2:0] according to the accompanying clock signal SCLK and RGB_DATA[2:0]. The output Q of the DFF is used to output the RGB data signal TTL_RGB[2:0]. The multiplexer MUX also receives the RGB data signal TTL_RGB[2:0] output by the DFF. When the comparison signal received by the multiplexer MUX is "0", the RGB data signal TTL_RGB[2:0] is output to the DFF, so that the DFF maintains the output of the RGB data signal TTL_RGB[2:0]. It can be understood here that when the counting signal is equal to the phase information PHASE, the RGB data signal is updated, otherwise the RGB data signal is maintained. The above description takes the data signal recovery unit i generating the display data signal as an RGB data signal as an example. When the data signal is an SPI signal, it is only necessary to replace RGB_DATA[2:0] with the corresponding SPI signal generation information and replace the phase information PHASE with the phase information of the SPI signal.

[0122] It should be noted that this embodiment does not limit the specific structures of the clock signal generating unit g, the control signal generating unit h, and the data signal recovery unit i. Other circuit structures can realize the generation of grayscale clock signals and data clock signals based on the clock signal generation information and the accompanying clock signal, both of which are suitable for the clock signal generating unit g. Other circuit structures can realize the generation of latch signals and line feed coding signals based on the control signal generation information and the accompanying clock signal, both of which are suitable for the control signal generating unit h. Other circuit structures can realize the recovery of display data signals based on the accompanying clock signal and data signal generation information, such as including RGB signal information and / or SPI signal generation information, such as including RGB data signals and / or SPI signals, both of which are suitable for the data signal recovery unit i.

[0123] For example, Fig. 9 As shown, the TTL output signal control circuit 104 includes a delay adjustment unit j and a current adjustment unit k. The input end of the delay adjustment unit j is connected to the output end of the driving timing recovery circuit 103, the delay adjustment unit is used to receive the driving signal, the delay adjustment unit j delays the driving signal according to the first control instruction, obtains the delayed signal and outputs it to the current adjustment unit k, the input end of the current adjustment unit k is connected to the output end of the delay adjustment unit j, the current adjustment unit k is used to receive the delayed signal, the current adjustment unit k adjusts the current intensity of the delayed signal according to the second control instruction, obtains the display driving signal and the line feed coding signal, the display driving signal includes a grayscale clock signal, a data clock signal, a latch signal and a display data signal; the current adjustment unit k outputs the line feed coding signal to the decoding module.

[0124] Among them, the first control instruction and the second control instruction can be understood as instructions issued through the configuration register. The delayed signal is of the same type as the drive signal, except that individual signals are delayed. For example, the aforementioned delayed drive signal includes: SPI-like signal: data clock signal DCLK, latch signal LAT, grayscale clock signal GCLK, line feed encoding signal ABCDE, RGB data signal; and / or SPI signal: SPI data input signal SPI_mosi, SPI data output signal SPI_miso, SPI clock signal SPI_clk and SPI chip select signal SPI_cs.

[0125] Among them, delay adjustment of the driving signal can be understood as delay adjustment of at least one of the data clock signal DCLK, the latch signal LAT, the grayscale clock signal GCLK, the line feed coding signal ABCDE, the RGB data signal, the SPI data input signal SPI_mosi, the SPI data output signal SPI_miso, the SPI clock signal SPI_clk and the SPI chip select signal SPI_cs.

[0126] Among them, adjusting the current intensity of the delayed signal can be understood as adjusting the current intensity of at least one of the data clock signal DCLK, the latch signal LAT, the grayscale clock signal GCLK, the line feed coding signal ABCDE, the RGB data signal, the SPI data input signal SPI_mosi, the SPI data output signal SPI_miso, the SPI clock signal SPI_clk and the SPI chip select signal SPI_cs.

[0127] It should be noted that, when the driving signal does not require delay adjustment but requires current intensity adjustment, the delay adjustment unit may not work, and directly output the driving signal as a delayed signal to the current adjustment unit; when the driving signal requires delay adjustment but does not require current intensity adjustment, the delay adjustment unit works, delays the signal that requires delay adjustment in the driving signal to obtain a delayed signal, and the current adjustment unit does not work, and directly outputs the delayed signal as a display driving signal and a line feed coding signal; when the driving signal requires neither delay adjustment nor current intensity adjustment, the delay adjustment unit and the current adjustment unit may both not work, that is, the delay adjustment unit outputs the driving signal as a delayed signal, and the current adjustment unit directly outputs the delayed signal as a display driving signal and a line feed coding signal.

[0128] For example, under normal circumstances, the line feed coding signal A and the line feed coding signal B are output simultaneously, but due to the external PCB routing problem, the line feed coding signal A is faster than the line feed coding signal B. At this time, in order to achieve simultaneous output, the delay adjustment unit delays and adjusts the line feed coding signal A according to the first control instruction until it is output simultaneously with the line feed coding signal B. The delay adjustment unit, for example, includes a delay adjustment subunit corresponding to each signal, and the delay adjustment subunit, for example, is composed of a plurality of cascaded D-type flip-flops DFF and a multiplexer MUX connected to the output terminal Q of each D-type flip-flop DFF. Each D-type flip-flop can achieve a fixed time delay, for example, 0.1 microseconds. The first control instruction tells the multiplexer MUX to use the output of the third-stage D-type flip-flop as the output signal, then the line feed coding signal A enters the first to third-stage D-type flip-flops to achieve a delay of 0.3 microseconds, and the multiplexer outputs the output signal of the third-stage D-type flip-flop as the line feed coding signal SDOUT after the delay adjustment based on the first control instruction.

[0129] For example, signal loss may occur during transmission, resulting in signal weakening. In order to improve the signal's anti-interference ability, the current regulation unit can enhance the signal current. The current regulation unit, for example, includes: multiple regulation sub-units corresponding to multiple signals, each regulation sub-unit, for example, includes multiple current sources and switching elements respectively connected to each current source. The second control instruction controls the opening and closing of the switching element to adjust the current strength of the signal received by the regulation sub-unit.

[0130] By setting the TTL output signal control circuit 104 in the communication interface module, a signal fine-tuning function is achieved, so that the communication interface chip can cope with different transmission environments and has better applicability.

[0131] Optional, such as Fig.10 As shown, the first interface module 10 also includes a coding processing circuit 107 and a LVDS data output circuit 108, wherein the input end of the coding processing circuit 107 is connected to the output end of the data distribution unit 1023, the data distribution unit 1023 is used to parse the second data signal to obtain the target data signal and the cascade data signal, the data distribution unit 1023 outputs the cascade data signal to the coding processing circuit 107, the coding processing circuit 107 encodes the cascade data signal to obtain the encoded cascade data signal and outputs it to the LVDS data output circuit, the input end of the LVDS data output circuit 108 is connected to the output end of the coding processing circuit 107, the LVDS data output circuit 108 performs parallel-to-serial conversion on the encoded cascade data signal, and outputs the LVDS cascade data signal to the cascaded communication interface chip.

[0132] The structure of the cascaded interface chip is the same as that of the communication interface chip 100. It can be understood here that a pair of LVDS data signals received by the communication interface chip 100 includes multiple data packets, wherein the multiple data packets may only be data required by itself, or may include data required by other communication interface chips, and the data distribution unit 1023 may identify the data required by itself and the data not required by itself, and then keep the data required by itself and output the data not required by itself, wherein the data distribution unit 1023 confirms whether it is its own data by, for example, identifying the identification code of the packet header, when the identification code is the same as its own identification code, it is the data required by itself, i.e., the target data, and when the identification code is different from its own identification code, it is the data not required by itself, i.e., the cascaded data.

[0133] The present application can realize the cascading function of the communication interface chip and increase the application scenarios of the communication interface chip by setting a data distribution unit 1023 in the data analysis circuit 102 of the communication interface chip, and setting an encoding processing circuit 107 and an LVDS data output circuit 108 in the communication interface chip.

[0134] Optional, such as Fig.11 As shown, the first interface module 10 further includes a data packetization circuit 106 and a TTL signal input circuit 105 .

[0135] Specifically, the output end of the TTL signal input circuit 105 is connected to the input end of the data packetization circuit 106, the TTL signal input circuit 105 receives the return data signal, and outputs the return data signal to the data packetization circuit 106. The input end of the data packetization circuit 106 is connected to the data distribution unit 1023, the output end of the data packetization circuit 106 is connected to the input end of the coding processing circuit 107, the data packetization circuit receives the return data signal and the cascade data signal, the data packetization circuit 106 performs packetization processing on the return data signal and the cascade data signal, obtains the packetized cascade return data signal, and transmits it to the coding processing circuit 107, and the return data signal is transmitted in the form of a TTL signal; the coding processing circuit 107 performs coding processing on the packetized cascade return data signal to obtain the coded cascade return data signal; the LVDS data output circuit 108 performs parallel-to-serial conversion processing on the coded cascade return data signal to obtain the LVDS cascade return data, which is output to the cascaded communication interface chip.

[0136] Among them, the feedback data signal is transmitted in the form of a TTL signal, for example, including the inspection data output by the display driver chip, the feedback data and status information, the sensor data output by the sensor, and the monitoring information output by the monitoring circuit. Among them, the inspection data is, for example, the data corresponding to the inspection result of the display unit array, for example, including: bad pixel information of the lamp point, etc. The status information is, for example, the state of the display unit array, for example, including: open circuit information and short circuit information, etc. The feedback data includes, for example, information such as the on-voltage value. The sensor data can be understood as a display device such as a display module that is also provided with a sensor circuit, for example, including temperature sensors, humidity sensors, smoke sensors, and / or voltage sensors and other types of sensors that generate corresponding sensor data to the interface chip. The monitoring information includes, for example, the monitoring information generated by the monitoring circuit monitoring the display driver chip and the display unit array. The LVDS feedback data is, for example, at least one pair of LVDS signals, for example, a pair of LVDS signals, or two pairs of LVDS signals.

[0137] For example, the TTL signal input circuit 105 includes: a clock gating unit and a plurality of D-type flip-flops DFF connected in series, wherein the data input end of the first D-type flip-flop DFF among the plurality of D-type flip-flops DFF receives the return data signal MISO, the data output ends of the plurality of D-type flip-flops are connected to the data packetization circuit, the clock gating unit is connected to the display driver chip to receive the data enable signal DATA_EN and the clock signal SPI_CLK, the output end of the clock gating unit is connected to the clock input end CK of each D-type flip-flop, and the reception of the return data signal transmitted in the form of a TTL signal can be realized through the cooperation of the clock gating unit and the plurality of D-type flip-flops. Among them, the clock gating unit is a circuit using the existing clock gating technology.

[0138] For example, the data packetization circuit 106 includes a counter and a multiplexer connected to the counter, one input end of the multiplexer is connected to the TTL signal input circuit 105 to receive the return data signal, another input end of the multiplexer receives the packet header data, and another input end of the multiplexer receives the packet tail data, so that the counter and the multiplexer can cooperate to realize the packetization processing of the return data signal, that is, add the packet header and the packet tail to complete the packaging process.

[0139] In one embodiment of the present application, Fig.12 As shown, the display device (such as an LED module) includes a plurality of cascaded communication interface chips 100, a plurality of display driver chips 200 and a display unit array 300 (not shown in the figure), wherein each communication interface chip 100 is connected to a display driver chip 200, wherein each display driver chip 200 is electrically connected to a display unit array 300. Among them, the communication interface chip 100 located at the first level is connected to a front-end controller such as an FPGA to receive the LVDS data signal output by the front-end controller and output the aforementioned LVDS cascade data signal to the cascaded M-1 communication interface chips 100, and the cascaded M-1 communication interface chips 100 transmit the M LVDS cascade data signals in sequence and send them to the front-end controller, thereby realizing the cascade function. Among them, the communication interface chip 100 located at the last level is connected to a front-end controller such as an FPGA to output M LVDS cascade data signals, so that the front-end controller such as an FPGA can detect the cascaded multiple communication interface chips 100. The LVDS cascade data signal includes error information, detection information and status information of each of the cascaded plurality of communication interface chips 100 .

[0140] In another embodiment of the present application, the communication interface chip 100 at the first level can output the aforementioned LVDS cascade return data to the cascaded communication interface chip 100, and the communication interface chip 100 at the last level is connected to the front-end controller such as FPGA to output the LVDS cascade return data received by each communication interface chip 100, thereby completing the cascade and return functions. In addition, the communication interface chip 100 at the last level can also package the LVDS cascade return data of the cascaded multiple communication interface chips 100 together and output it to the front-end controller such as FPGA.

[0141] It should be noted that the present embodiment does not limit the specific structure of the TTL signal input circuit 105 and the data packetizing circuit 106. Other circuits that can realize the TTL signal input function are all applicable to the TTL signal input circuit 105, and other circuits that can realize the data packetizing function are all applicable to the data packetizing circuit 106.

[0142] By setting a data distribution module 1023 in the data analysis circuit 102 of the communication interface chip 100, and setting a TTL signal input circuit 105, a data packetization circuit 06, a coding processing circuit 107 and a LVDS data output circuit 108 in the communication interface chip, the cascading and feedback functions of the communication interface chip 100 can be realized, thereby increasing the application scenarios of the communication interface chip 100.

[0143] Exemplarily, the first interface module outputs binary code to the decoding module, and the decoding module is n-line-2 n The 5-32 line decoding chip has 5 input terminals and 32 output terminals. The 5-32 line decoding chip receives the line feed coding signal ABCDE output by the first interface module 10. The following Table 1 shows the logic truth table corresponding to the 5-32 line decoding chip, and digital decoding can be implemented based on the logic truth table. Among them, ABCDE represents the input 5-way binary line feed coding signal, Y0 to Y 31 Represents the 32-way line-feed level signal output by the 5-32 decoding chip.

[0144] Table 1

[0145]

[0146]

[0147] There are 32 outputs in Table 1, so 32 logic function expressions can be obtained. And each expression has only one minimum term. Each binary code can only make one minimum term 1, and make the rest of the minimum terms 0, so that the decoding function is realized. In this embodiment, the high level 1 is set as the effective level, and the low level 0 is set as the invalid level, that is, at any time, only one output terminal of Y0~Y31 outputs 1, and the other 31 output terminals are 0.

[0148] Exemplarily, the decoding module outputs a line-break level signal to the row control module. In this embodiment, the number of MOS tubes is 32, which are respectively connected to the 32 output terminals of the 5-32 decoding chip to respectively control a row of light boards in the display unit array. The display unit array in this embodiment has 32 rows.

[0149] Optionally, the MOS tube working modes include:

[0150] Low-end driver: Fig.13 As shown, the first MOS tube is an N-channel enhancement type MOS tube, the source S is grounded, the gate G is connected to the 5-32 decoding chip, and the drain D is electrically connected to the display unit array. When the 5-32 decoding chip outputs a high level to the first MOS tube, that is, the voltage Vgs between the gate and the source is greater than or equal to the turn-on voltage V GS , the first MOS tube is in the on state, the first row of light arrays corresponding to the first MOS tube in the display unit array is lit, and the other row of light arrays are off; when the 5-32 decoding chip outputs a low level to the first MOS tube, that is, Vgs=0, the first MOS tube is in the off state, the first row of light arrays corresponding to the first MOS tube in the display unit array is off, and any row of light arrays in the display unit except the first row of light arrays is lit;

[0151] High-end driver: Fig.14 As shown, the first MOS tube is a P-channel enhancement type MOS tube, the source S is connected to a high level, the gate G is connected to a 5-32 decoding chip, and the drain D is electrically connected to the display unit array. When the 5-32 decoding chip outputs a low level to the first MOS tube, that is, the voltage Vgs between the gate and the source is less than the turn-on voltage V GS , the first MOS tube is in the on state, the first row of lights corresponding to the first MOS tube in the display unit array is lit, and the other rows of lights are off; when the 5-32 decoding chip outputs a high level to the first MOS tube, that is, Vgs is greater than or equal to the turn-on voltage V GS , the first MOS tube is in the cut-off state, the first row of light arrays corresponding to the first MOS tube in the display unit array is off, and any row of light arrays in the display unit array except the first row of light arrays is lit;

[0152] The first MOS tube is any one of the 32 MOS tubes of the row control module. The first row of light arrays is any one of the 32 rows of the display unit array.

[0153] This embodiment integrates the interface module 10, the decoding module 20 and the row control module 30, and can receive the LVDS data signal output by the front-end controller to generate a driving signal transmitted in the form of a TTL signal, thereby solving the problem that there are too many chips on a single LED module, resulting in the design of the module becoming more and more complicated, and the reliability also decreases with the increase in the number of chips, thereby saving design costs and making the entire LED module smaller, more integrated and more reliable.

[0154] Embodiment 2: Communication interface chip 100B integrating LVDS interface module and decoding module

[0155] like Fig.15 In the second embodiment, the communication interface chip 100B is an interface chip integrating the first interface module 10 and the decoding module 20. Here, the decoding module is a 5-32 line decoding chip as an example for exemplary description.

[0156] Specifically, the first output end of the first interface module 10 is connected to the input end of the decoding module 20; the first interface module 10 receives the LVDS data signal output by the front-end controller, and the first interface module 10 converts the LVDS data signal into a line feed coding signal transmitted in the form of a TTL signal; the first interface module outputs the line feed coding signal to the decoding module, the decoding module receives the line feed coding signal, and outputs the line feed coding signal as a line feed level signal, and the line feed level signal is used to control the line feed of the display unit array.

[0157] The first interface module 10 includes an LVDS interface circuit 101, a data analysis circuit 102, a drive timing recovery circuit 103, and a TTL output signal control circuit 104. The data analysis circuit 102 is electrically connected to the LVDS interface circuit 101, the drive timing recovery circuit 103 is electrically connected to the data analysis circuit 102, and the TTL output signal control circuit 104 is electrically connected to the drive timing recovery circuit 103. The input end of the decoding module 20 is connected to the output end of the TTL output signal control circuit 104, and the TTL output signal control circuit 104 outputs a line feed encoding signal transmitted in the form of a TTL signal to the decoding module 20.

[0158] The circuits included in the first interface module of this embodiment, the constituent units and sub-units of each circuit refer to the first embodiment, and the beneficial effects of this embodiment refer to the first embodiment, which will not be repeated here.

[0159] Embodiment 3: Display device N including communication interface chip 100A

[0160] See also Fig.16In this embodiment, the display device N includes a communication interface chip 100A, a display driver chip 200, and a display unit array 300; the decoding module is taken as a 5-32 row decoding chip as an example for exemplary description.

[0161] Specifically, the input end of the communication interface chip 100A is connected to the output end of the front-end controller, the output end of the communication interface chip 100A is connected to the input end of the display driver chip 200, and the output end of the display driver chip 200 is connected to the display unit array 300; the communication interface chip 100A receives the LVDS data signal, converts the LVDS data signal into a display drive signal, and outputs it to the display driver chip 200, and the display driver chip 200 receives the display drive signal, and the display drive signal is used to light up the display unit array 300. Among them, R-0~R-31 represent 32-way row control signals, and C-0~C-15 represent 16-way column control signals.

[0162] The modules included in the communication interface chip 100A in this embodiment, the constituent circuits of each module, and the constituent units and sub-units of each circuit refer to the first embodiment. The beneficial effects of this embodiment refer to the first embodiment and are not described in detail here.

[0163] Embodiment 4: Display device M including communication interface chip 100B

[0164] See also Fig.17 In this embodiment, the display device M includes a communication interface chip 100B, a row control chip 400, a display driver chip 200, and a display unit array 300; wherein the decoding module is a 5-32 row decoding chip as an example for exemplary description.

[0165] Specifically, the input end of the communication interface chip 100B is connected to the output end of the front-end controller, and the output end of the communication interface chip 100B is respectively connected to the input end of the display driver chip 200 and the input end of the row control chip 400, and the output end of the display driver chip 200 and the output end of the row control chip 400 are respectively connected to the display unit array 300; the communication interface chip 100B receives the LVDS data signal output by the front-end controller, converts the LVDS data signal into a display drive signal and a line-changing level signal, and the communication interface chip 100B then outputs the display drive signal to the display driver chip 200, and the display driver chip 200 receives the display drive signal, and the display drive signal is used to light up the display unit array 300, and the communication interface chip 100B outputs the line-changing level signal to the row control chip 400, and the line-changing level signal is used to control the display unit array 300 to change lines. Among them, R-0~R-31 represent 32-way row control signals, and C-0~C-15 represent 16-way column control signals.

[0166] The communication interface chip 100B is a communication interface chip integrating two modules: a first interface module 10 and a decoding module 20 .

[0167] Specifically, the first output end of the first interface module 10 is connected to the input end of the decoding module 20; the first interface module 10 receives the LVDS data signal output by the front-end controller, and the first interface module 10 converts the LVDS data signal into a line feed coding signal transmitted in the form of a TTL signal; the first interface module transmits the line feed coding signal to the decoding module, the decoding module receives the line feed coding signal, and outputs the line feed coding signal as a line feed level signal, and the line feed level signal is used to control the line feed of the display unit array.

[0168] The modules included in the communication interface chip 100B in this embodiment, the constituent circuits of each module, and the constituent units and sub-units of each circuit refer to the first embodiment. The beneficial effects of this embodiment refer to the first embodiment and are not described in detail here.

[0169] It should be noted that the aforementioned communication interface chip 100 also includes a printed circuit board, which is a PCB circuit board. The LVDS data input circuit 101, the data analysis circuit 102, the drive timing recovery circuit 103, and the TTL signal output control circuit 104 are all arranged on the same printed circuit board.

[0170] Furthermore, the LVDS data input circuit 101, the data analysis circuit 102, the driving timing recovery circuit 103, the TTL signal output control circuit 104, the encoding processing circuit 107 and the LVDS data output circuit 108 are all arranged on the same printed circuit board.

[0171] Furthermore, the LVDS data input circuit 101, the data analysis circuit 102, the drive timing recovery circuit 103, the TTL signal output control circuit 104, the encoding processing circuit 107, the LVDS data output circuit 108, the TTL signal input circuit 105 and the data packaging circuit 106 are all arranged on the same printed circuit board.

[0172] Furthermore, the communication interface chip 100 and the display driver chip 200 are located on the same printed circuit board, for example, thereby increasing the integration of the display device, such as the LED module, and facilitating the miniaturization of the display device, such as the LED module.

[0173] In the several embodiments provided in the present application, it should be understood that the disclosed device can be implemented in other ways. For example, the device embodiments described above are only schematic, for example, the division of modules or units is only a logical function division, and there may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another device, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0174] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

[0175] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A communication interface chip, characterized in that: The communication interface chip includes a first interface module, a decoding module and a row control module; the first output end of the first interface module is connected to the input end of the decoding module, and the output end of the decoding module is connected to the input end of the row control module; The first interface module is used to receive a first signal and generate a line feed encoding signal based on the first signal; The decoding module is used to receive the line feed coding signal output by the first interface module, and decode the line feed coding signal to obtain a line feed level signal; The line control module is used to receive the line break level signal output by the decoding module.

2. The communication interface chip according to claim 1, characterized in that: The output end of the row control module is connected to the display unit array; The row control module is further used to control the display unit array to change rows based on the row change level signal.

3. The communication interface chip according to claim 2, characterized in that: The second output terminal of the first interface module is connected to a display driver chip, and the display driver chip is connected to the display unit array; The first interface module is further configured to generate a display driving signal based on the first signal; The display driving chip is used to receive the display driving signal output by the first interface module, and drive the display unit array to light up or turn off based on the display driving signal.

4. The communication interface chip according to claim 3, characterized in that: The row control module includes 2 n MOS tubes; the line break coding signal is an n-bit coding signal, and the line break level signal is 2 n High / low level signal; Among them, the 2 n The high / low level signals are transmitted to the 2 n MOS tube.

5. The communication interface chip according to any one of claims 1 to 4, characterized in that: The input end of the first interface module is connected to the front-end controller; The front-end controller is used to transmit data signals and control signals to the first interface module; The first interface module is used to obtain the error information of the communication interface chip according to the data signal and the control signal, and return the error information, detection information and status information of the communication interface chip to the front-end controller.

6. The communication interface chip according to any one of claims 1 to 4, characterized in that: The communication interface chip is a cascade combination of communication interface chips, and the cascade combination of communication interface chips includes a first communication interface chip and a second communication interface chip connected in series; The first communication interface chip is used to receive the data signal and the control signal transmitted by the front-end controller, and obtain the error information of the first communication interface chip according to the data signal and the control signal; The first communication interface chip is further used to transmit the data signal and control signal, as well as error information, detection information and status information of the first communication interface chip to the second communication interface chip; The second communication interface chip is used to obtain the bit error information of the second communication interface chip according to the data signal and the control signal; The second communication interface chip is also used to return the error information, detection information and status information of the first communication interface chip, as well as the error information, detection information and status information of the second communication interface chip to the front-end controller.

7. A display device, characterized in that: Comprising a display driver chip, a display unit array, and a communication interface chip as claimed in any one of claims 1 to 6; Among them, the input end of the communication interface chip is connected to the front-end controller, one output end of the communication interface chip is connected to the display unit array, the other output end of the communication interface chip is connected to the input end of the display driver chip, and the output end of the display driver chip is connected to the display unit array.

8. A communication interface chip, characterized in that: The communication interface chip includes a first interface module and a decoding module; the first output end of the first interface module is connected to the input end of the decoding module; The first interface module is used to receive a first signal and generate a line feed encoding signal based on the first signal; The decoding module is used to receive the line feed coding signal output by the first interface module, and decode the line feed coding signal to obtain a line feed level signal.

9. The communication interface chip according to claim 8, characterized in that: The output end of the decoding module is connected to the input end of the row control chip, and the output end of the row control chip is connected to the display unit array; The row control chip is used to receive the row-change level signal output by the decoding module, and control the display unit array to change rows based on the row-change level signal.

10. The communication interface chip according to claim 9, characterized in that: The second output terminal of the first interface module is connected to a display driver chip, and the display driver chip is connected to the display unit array; The first interface module is further configured to generate a display driving signal based on the first signal; The display driving chip is used to receive the display driving signal output by the first interface module, and drive the display unit array to light up or turn off based on the display driving signal.

11. The communication interface chip according to any one of claims 8 to 10, characterized in that: The input end of the first interface module is connected to the front-end controller; The front-end controller is used to output data signals and control signals to the first interface module; The first interface module is also used to obtain the error information of the communication interface chip according to the data signal and the control signal, and return the error information, detection information and status information of the communication interface chip to the front-end controller.

12. The communication interface chip according to any one of claims 8 to 10, characterized in that: The communication interface chip is a cascade combination of communication interface chips, and the cascade combination of communication interface chips includes a first communication interface chip and a second communication interface chip connected in series; The first communication interface chip is used to receive the data signal and the control signal transmitted by the front-end controller, and obtain the error information of the first communication interface chip according to the data signal and the control signal; The first communication interface chip is further used to transmit the data signal and control signal, as well as error information, detection information and status information of the first communication interface chip to the second communication interface chip; The second communication interface chip is used to obtain the bit error information of the second communication interface chip according to the data signal and the control signal; The second communication interface chip is also used to return the error information, detection information and status information of the first communication interface chip, as well as the error information, detection information and status information of the second communication interface chip to the front-end controller.

13. A display device, characterized in that: comprising a display driver chip, a display unit array, a row control chip, and a communication interface chip as claimed in any one of claims 8 to 12; Among them, the input end of the communication interface chip is connected to the front-end controller, one output end of the communication interface chip is connected to the input end of the row control chip, the other output end of the communication interface chip is connected to the input end of the display driver chip, and the output end of the row control chip and the output end of the display driver chip are respectively connected to the display unit array.

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