Semiconductor device

Abstract

The utility model discloses a semiconductor device. The semiconductor device comprises a substrate; the epitaxial structure is positioned on one side of the substrate; the electrode structure is positioned on one side, far away from the substrate, of the epitaxial structure; the electrode structure comprises a source electrode, a drain electrode and a grid electrode located between the source electrode and the drain electrode; the grid electrode comprises a first side surface close to one side of the drain electrode and a first surface far away from one side of the substrate; the source field plate is positioned on one side, far away from the substrate, of the gate and is insulated from the gate; the source field plate is not overlapped with the first surface along the thickness direction of the semiconductor device; the source field plate comprises a first field plate branch and a second field plate branch which are connected, the first field plate branch covers at least part of the first side face, and the second field plate branch is located between the grid electrode and the drain electrode. By adopting the technical means, the source electrode field plate is not overlapped with the first surface, the capacitance between the source electrode field plate and the grid electrode can be reduced, and the performance and the reliability of the semiconductor device are improved.

Description

Technical Field

[0001] The utility model relates to the technical field of microelectronic devices, in particular to a semiconductor device. Background Art

[0002] With the further development of the microelectronics industry, the operating frequency of electronic products is getting higher and higher, and the bandwidth and operating frequency requirements of semiconductor chips are also getting higher and higher. Among them, the gallium nitride high electron mobility transistor (HEMT) is a high electron mobility device formed by the two-dimensional electron gas at the AlGaN or GaN heterojunction, which can be better applied to high frequency, high voltage and high power fields.

[0003] However, when the high electron mobility transistor is working, the distribution of electric field lines in the depletion region of the barrier layer is not uniform, and the edge of the gate close to the drain side often collects most of the electric field lines, so the electric field lines accumulate there and the peak value is large. The high electric field here will increase the gate leakage current and cause the device to break down prematurely, thus preventing the advantages of such devices such as high breakdown voltage and high power from being fully utilized.

[0004] In order to improve the breakdown voltage of high electron mobility transistors and give full play to their advantages of high output power, researchers at home and abroad have proposed many methods, and the source field plate structure is the most effective and widely used one. However, the source field plate will introduce a large gate-source parasitic capacitance, which will weaken the RF performance of HEMT devices. Utility Model Content

[0005] The embodiment of the utility model provides a semiconductor device to reduce the capacitance between the source field plate and the gate and improve the frequency response of the semiconductor device.

[0006] The present invention provides a semiconductor device, comprising:

[0007] substrate;

[0008] An epitaxial structure, located on one side of the substrate;

[0009] An electrode structure, located on a side of the epitaxial structure away from the substrate; the electrode structure comprises a source, a drain, and a gate located between the source and the drain; the gate comprises a first side surface close to the drain and a first surface away from the substrate;

[0010] A source field plate is located on a side of the gate away from the substrate and is insulated from the gate; along the thickness direction of the semiconductor device, the source field plate does not overlap with the first surface; the source field plate includes a first field plate section and a second field plate section connected, the first field plate section covers at least a portion of the first side surface, and the second field plate section is located between the gate and the drain.

[0011] Optionally, the semiconductor device further comprises a dielectric layer located between the gate and the source field plate, the dielectric layer comprising a first dielectric portion covering the first side surface;

[0012] The first dielectric section includes a first dielectric position away from the substrate side, and the first field plate section includes a first field plate position away from the substrate side; the first field plate position is flush with the first dielectric position, or the first field plate position is located on the side of the first dielectric position close to the substrate.

[0013] Optionally, along the thickness direction of the semiconductor device, the height of the first dielectric section is H1, and the height of the first field plate section is H2;

[0014] Among them, H2 / H1≥1 / 2.

[0015] Optionally, the first field plate is flush with the first surface, or the first field plate is located on a side of the first surface close to the substrate.

[0016] Optionally, an extension length of the second field plate section is smaller than an extension length of the first field plate section.

[0017] Optionally, an extension length L of the second field plate portion satisfies 0<L≤400nm.

[0018] Optionally, at any two positions of the first field plate section, the thickness of the first field plate section is the same.

[0019] Optionally, the dielectric layer further includes a second dielectric portion covering the first surface;

[0020] The semiconductor device further includes a protection layer, which covers the dielectric layer and the source field plate, and the protection layer is in contact with the second dielectric portion.

[0021] Optionally, the semiconductor device further comprises a field plate connection portion, wherein the field plate connection portion is electrically connected to the source field plate and the source respectively;

[0022] The semiconductor device comprises an active region and an inactive region surrounding the active region;

[0023] The source electrode and the source field plate are located in the active region, and the field plate connecting portion is located in the inactive region.

[0024] Optionally, the epitaxial structure:

[0025] A nucleation layer, located on one side of the substrate;

[0026] A buffer layer, located on a side of the nucleation layer away from the substrate;

[0027] A channel layer, located on a side of the buffer layer away from the substrate;

[0028] The barrier layer is located at a side of the channel layer away from the substrate, and the barrier layer and the channel layer form a heterojunction structure.

[0029] According to the technical solution of the embodiment of the utility model, the semiconductor device includes a source field plate located on a side of the gate away from the substrate and insulated from the gate. Along the thickness direction of the semiconductor device, the source field plate does not overlap with the first surface, the first field plate portion covers at least a portion of the first side surface, and the second field plate portion is located between the gate and the drain. That is, the source field plate is not arranged on the upper surface of the gate, and the source field plate only covers the first side surface of the gate. In this way, the facing area between the gate and the source field plate can be reduced, thereby reducing the parasitic capacitance between the gate and the source field plate, and improving the performance and reliability of the semiconductor device.

[0030] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present utility model, nor are they intended to limit the scope of the present utility model. Other features of the present utility model will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 A schematic top view of a semiconductor device provided by an embodiment of the utility model;

[0032] Figure 2 for Figure 1 A schematic diagram of a cross-sectional structure of a semiconductor device along a cross-sectional line AA' is provided;

[0033] Figure 3 for Figure 1 A schematic cross-sectional structure diagram of another semiconductor device along a cross-sectional line AA' is provided;

[0034] Figure 4 for Figure 1 A schematic cross-sectional structure diagram of another semiconductor device along the cross-sectional line AA' is provided. DETAILED DESCRIPTION

[0035] In order to enable those skilled in the art to better understand the solution of the utility model, the technical solution in the embodiment of the utility model will be clearly and completely described below in conjunction with the drawings in the embodiment of the utility model. Obviously, the described embodiment is only a part of the embodiment of the utility model, not all of the embodiments. Based on the embodiment of the utility model, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the utility model.

[0036] Before describing in detail the technical solution of the embodiment of the utility model, the parasitic capacitance that affects the performance of the semiconductor device is first described.

[0037] HEMT is a wide bandgap semiconductor device with high concentration of two-dimensional electron gas (2DEG). It has the advantages of high output power density, high temperature resistance, strong stability and high breakdown voltage. It has great application potential in both radio frequency and power electronic devices. In order to achieve high performance at high frequency, the parasitic capacitance of the device needs to be minimized in the structural design of semiconductor devices.

[0038] The parasitic capacitance of semiconductor devices is mainly divided into gate-source capacitance, gate-drain capacitance and source-drain capacitance. Among them, gate-source capacitance has the greatest impact on device frequency. There are two main sources of gate-source capacitance of semiconductor devices, one is the parasitic capacitance of gate metal and channel, and the other is the capacitance of gate metal and source field plate.

[0039] When the semiconductor device is working, the source field plate and the source are both at zero potential. At this time, the source field plate can increase the area of ​​the depletion region on the side of the gate close to the drain, increase the drain-source voltage that the depletion region can bear, and thus increase the breakdown voltage of the device; at the same time, the source field plate is used to modulate the distribution of the electric field lines in the depletion region of the barrier layer, reducing the gate leakage current. The technical solution of the embodiment of the utility model aims to reduce the parasitic capacitance between the gate and the source field plate by designing the source field plate, thereby improving the performance and reliability of the semiconductor device. The technical solution of the embodiment of the utility model is described in detail below.

[0040] Figure 1 A schematic top view of a semiconductor device provided by an embodiment of the utility model, Figure 2 for Figure 1 A schematic diagram of a cross-sectional structure of a semiconductor device along a cross-sectional line AA' is provided, as shown in FIG. Figure 1 and Figure 2As shown, the semiconductor device includes a substrate 10; an epitaxial structure 20, which is located on one side of the substrate 10; an electrode structure 30, which is located on the side of the epitaxial structure 20 away from the substrate 10; the electrode structure 30 includes a source 301, a drain 302 and a gate 303 located between the source 301 and the drain 302; the gate 303 includes a first side 3031 close to the drain 302 and a first surface 3032 away from the substrate 10; a source field plate 40, which is located on the side of the gate 303 away from the substrate 10 and is insulated from the gate 10; along the thickness direction of the semiconductor device (Z direction as shown in the figure), the source field plate 40 does not overlap with the first surface 3032; the source field plate 40 includes a first field plate section 401 and a second field plate section 402 connected, the first field plate section 401 covers at least a portion of the first side 3031, and the second field plate section 402 is located between the gate 303 and the drain 302.

[0041] Exemplarily, the substrate 10 may be aluminum gallium nitride, gallium nitride, aluminum gallium arsenic, gallium arsenic, silicon carbide or silicon, etc. The embodiment of the utility model does not specifically limit the type of the material of the substrate 10. The epitaxial structure 20 located on one side of the substrate 10 may be formed of one or more of III-V group nitrides such as gallium nitride, aluminum gallium nitride, indium gallium nitride, aluminum nitride or indium aluminum gallium nitride. Exemplarily, the thickness of the substrate 10 may be 100 μm-1000 μm.

[0042] Further, the electrode structure 30 located on the side of the epitaxial structure 20 away from the substrate 10 includes a source 301, a drain 302, and a gate 303 located between the source 301 and the drain 302. Both the source 301 and the drain 3021 can form an ohmic contact with the epitaxial structure 20. Exemplarily, the source 301 can be used as the input end of the semiconductor device, the drain 302 can be used as the output end of the semiconductor device, and the gate 303 can be used as the control end of the semiconductor device. The current flow between the source 301 and the drain 302 can be achieved by controlling the voltage of the gate 303. The semiconductor device may also include a gate pad 304, which is connected to the gate 303 in the active area aa, and provides a gate voltage signal to the gate 303 to ensure the normal operation of the semiconductor device. Exemplarily, the materials of the source 301, the drain 302, the gate 303 and the source field plate 40 can be gold, silver, copper, iron, aluminum, indium, platinum, titanium, nickel and other metals or alloys formed by any combination.

[0043] Specifically, the source field plate 40 is located on the side of the gate 303 away from the substrate 10 and is insulated from the gate 303, that is, the source field plate 40 does not contact the gate 303, but the insulation setting of the gate 303 and the source field plate 40 is achieved by setting a dielectric layer 50 on the upper surface and side of the gate 303.

[0044] Furthermore, along the thickness direction Z of the semiconductor device, the source field plate 401 does not overlap with the first surface 3032, and the source field plate 40 includes a first field plate portion 401 and a second field plate portion 402 connected to each other, the first field plate portion 401 covers at least a portion of the first side surface 3031, and the second field plate portion 402 is located between the gate 303 and the drain 302, that is, the source field plate 40 is not arranged on the upper surface of the gate 303, and the first field plate portion 401 and the second field plate portion 402 of the source field plate 40 can form an "L" shape on the first side surface 3031, thereby reducing the facing area of ​​the source field plate 40 and the gate 303, thereby reducing the parasitic capacitance between the gate 303 and the source field plate 40, and improving the performance and reliability of the semiconductor device.

[0045] It should be noted that, since there is a dielectric layer 50 between the film layer where the gate 303 is located and the film layer where the source field plate 40 is located, the dielectric layer 50 forms a dielectric layer top corresponding to the top of the gate 303 and a dielectric layer side corresponding to the side of the gate 303. Therefore, the first field plate subsection 401 in the implementation of the utility model covers at least part of the first side 3031, which does not mean that the first field plate subsection 401 directly covers the first side 3031 of the gate 303, but means that the first field plate subsection 401 includes a portion corresponding to the first side 3031 of the gate 303. Or it can be understood that along the thickness direction of the semiconductor device, the first field plate subsection 401 includes a portion overlapping with the side of the dielectric layer.

[0046] In the semiconductor device provided by the embodiment of the utility model, along the thickness direction of the semiconductor device, the source field plate does not overlap with the first surface, the first field plate portion covers at least a portion of the first side surface, and the second field plate portion is located between the gate and the drain. That is, no source field plate is arranged on the upper surface of the gate, and the source field plate only covers the first side surface of the gate. In this way, the facing area between the gate and the source field plate can be reduced, thereby reducing the parasitic capacitance between the gate and the source field plate, and improving the performance and reliability of the semiconductor device.

[0047] Optional, Figure 3 for Figure 1 Another schematic diagram of the cross-sectional structure of a semiconductor device provided along the cross-sectional line AA' is shown in FIG. Figure 2 and Figure 3 The semiconductor device also includes a dielectric layer 50 located between the gate 303 and the source field plate 40, the dielectric layer 50 includes a first dielectric section 501 covering the first side 3031; the first dielectric section 501 includes a first dielectric position a1 away from the side of the substrate 10, and the first field plate section 401 includes a first field plate position b1 away from the side of the substrate 10; the first field plate position b1 is flush with the first dielectric position a1, or the first field plate position b1 is located on the side of the first dielectric position a1 close to the substrate 10.

[0048] Specifically, as a feasible implementation method, continue to refer to Figure 2 , the first field plate position b1 is flush with the first dielectric position a1, that is, the first field plate position b1 and the first dielectric position a1 are located on the same horizontal line, that is, the first field plate position b1 does not exceed the first side surface 3031 of the gate 303 and does not overlap with the first surface 3032, which is conducive to improving the RF performance of the semiconductor device. As another feasible implementation, continue to refer to Figure 3 The first field plate position b1 is located on the side of the first dielectric position a1 close to the substrate 10, that is, the first field plate position b1 is lower than the first dielectric position a1, which further reduces the parasitic capacitance between the gate and the source, especially the parasitic capacitance caused by the gate sidewall, thereby improving the comprehensive performance of the semiconductor device.

[0049] For example, the material of the dielectric layer 50 may be silicon dioxide, silicon nitride, or aluminum oxide.

[0050] Optional, continue to refer to Figure 3 , along the thickness direction Z of the semiconductor device, the height of the first dielectric section 501 is H1, and the height of the first field plate section 401 is H2; wherein H2 / H1≥1 / 2.

[0051] Specifically, the height H1 of the first dielectric section 501 and the height H2 of the first field plate section 401 satisfy H2 / H1≥1 / 2, thereby ensuring the performance of the source field plate 40, thereby improving the radio frequency performance of the semiconductor device and strengthening the regulation of the electric field peak at the edge of the first side surface 3031, which is beneficial to improving the overall performance of the device.

[0052] Exemplarily, when H2 / H1 < 1 / 2, it means that the height H2 of the first field plate portion 401 is significantly different from the height H1 of the first dielectric portion 501 , which is not conducive to improving the breakdown voltage of the high electron mobility transistor through the source field plate 40 .

[0053] Optional, continue to refer to Figure 3 The first field plate position b1 is flush with the first surface 3032 , or the first field plate position b1 is located on a side of the first surface 3032 close to the substrate 10 .

[0054] Specifically, as a feasible implementation, the first field plate position b1 is flush with the first surface 3032, that is, the upper surface of the first field plate portion 401 away from the substrate 10 is on the same horizontal line as the first surface 3032, and the first field plate portion 401 just covers the entire first side surface 3031, which can reduce the parasitic capacitance between the gate 303 and the source field plate 40, thereby improving the performance of the semiconductor device.

[0055] It should be noted that Figure 3Only the technical solution in which the first field plate position b1 is flush with the first surface 3032 is shown. It can be understood that the first field plate position b1 is located on the side of the first surface 3032 close to the substrate 10, that is, the upper surface of the first field plate portion 401 away from the substrate 10 is closer to the substrate 10 than the first surface 3032. In this way, the first field plate portion 401 only covers a portion of the first side surface 3031, which can further reduce the parasitic capacitance between the source field plate 40 and the gate 303, and further improve the performance of the semiconductor device.

[0056] Optional, continue to refer to Figure 2 , an extension length of the second field plate sub-portion 402 is less than an extension length of the first field plate sub-portion 401 .

[0057] Specifically, the extension length of the second field plate section 402 is smaller than the extension length of the first field plate section 401, that is, the extension length of the second field plate section 402 located between the gate 303 and the drain 302 on the surface of the dielectric layer 50 is smaller than the extension length of the first field plate section 401 covering the first side surface 3031 on the surface of the dielectric layer 50. This is beneficial to balanced electric field regulation on the one hand, and can reduce the parasitic capacitance between the gate 303 and the drain 302 on the other hand, thereby ensuring the performance of the semiconductor device.

[0058] Optional, continue to refer to Figure 2 , the extension length L of the second field plate portion 402 satisfies 0<L≤400nm, that is, the extension length L of the second field plate portion 402 located between the gate 303 and the drain 302 satisfies 0<L≤400nm, which is beneficial to reduce the parasitic capacitance between the gate 303 and the drain 302 and ensure the working performance of the semiconductor device.

[0059] Exemplarily, the extension length L of the second field plate portion 402 may be L=100 nm, L=200 nm, L=300 nm or L=400 nm.

[0060] Optional, continue to refer to Figure 2 , the thickness of the first field plate sub-portion 401 is the same at any two positions of the first field plate sub-portion 401 .

[0061] As a comparative example, in the prior art, the source field plate 40 includes two source field plate sections covering at least a portion of the first surface 3032 and a portion of the first side surface 3031. In order to reduce the parasitic capacitance between the gate 303 and the source field plate 40, the source field plate section covering at least a portion of the first surface 3032 can be disconnected from the source field plate section covering at least a portion of the first side surface 3031. In this way, the thickness of the source field plate section is uneven, and the thickness of the source field plate located at the junction of the upper surface and the side surface of the gate 303 is thinner. Specifically, the thickness of any two positions in the first field plate section 401 is the same. That is to say, in the process of preparing the source field plate 40 in the embodiment of the utility model, a whole layer of the source field plate 40 can be first deposited on the first surface 3032 and the first side surface 3031 of the gate 303, and then the source field plate 40 at the position of the first surface 3032 can be etched away through an etching process. On the one hand, this can ensure that the source field plate 40 does not overlap with the first surface 3032. On the other hand, it is beneficial to ensure that the thickness of any two positions in the first field plate section 401 is the same, and the preparation process is simple.

[0062] Optional, Figure 4 for Figure 1 A schematic cross-sectional structure diagram of another semiconductor device along the cross-sectional line AA' is provided, as shown in FIG. Figure 4 As shown, the dielectric layer 50 further includes a second dielectric portion 502 covering the first surface 3032 ; the semiconductor device further includes a protective layer 60 , which covers the dielectric layer 50 and the source field plate 40 , and is in contact with the second dielectric portion 502 .

[0063] Specifically, the protective layer 60, also known as the passivation layer, is used to protect the semiconductor device. The protective layer 60 covers the dielectric layer 50 and the source field plate 40, and the protective layer 60 is in contact with the second dielectric portion 502. In this way, during the preparation of the semiconductor device, the source field plate 40 is first deposited on the first surface 3032 and the first side surface 3031 of the gate 303, and then the source field plate 40 on the first surface 3032 is removed by etching. In this way, it can be ensured that the protective layer 60 is in contact with the second dielectric portion 502, and the protective layer 60 can protect the semiconductor device.

[0064] Exemplarily, the protection layer 60 may cover the entire semiconductor device.

[0065] It is understood that the protective layer 60 can be a single layer, or multiple layers having the same or different compositions.

[0066] Specifically, the material of the protective layer 60 may include, for example, but not limited to, a dielectric material. For example, the protective layer 60 may include Si 3 N 4, SiON, SiC, SiBN, SiCBN, oxide, nitride, oxide, plasma enhanced oxide (PEOX) or a combination thereof.

[0067] Optional, continue to refer to Figure 1 The semiconductor device also includes a field plate connection portion 70, which is electrically connected to the source field plate 40 and the source 301 respectively; the semiconductor device includes an active area aa and an inactive area bb surrounding the active area aa; the source 301 and the source field plate 40 are located in the active area aa, and the field plate connection portion 70 is located in the inactive area bb.

[0068] Specifically, the active region aa can be understood as a region where two-dimensional electron gas, electrons or holes exist below it, and its working state and characteristics are affected by the external circuit, and it is the active working region of the semiconductor device. The passive region bb participates in the work of the semiconductor device, but its working state is not affected by the external circuit. For example, the lead-out structure of the electrode in the active region aa can be set in the passive region bb, and the passive region bb can be set around the active region aa.

[0069] Specifically, the field plate connection portion 70 is located in the passive region bb, which can realize the electrical connection between the source field plate 40 and the source 301, realize the modulation effect of the source field plate 30 on the electric field, and can suppress the maximum electric field strength in the channel region and increase the breakdown voltage. In addition, the field plate connection portion 70 is located in the passive region bb, which will not affect the normal operation and performance of the active region aa, and ensure the stable performance of the semiconductor device. In addition, since there is a large setting space in the passive region bb, the field plate connection portion 70 set in the passive region bb can have a large degree of design freedom.

[0070] Optional, continue to refer to Figure 2 , epitaxial structure 20: a nucleation layer 201, located on one side of the substrate 10; a buffer layer 202, located on the side of the nucleation layer 201 away from the substrate 10; a channel layer 203, located on the side of the buffer layer 202 away from the substrate 10; a barrier layer 204, located on the side of the channel layer 203 away from the substrate 10, the barrier layer 204 and the channel layer 203 form a heterojunction structure, i.e., a two-dimensional electron gas.

[0071] For example, continue to refer to Figure 2 The material of the nucleation layer 201 may be aluminum nitride, and is located between the substrate 10 and the buffer layer 202. The nucleation layer 201 affects the crystal quality, surface morphology, and electrical properties of the heterojunction material above. The nucleation layer 201 varies with different substrate materials, and mainly plays a role in matching the substrate material and the semiconductor material layer in the heterojunction structure. Exemplarily, the thickness of the nucleation layer 201 may be 20 nm.

[0072] For example, continue to refer to Figure 2, the buffer layer 202 is located on one side of the substrate 10. The material of the buffer layer 202 may be gallium nitride, and the buffer layer 202 may include iron atoms, which is conducive to achieving the high resistance of the buffer layer 202, ensuring that vertical leakage can be blocked and the pinch-off performance of the semiconductor device can be improved. The buffer layer 202 can play the role of bonding the semiconductor material layer that needs to be grown next, and can protect the substrate 10 from being invaded by some metal ions. The material of the buffer layer 202 can be a group III nitride material such as AlGaN, GaN or AlGaInN. Exemplarily, the thickness of the buffer layer 202 can be 0.1μm-10μm.

[0073] For example, continue to refer to Figure 2 The channel layer 203 may be a group III nitride, such as Al x Ga 1－x N, where 0≤x<1, that is, at the interface between the channel layer 203 and the barrier layer 204, that is, the energy of the conduction band edge of the channel layer 203 is less than the energy of the conduction band edge of the barrier layer 204. Exemplarily, x=0 indicates that the channel layer 203 is GaN. The channel layer 203 may also be other group III nitrides, such as InGaN and AlInGaN. The channel layer 203 may be undoped or unintentionally doped. The channel layer 203 may also be a multilayer structure, such as a combination of a superlattice, GaN or AlGaN. Exemplarily, the thickness of the channel layer 203 may be 0.1μm-10μm.

[0074] For example, continue to refer to Figure 2 The barrier layer 204 may be AlN, AlInN, AlGaN or AlInGaN. The barrier layer 204 has a sufficient thickness and a sufficiently high Al composition to form a significant carrier concentration at the interface between the channel layer 203 and the barrier layer 204.

[0075] For example, continue to refer to Figure 2 , the channel layer 203 may include GaN, and the barrier layer 204 may include AlGaN, that is, the material of the barrier layer 204 has a higher band gap than the material of the channel layer 203, and the channel layer 203 may also have a greater electron affinity than the barrier layer 204. Due to the band gap difference between the barrier layer 204 and the channel layer 203 and the piezoelectric polarization effect between the barrier layer 204 and the channel layer 203, a two-dimensional electron gas is formed between the channel layer 203 and the barrier layer 204. Exemplarily, the thickness of the barrier layer 204 may be 1nm-1μm.

[0076] It is understandable that the epitaxial structure 20 may further include a cap layer, which is located on the surface of the barrier layer 204 away from the substrate 10. The cap layer can reduce the surface state, reduce the surface leakage of the subsequent semiconductor device, and inhibit current collapse, thereby improving the performance and reliability of the epitaxial structure 20 and the semiconductor device.

[0077] It should be understood that from the perspective of semiconductor device design, the embodiment of the utility model can reduce the capacitance between the source field plate and the gate and improve the frequency response of the semiconductor device by setting an "L"-shaped source field plate, and the source field plate and the upper surface of the gate do not overlap. The semiconductor devices include but are not limited to: high-power high electron mobility transistors (HEMT) operating in high voltage and high current environments, transistors with silicon-on-insulator (SOI) structures, transistors based on gallium arsenide (GaAs), and metal-oxide-semiconductor field-effect transistors (MOSFET), metal-insulator semiconductor field-effect transistors (MISFET), double heterojunction field-effect transistors (DHFET), junction field-effect transistors (JFET), metal-semiconductor field-effect transistors (MESFET), and metal-semiconductor heterojunction field-effect transistors (MESFET). Transistor, referred to as MISHFET) or other field effect transistors. The source field plate provided in the semiconductor device provided by the embodiment of the utility model can be widely used in the semiconductor device manufacturing fields such as radio frequency microwave and power electronics. In particular, the advantages of gallium nitride electronic devices with large bandgap width, high electron mobility, high breakdown field strength and good thermal conductivity are more obvious, and can better meet the high performance requirements of the rapidly developing electronic communication and other fields.

[0078] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention is described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A semiconductor device, characterized in that: include: substrate; An epitaxial structure, located on one side of the substrate; An electrode structure, located on a side of the epitaxial structure away from the substrate; the electrode structure comprises a source, a drain, and a gate located between the source and the drain; the gate comprises a first side surface close to the drain and a first surface away from the substrate; a source field plate, located on a side of the gate away from the substrate and insulated from the gate; along the thickness direction of the semiconductor device, the source field plate does not overlap with the first surface; The source field plate includes a first field plate section and a second field plate section connected to each other, wherein the first field plate section covers at least a portion of the first side surface, and the second field plate section is located between the gate and the drain.

2. The semiconductor device according to claim 1, wherein: The semiconductor device further comprises a dielectric layer located between the gate and the source field plate, the dielectric layer comprising a first dielectric portion covering the first side surface; The first dielectric section includes a first dielectric position away from the substrate side, and the first field plate section includes a first field plate position away from the substrate side; the first field plate position is flush with the first dielectric position, or the first field plate position is located on the side of the first dielectric position close to the substrate.

3. The semiconductor device according to claim 2, characterized in that Along the thickness direction of the semiconductor device, the height of the first dielectric section is H1, and the height of the first field plate section is H2; Among them, H2 / H1≥1 / 2.

4. The semiconductor device according to claim 2, characterized in that The first field plate is flush with the first surface, or the first field plate is located on a side of the first surface close to the substrate.

5. The semiconductor device according to claim 1, wherein: An extension length of the second field plate section is less than an extension length of the first field plate section.

6. The semiconductor device according to claim 5, characterized in that An extension length L of the second field plate section satisfies 0<L≤400 nm.

7. The semiconductor device according to claim 1, wherein: At any two positions of the first field plate section, the thickness of the first field plate section is the same.

8. The semiconductor device according to claim 2, wherein: The dielectric layer further includes a second dielectric portion covering the first surface; The semiconductor device further includes a protection layer, which covers the dielectric layer and the source field plate, and the protection layer is in contact with the second dielectric portion.

9. The semiconductor device according to claim 1, wherein: The semiconductor device further comprises a field plate connection portion, wherein the field plate connection portion is electrically connected to the source field plate and the source electrode respectively; The semiconductor device comprises an active region and an inactive region surrounding the active region; The source electrode and the source field plate are located in the active region, and the field plate connecting portion is located in the inactive region.

10. The semiconductor device according to claim 1, wherein: The epitaxial structure: A nucleation layer, located on one side of the substrate; A buffer layer, located on a side of the nucleation layer away from the substrate; A channel layer, located on a side of the buffer layer away from the substrate; The barrier layer is located at a side of the channel layer away from the substrate, and the barrier layer and the channel layer form a heterojunction structure.

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