Bottom chip and corresponding semiconductor power device stacked core structure
By designing the metal layer on the top of the source and drain in the stacked core structure of semiconductor power devices, and using the insulating layer to open windows to achieve electrical connection, the problem of high resistance in the traditional stacked core structure is solved, and a more optimized current distribution is achieved and cost reduction.
Patent Information
- Application Number
- CN202420564482.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-03-21
- Publication Date
- 2024-12-17
- Estimated Expiration
- 2034-03-21
AI Technical Summary
In the traditional semiconductor power device stack structure, due to the large area of the Source pad of the wide bandgap HEMT, the series resistance in the top metal interconnect structure of the Drain electrode is higher, which increases the resistance and cost per unit area of the chip.
Design a bottom chip, which is equipped with a parallel metal layer on the top of the source and drain, and realizes the electrical connection between the upper and lower chips through the insulating layer window. The metal layer on the top of the drain extends below the top chip to increase the area and reduce the Resistance while maintaining insulation from the top chip.
The series resistance of the source and drain metals is effectively reduced, the resistance per unit area of the chip is reduced, the cost is reduced, and the current distribution is optimized.
Smart Images
Figure CN222190733U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the field of semiconductor devices, in particular to a bottom chip and a corresponding semiconductor power device stacked core structure. Background Art
[0002] Cascade-structured gallium nitride (GaN) semiconductor power devices are usually a high-voltage D-mode (Deplet ion-Mode) wide-bandgap HEMT (High electron mobility transistor, a type of field effect transistor) device and a low-voltage Si MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor, metal-oxide-semiconductor field-effect transistor, referred to as gold-oxide semiconductor field-effect transistor) device. Its driver is compatible with traditional N-channel MOS controllers. Compared with E-mode (Enhancement-Mode) gallium nitride HEMT, there is no need to redesign the circuit, while retaining the advantages of low switching loss of gallium nitride and low gate charge of low-voltage N-channel MOS.
[0003] In order to reduce the parasitic parameters in the entire cascade structure package, save area and improve the overall performance, there is a die on die (stacked core) packaging form in the industry, which fixes the Si MOSFET on the wide bandgap device Source Pad (source top metal layer) through conductive adhesive materials, reducing the parasitic parameters brought by the bottom metal layer between the Si MOSFET drain and the wide bandgap device source in the traditional cascade structure.
[0004] For the traditional stacked core cascade structure, in order to accommodate a larger area of Si MOSFET, the Source pad of the wide bandgap HEMT is generally larger in area, and the top metal of the Drain electrode cannot be set under the MOSFET, which limits the distribution of the top metal of the Drain electrode, resulting in a higher series resistance in the metal interconnection structure of the Drain electrode, thereby increasing the resistance per unit area of the entire chip and increasing the cost. Utility Model Content
[0005] The utility model provides a bottom chip and a corresponding semiconductor power device stacked core structure, which can reduce the series resistance in the interconnection structure.
[0006] The utility model embodiment provides a bottom chip, which is used in a semiconductor power device stacked core structure, wherein the upper surface of the bottom chip is provided with a source connection metal area for connecting to a top chip and a drain connection metal area for connecting to a packaging structure; the bottom chip is provided with a source bottom metal layer, a drain bottom metal layer, a source top metal layer, a drain top metal layer and an insulating layer;
[0007] The source top metal layer is located above the source bottom metal layer and is electrically connected to the source bottom metal layer; its two ends are respectively located at the source connection metal region and the drain connection metal region; the drain top metal layer is located above the drain bottom metal layer and is electrically connected to the drain bottom metal layer; its two ends are respectively located at the source connection metal region and the drain connection metal region; the source top metal layer and the drain top metal layer are spaced apart in the source connection metal region;
[0008] The insulating layer covers the source top metal layer and the drain top metal layer, and the insulating layer is provided with a source window and a drain window. The source window is located in the source connection metal area and is arranged corresponding to the source top metal layer, and the source top metal layer is connected to the top chip through the source window; the drain window is located in the drain connection metal area and is arranged corresponding to the drain top metal layer, and the drain top metal layer is connected to the packaging structure through the drain window.
[0009] The bottom chip and the corresponding semiconductor power device stacked core structure provided by the utility model can effectively reduce the resistance of the electrode bottom metal layer and the drain bottom metal layer through the parallel structure of the source top metal layer and the source bottom metal layer, and the parallel structure of the drain top metal layer and the drain bottom metal layer, so that the entire semiconductor power device obtains a more optimized current distribution and greatly reduces the series resistance in the interconnection structure; the electrical connection between the upper and lower chips can be achieved through the source window; the electrical connection between the bottom chip and the packaging structure is achieved through the drain window; one end of the drain top metal layer is located in the source connection metal area, so that the drain top metal layer can extend to the bottom of the top chip, increase the area of the drain top metal layer, reduce the resistance, and reduce the chip unit area resistance, and the drain top metal layer can maintain insulation from the top chip through the insulating layer; the utility model can effectively reduce the source and drain metal series resistance and reduce the chip unit area resistance through the arrangement of the source top metal layer and the drain top metal layer. BRIEF DESCRIPTION OF THE DRAWINGS
[0010] Figure 1 A schematic structural diagram of a semiconductor power device stacked core structure provided by the first embodiment of the utility model;
[0011] Figure 2 for Figure 1 A schematic diagram of the structure of the bottom chip of the stacked core structure of a semiconductor power device;
[0012] Figure 3a-3c for Figure 2 Schematic diagram of the layout of the components of the mid- and bottom-layer chips;
[0013] Figure 4 A schematic structural diagram of a semiconductor power device stacked core structure provided in another embodiment of the present invention.
[0014] Figure 5 A schematic diagram of the structure of the bottom chip provided for the second embodiment of the utility model;
[0015] Figure 6 A schematic diagram of the structure of the bottom chip provided in the third embodiment of the utility model;
[0016] Figure 7 A schematic diagram of the structure of the bottom chip provided in the fourth embodiment of the utility model;
[0017] Figure 8 This is a schematic diagram of the structure of the bottom chip provided in the fifth embodiment of the utility model. DETAILED DESCRIPTION
[0018] The following will be combined with the drawings in the embodiments of the utility model to clearly and completely describe the technical solutions in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments of the utility model, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the utility model.
[0019] In the figures, structurally similar elements are denoted by the same reference numerals.
[0020] Please refer to Figure 1 A preferred embodiment of the utility model provides a semiconductor power device stacked core structure, including a bottom chip 100 and a top chip 200 connected above the bottom chip 100 .
[0021] like Figure 2 As shown, the upper surface of the bottom chip 100 is provided with a source connection metal area 101 for connecting to the top chip 200 and a drain connection metal area 102 for connecting to the package structure. The top chip 200 can be mounted to the source connection metal area 101, and the source connection metal area 101 and the drain connection metal area 102 are arranged in the longitudinal direction. In this embodiment, the source connection metal area 101 and the drain connection metal area 102 are both relatively regular square areas to facilitate the structural layout design.
[0022] Combination Figure 2 and Figure 3a As shown, the bottom chip 100 is provided with a source bottom metal layer 11, a drain bottom metal layer 21, a source top metal layer 12, a drain top metal layer 22, and an insulating layer 3. In this embodiment, the bottom chip 100 is only provided with one source bottom metal layer 11 and one drain bottom metal layer 21.
[0023] In the present embodiment, the length directions of the source bottom metal layer 11 and the drain bottom metal layer 21 are both horizontal. Of course, as other feasible implementation methods, according to the different positions and arrangements of the drain connection metal area and the source connection metal area, the source bottom metal layer 11 and the drain bottom metal layer 21 are not necessarily parallel to each other, nor do they necessarily extend in the longitudinal direction.
[0024] In this embodiment, the source top metal layer 12 is arranged along the vertical direction of the source bottom metal layer 11, and an insulating film 41 and a through hole 42 are arranged on the surface of the source bottom metal layer 11. The source bottom metal layer 11 is electrically connected to the source top metal layer 12 through the through hole 42. The source top metal layer 12 is located above the source bottom metal layer 11 and the source top metal layer 12, and its two ends are respectively located at the source connection metal region 101 and the drain connection metal region 102.
[0025] The drain top metal layer 22 is arranged along the vertical direction of the drain bottom metal layer 21, and an insulating film 41 and a through hole 42 are arranged on the surface of the drain bottom metal layer 21. The drain bottom metal layer 21 is electrically connected to the drain top metal layer 22 through the through hole 42. The drain top metal layer 22 is located above the drain bottom metal layer 21 and the source bottom metal layer 11, and its two ends are respectively located at the source connection metal area 101 and the drain connection metal area 102. The source top metal layer 12 and the drain top metal layer 22 are spaced apart to insulate the two.
[0026] In this embodiment, the source top metal layer 12 and the drain top metal layer 22 are both rectangular and regular in shape, which is convenient for processing and preparation. Of course, in other embodiments, the ends of the source top metal layer and the drain top metal layer may also be other shapes.
[0027] Through the parallel structure of the source top metal layer 12 and the source bottom metal layer 11, and the parallel structure of the drain top metal layer 22 and the drain bottom metal layer 21, compared with the separate source bottom metal layer 11 and the drain bottom metal layer 21, the source top metal layer and the drain top metal layer can effectively reduce the resistance at the corresponding position, reduce the parasitic parameters brought by the bottom metal layer, so that the entire semiconductor power device obtains a more optimized current distribution, greatly reduces the series resistance in the interconnection structure, and thus makes the cost lower under the same specifications.
[0028] Combination Figure 2 and Figure 3bAs shown, the bottom chip 100b is provided with a first source bottom metal layer 11a, a second source bottom metal layer 11b, a first drain bottom metal layer 21a and a second drain bottom metal layer 21b.
[0029] In this embodiment, the source top metal layer 12 is arranged along the vertical direction of the first source bottom metal layer 11a, and an insulating film 41 and a through hole 42 are arranged on the surface of the first source bottom metal layer 11a. The first source bottom metal layer 11a is electrically connected to the source top metal layer 12 through the through hole 42. The source top metal layer 12 is located above the first source bottom metal layer 11a and the first drain bottom metal layer 21a, and its two ends are respectively located at the source connection metal region 101 and the drain connection metal region 102.
[0030] The second source bottom metal layer 11b is located below the first source bottom metal layer 11a and is arranged parallel to the first source bottom metal layer 11a. A through hole 43 is arranged on the surface of the second source bottom metal layer 11b, and the second source bottom metal layer 11b is connected to the first source bottom metal layer 11a through the through hole 43.
[0031] The drain top metal layer 22 is arranged along the vertical direction of the first drain bottom metal layer 21a, and an insulating film 41 and a through hole 42 are arranged on the surface of the drain bottom metal layer 21. The drain bottom metal layer 21 is electrically connected to the drain top metal layer 22 through the through hole 42. The drain top metal layer 22 is located above the first source bottom metal layer 11a and the first drain bottom metal layer 21a, and its two ends are respectively located at the source connection metal region 101 and the drain connection metal region 102.
[0032] The second drain bottom metal layer 21b is located below the first drain bottom metal layer 21a and is arranged parallel to the second drain bottom metal layer 21a. A through hole 43 is arranged on the surface of the second drain bottom metal layer 21b, and the second drain bottom metal layer 21b is connected to the first drain bottom metal layer 21a through the through hole 43. The second drain bottom metal layer 21b and the second source bottom metal layer 11b are arranged at intervals.
[0033] The source top metal layer 12 and the drain top metal layer 22 are spaced apart from each other so as to be insulated from each other.
[0034] Combination Figure 2 and Figure 3c As shown, the bottom chip 100c is provided with a first source bottom metal layer 11c, a second source bottom metal layer 11d, a first drain bottom metal layer 21c and a second drain bottom metal layer 21d.
[0035] In this embodiment, the source top metal layer 12 is arranged along the vertical direction of the first source bottom metal layer 11c, and the surface of the first source bottom metal layer 11c is provided with an insulating film 41 and a through hole 42, and the first source bottom metal layer 11c is electrically connected to the source top metal layer 12 through the through hole 42. The source top metal layer 12 is located above the first source bottom metal layer 11c and the first drain bottom metal layer 21c, and its two ends are respectively located at the source connection metal region 101 and the drain connection metal region 102.
[0036] The second source bottom metal layer 11d is located below the first source bottom metal layer 11c and is vertically arranged with the first source bottom metal layer 11c. A through hole 43 is arranged on the surface of the second source bottom metal layer 11d. The second source bottom metal layer 11d is connected to the first source bottom metal layer 11c through the through hole 43.
[0037] The drain top metal layer 22 is arranged along the vertical direction of the first drain bottom metal layer 21c, and an insulating film 41 and a through hole 42 are arranged on the surface of the drain bottom metal layer 21, and the first drain bottom metal layer 21c is electrically connected to the drain top metal layer 22 through the through hole 42. The drain top metal layer 22 is located above the first source bottom metal layer 11c and the first drain bottom metal layer 21c, and its two ends are respectively located at the source connection metal region 101 and the drain connection metal region 102.
[0038] The second drain bottom metal layer 21d is located below the first drain bottom metal layer 21c and is arranged vertically with the second drain bottom metal layer 21c. A through hole 43 is arranged on the surface of the second drain bottom metal layer 21d, and the second drain bottom metal layer 21d is connected to the first drain bottom metal layer 21c through the through hole 43. The second drain bottom metal layer 21d and the second source bottom metal layer 11d are arranged at intervals.
[0039] The source top metal layer 12 and the drain top metal layer 22 are spaced apart from each other so as to be insulated from each other.
[0040] The insulating layer 3 covers the source top metal layer 12 and the drain top metal layer 22. The insulating layer 3 is provided with a source window 31 and a drain window 32. The source window 31 is located in the source connection metal region 101 and is provided corresponding to the source top metal layer 12. The source top metal layer 12 is connected to the top chip 200 through the source window 31. The drain window 32 is located in the drain connection metal region 102 and is provided corresponding to the drain top metal layer 22. The drain top metal layer 22 is connected to the packaging structure through the drain window 32.
[0041] Through the source opening 31 located in the source connection metal area 101, the source top metal layer 12 located at the source opening 31 is exposed, and the source opening 31 forms a conductive gas connection channel between the source top metal layer 12 and the top chip 200, thereby realizing electrical connection between the upper and lower chips. Through the drain opening 32 located in the drain connection metal area 102, the drain top metal layer 22 located at the drain opening 32 is exposed, and the drain opening 32 forms a conductive gas connection channel between the drain top metal layer 22 and the packaging structure, thereby realizing electrical connection between the bottom chip 100 and the packaging structure.
[0042] One end of the drain top metal layer 22 is located at the source connection metal area 101, so that the drain top metal layer 22 can extend to the bottom of the top chip 200, increasing the area of the drain top metal layer 22 and reducing the resistance. The drain top metal layer 22 can remain insulated from the top chip 200 through the insulating layer 3, so as not to be electrically connected to the top chip 200.
[0043] The utility model can effectively reduce the source and drain metal series resistance and the chip unit area resistance by arranging the source top metal layer 12 and the drain top metal layer 22, thereby reducing the cost.
[0044] In the present embodiment, the source bottom metal layer 11, the drain bottom metal layer 21, the source top metal layer 12, and the drain top metal layer 22 are all multiple, so as to reduce the resistance of each source bottom metal layer 11 and each drain bottom metal layer 21 at the corresponding circuit. Multiple source bottom metal layers 11 and multiple drain bottom metal layers 21 are arranged alternately, and correspondingly, multiple source top metal layers 12 and multiple drain top metal layers 22 are arranged alternately. One end of the drain top metal layer 22 located at the outermost edge may be located at one side of the source connection metal area 101 in the horizontal direction, or may be located at the source connection metal area 101. That is, the top chip 200 may not cover the drain top metal layer 22 at the outermost edge, such as Figure 1 It can also cover the drain top metal layer 22 at the edge, as shown in Figure 4 shown.
[0045] like Figure 2 As shown, the lengths and widths of the multiple source top metal layers 12 and the multiple drain top metal layers 22 are equal, so that the resistance at each position is roughly the same and the current distribution is uniform, which is beneficial to further reduce the resistance of the overall device and facilitate the layout and processing of the source top metal layer 12 and the drain top metal layer 22.
[0046] Furthermore, each source top metal layer 12 corresponds to one source window 31, which is located in the length direction of the source top metal layer 12. Figure 2In the longitudinal direction, the size of the source window 31 is equal to or larger than the size of the source connection metal area 101, so that the size of the source window 31 is larger than the size of the top chip 200, thereby increasing the contact area between the top chip 200 and the source top metal layer 12, facilitating the installation of the top chip 200.
[0047] In the width direction of the source top metal layer 12, that is, Figure 2 In the horizontal direction, the size of the source window 31 is smaller than the width of the source top metal layer 12, so that the insulating layer 3 can more reliably insulate the drain top metal layer 22 from the top chip 200, avoiding electrical connection between the drain top metal layer 22 and the top chip 200.
[0048] In this embodiment, the bottom chip 200 is a high-voltage D-mode wide bandgap HEMT device, and the top chip 100 is a low-voltage SiMOSFET device. Of course, in other feasible implementations, the layout structure of the source top metal layer and the drain top metal layer provided by the utility model can also be applied to other structures of two or more chip stacks. The lower layer and the top chip 200 in the stacked core structure are not limited to semiconductor materials such as GaN, Si, Si C, GaAs, and diamond, because these types of semiconductor chips will have a bottom metal layer. The technical solution of the utility model can be applied to these stacked core structure designs to reduce the overall device resistance and reduce costs.
[0049] like Figure 5 As shown, in the semiconductor power device stacked core structure provided in the second embodiment of the utility model, it is a further improvement on the basis of the first embodiment. Specifically, an end metal layer 13 is connected between two adjacent source top metal layers 12, and the end metal layer 13 can be arranged adjacent to the source window 31. Through the end metal layer 13, multiple source top metal layers 12 can be connected as a whole, which can achieve a smaller metal series resistance and reduce the chip unit area resistance. The end metal layer 13 is arranged adjacent to the source window 31, and will not occupy the space at the drain connection metal area 102, ensuring the effective size setting of the drain top metal layer 22.
[0050] In this embodiment, the end metal layer 13 is located at the end of the source top metal layer 12 to facilitate processing and forming, and the end metal layer 13 is located outside the source connection metal area 101 and away from the drain connection metal area 102, and does not occupy the space under the top chip 200, so that there is more space under the top chip 200 to set the drain top metal layer 22. Here, in other embodiments, the end metal layer 13 can also be partially or completely located in the source connection metal area 101.
[0051] Similarly, the end metal layer may also be disposed between the ends of the drain top metal layer, and the end metal layer is located outside the drain connection metal region and on a side away from the source connection metal region.
[0052] like Figure 6 As shown, in the semiconductor power device stacked core structure provided in the third embodiment of the utility model, it is a further improvement on the basis of the second embodiment. Specifically, a middle metal layer 14 is connected between two adjacent source top metal layers 12, and the middle metal layer 14 is located in the source connection metal area 101 and is spaced apart from the end metal layer 13. The drain top metal layer 22 located between the two adjacent source top metal layers 12 includes a first section metal layer 221 and a second section metal layer 222, and the first section metal layer 221 and the second section metal layer 222 are arranged in the vertical direction of the topmost drain bottom metal layer 21, and the first section metal layer 221 is located between the end metal layer 13 and the middle metal layer 14, and one end of the second section metal layer 222 is located in the drain connection metal area 102, and the other end extends to the source connection metal area 101. The drain opening 32 is arranged on the second metal layer 222.
[0053] The middle metal layer 14 can be used to enhance the connection between the source top metal layer 12 to further reduce the resistance. The drain top metal layer 22 can be divided into two sections, so that the source connection metal area 101, that is, the setting area of the top chip 200, still has part of the drain top metal layer 22, and the first section of the metal layer 221 located in the source connection metal area 101 can still play a role in reducing the series resistance, making the structural layout design of the source top metal layer 12 and the drain top metal layer 22 more flexible, so as to make full use of the space and achieve the purpose of reducing resistance. The user can further split the drain top metal layer into multiple metal layers through the middle metal layer as needed.
[0054] A window may also be provided at the insulating layer 3 corresponding to the middle metal layer 14 to expose a portion of the surface of the middle metal layer 14 so that the middle metal layer 14 can also be connected to the top chip 200 .
[0055] When the end metal layer 13 is partially or completely located in the source connection metal area 101 , the insulating layer 3 may also be provided with a window at the end metal layer 13 corresponding to the source connection metal area 101 , so that the end metal layer 13 may also be electrically connected to the top chip 200 .
[0056] like Figure 7As shown, in the semiconductor power device stacked core structure provided in the fourth embodiment of the utility model, it is a further improvement on the basis of the first embodiment. In the first embodiment, each source top metal layer 12 corresponds to one source window 31, and in the length direction of the source bottom metal layer 11, the size of the source window 31 is equivalent to the size of the source connection metal area 101. In this fourth embodiment, each source top metal layer 12 corresponds to a plurality of source windows 31. The plurality of drain windows 32 are all square and can be arranged in an array for easy processing and preparation. Of course, the shape of the drain window can also be a triangle, a circle or other shapes, or arranged in other forms. Since the plurality of drain windows 32 are still located at the position of the original single drain window 32, the size of each drain window 32 is small, which can reduce the impact on the structure of the insulating layer 3 and ensure the stability of the insulating layer 3 structure. The structure of providing a plurality of source windows 31 at each source top metal layer 12 can also be applied to the aforementioned second and third embodiments.
[0057] like Figure 8 As shown, in the semiconductor power device stacked core structure provided in the fifth embodiment of the utility model, it is a further improvement on the basis of the first embodiment. In this embodiment, a stacked core metal layer 15 is also provided on the bottom chip 100, and the stacked core metal layer 15 is located above the insulating layer 3, and is electrically connected to at least two source top metal layers 12 through the source window 31. Preferably, there is one stacked core metal layer 15, which is electrically connected to all source top metal layers 12. The stacked core metal layer 15 can provide a smoother surface for adhesion to the top chip 200, thereby improving the adhesion effect, so that the stability of the top chip 200 after pasting is increased, and the top chip 200 and the bottom chip 100 are prevented from being delaminated or the top chip 200 falling off after long-term use. In addition, the stacked core metal layer 15 is used to reduce the contact resistance between the top metal layer 12 and the source, so that the resistance of the overall structure is lower.
[0058] In this embodiment, there is one stacked metal layer 15, which is electrically connected to all source top metal layers for easy assembly and connection; of course, in other embodiments, there can be multiple stacked metal layers 15, which are laid flat on the upper surface of the insulating layer 3, and each stacked metal layer 15 is electrically connected to several source top metal layers 12.
[0059] The material of the laminated metal layer 15 includes, but is not limited to, metal materials such as Ti, Ni, Cu, Ag, Au, or a combination of compounds and multilayer materials thereof, and the material can achieve electrical conduction.
[0060] The structure of the stacked metal layer 15 in this embodiment can be applied to any of the above embodiments.
[0061] In the utility model, multiple source top metal layers and multiple drain top metal layers are all strip-shaped and extend in the longitudinal direction, and the two are arranged alternately and spaced in the transverse direction; an insulating layer is arranged above the source top metal layer and the drain top metal layer, and a source window and a drain window are arranged on the insulating layer, corresponding to the source top metal layer and the drain top metal layer respectively, and the source top metal layer and the drain top metal layer at the window portion are conductive and can be used for electrical conduction with a top chip or a packaging structure; by arranging multiple source top metal layers, a partial area of each source top metal layer is located in the source connection metal area, that is, the source top metal layer and the source connection metal area overlap, and a source window is arranged at the overlap, and the source window is used as a conductive channel during packaging to realize the electrical connection between the bottom chip and the drain of the top chip; and a part of the drain top metal layer extends to the source connection metal area so that it can be located below the top chip, and there is no window at the drain top metal layer of this part, so it is not electrically connected to the top chip. The top chip can cover all the source top metal layer and the drain top metal layer, or only cover part of them. The utility model realizes the characteristic of reducing the resistance of the metal interconnect structure through the arrangement of the source top metal layer and the drain top metal layer and the connection with the top chip, thereby reducing the overall resistance of the device.
[0062] In summary, although the present invention has been disclosed as above in terms of preferred embodiments, the above preferred embodiments are not intended to limit the present invention. A person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be based on the scope defined in the claims.
Claims
1. A bottom chip used in a semiconductor power device stacked core structure, characterized in that: The upper surface of the bottom chip is provided with a source connection metal area for connecting to the top chip and a drain connection metal area for connecting to the packaging structure; the bottom chip is provided with a source bottom metal layer, a drain bottom metal layer, a source top metal layer, a drain top metal layer and an insulating layer; The source top metal layer is located above the source bottom metal layer and is electrically connected to the source bottom metal layer; Its two ends are respectively located at the source connection metal region and the drain connection metal region; the drain top metal layer is located above the drain bottom metal layer and is electrically connected to the drain bottom metal layer; Its two ends are respectively located at the source connection metal region and the drain connection metal region; The insulating layer covers the source top metal layer and the drain top metal layer, a source window and a drain window are arranged on the insulating layer, the source window is located in the source connection metal area and is arranged corresponding to the source top metal layer, and the source top metal layer is connected to the top chip through the source window; The drain opening is located in the drain connection metal region and is arranged corresponding to the drain top metal layer. The drain top metal layer is connected to the packaging structure through the drain opening.
2. The bottom chip according to claim 1, characterized in that: The source bottom metal layer and the drain bottom metal layer are one or more layers, and the multiple bottom metal layers are perpendicular or parallel to each other; the source top metal layer is arranged in a direction perpendicular to the direction of the topmost source bottom metal layer, and the drain top metal layer is arranged in a direction perpendicular to the direction of the topmost drain bottom metal layer; Each of the top source bottom metal layers is connected to one or more source top metal layers, and each of the source top metal layers is also connected to one or more of the top source bottom metal layers, and the multiple top source bottom metal layers are arranged in a mesh shape; Each of the topmost drain bottom metal layers is connected to one or more drain top metal layers, and each of the drain top metal layers is also connected to one or more of the topmost drain bottom metal layers. Multiple topmost drain bottom metal layers and multiple drain top metal layers are arranged in a grid.
3. The bottom chip according to claim 2, characterized in that: An end metal layer is connected between the ends of two adjacent source top metal layers; the end metal layer is located outside the source connection metal region and on a side away from the drain connection metal region.
4. The bottom chip according to claim 2, characterized in that: An end metal layer is connected between the ends of two adjacent drain top metal layers; the end metal layer is located outside the drain connection metal region and on a side away from the source connection metal region.
5. The bottom chip according to claim 3, characterized in that: A middle metal layer is connected between two adjacent source top metal layers, the middle metal layer is located in the source connection metal area and is spaced apart from the end metal layer; the drain top metal layer located between two adjacent source top metal layers includes a first metal layer and a second metal layer, the first metal layer and the second metal layer are arranged in a vertical direction of the topmost drain bottom metal layer, the first metal layer is located between the end metal layer and the middle metal layer, one end of the second metal layer is located in the drain connection metal area, and the other end extends to the source connection metal area.
6. The bottom chip according to claim 4, characterized in that: A middle metal layer is connected between two adjacent source top metal layers, the middle metal layer is located in the source connection metal area and is spaced apart from the end metal layer; the drain top metal layer located between two adjacent source top metal layers includes a first metal layer and a second metal layer, the first metal layer and the second metal layer are arranged in a vertical direction of the topmost drain bottom metal layer, the first metal layer is located between the end metal layer and the middle metal layer, one end of the second metal layer is located in the drain connection metal area, and the other end extends to the source connection metal area.
7. The bottom chip according to claim 2, characterized in that: A stacked metal layer is also provided on the bottom chip. The stacked metal layer is located above the insulating layer and is electrically connected to at least two source top metal layers through the source opening.
8. The bottom chip according to claim 7, characterized in that: There is one stacked core metal layer, which is electrically connected to all source top metal layers.
9. The bottom chip according to any one of claims 1 to 8, characterized in that: Each of the source top metal layers corresponds to one source window; or each of the source top metal layers corresponds to multiple source windows.
10. The bottom chip according to any one of claims 1 to 8, characterized in that: In the length direction of the source top metal layer, the size of the source window is equal to or larger than the size of the source connection metal region.
11. A semiconductor power device stacked core structure, characterized in that: It comprises a top chip and a bottom chip as described in any one of claims 1 to 10; the top chip is arranged in the source connection metal area of the bottom chip, and the drain metal on the lower surface of the top chip is connected to the source top metal layer on the upper surface of the bottom chip.