Temperature sensor circuit based on scaling type analog-to-digital converter

Abstract

The utility model discloses a temperature sensor circuit based on a scaling type analog-to-digital converter, and belongs to the field of temperature sensor circuits. Comprising an analog front end used for generating a quantized reference voltage delta VBE of a positive temperature coefficient and a to-be-quantized voltage VBE of a negative temperature coefficient, and a scaling type analog-to-digital converter comprising an N-bit SAR ADC, an N-bit DAC, a second-order loop filter, a comparator and a combiner. The output end of the analog front end is connected with the input end of the N-bit SAR ADC and the first input end of the adder, the output end of the N-bit SAR ADC is connected with the first input end of the N-bit ADC and the first input end of the combiner, the output end of the N-bit ADC is connected with the second input end of the first adder after passing through the NOT gate, and the output end of the adder is connected with the input end of the second-order loop filter. The output end of the second-order loop filter is connected with the second input end of the N-bit ADC and the second input end of the combiner through the comparator, and the output end of the combiner is connected with an external digital rear end.

Description

Technical Field

[0001] The utility model relates to the field of temperature sensor circuits, in particular to a temperature sensor circuit based on a scaling analog-to-digital converter. Background Art

[0002] Temperature sensors have a long history of development. According to the integration level of temperature sensors, the development of temperature sensors has roughly gone through the following three stages: discrete, analog integrated, and intelligent temperature sensors (the latter two are collectively referred to as integrated temperature sensors). The temperature measurement range of integrated temperature sensors is generally limited to -55℃~150℃, but they are small in size, highly repeatable, highly accurate and low in cost, and are widely used in information, industrial, consumer and other fields.

[0003] With the continuous advancement of the Internet era and the continuous improvement of the degree of informatization, the research on complementary metal oxide semiconductor (CMOS) intelligent temperature sensors has become one of the hottest research topics today. The sensing unit in the CMOS temperature sensor generally uses a device with temperature-related physical properties as a temperature sensing device. At present, the widely used temperature sensing devices are mainly parasitic BJT, MOSFET, resistors and pure substrates based on the principle of heat diffusion in CMOS. Among them, the temperature sensor using BJT as the sensing unit mainly uses the negative temperature coefficient voltage V of BJT. BE With positive temperature coefficient voltage ΔV BE , realizing temperature sensing.

[0004] At present, most BJT-based intelligent temperature sensors use high-precision Δ-Σ ADC to complete the quantization process to obtain the final digital code output. SAR ADC has relatively lower power consumption and higher speed, but SAR ADC is rarely used. Because the input voltage range of the temperature sensor to the ADC is small, in order to obtain a higher resolution, the ADC bit number requirement is high. In addition, due to the large noise of SAR ADC, it is more complicated to design a high-precision SAR ADC. SAR ADC has high energy efficiency, but the resolution is limited to 12 bits without correction. Δ-Σ ADC can obtain very high resolution thanks to oversampling and noise shaping technology, but generally chooses to use high-order or multi-bit Δ-Σ modulator to achieve a high dynamic range, which will cause high power consumption due to the high oversampling rate and the use of multiple integrators. Utility Model Content

[0005] The purpose of the utility model is to provide a temperature sensor circuit based on a scaling analog-to-digital converter, which adopts a scaling analog-to-digital converter including an N-bit SAR ADC, an N-bit DAC, a second-order loop filter, a comparator, and a combiner, and optimally combines multiple ADC architectures to improve the performance of a single architecture to achieve high resolution and high energy efficiency.

[0006] In order to achieve the above purpose, the technical solution adopted by the utility model is as follows:

[0007] A temperature sensor circuit based on a scaling analog-to-digital converter includes a quantized reference voltage ΔV for generating a positive temperature coefficient BE The voltage to be quantized with a negative temperature coefficient V BE The analog front end and the scaling analog-to-digital converter including N-bit SAR ADC, N-bit DAC, second-order loop filter, comparator, and combiner;

[0008] The output end of the analog front end is respectively connected to the input end of the N-bit SAR ADC and the first input end of the adder, the output end of the N-bit SAR ADC is connected to the first input end of the N-bit ADC and the first input end of the combiner, the output end of the N-bit ADC is connected to the second input end of the first adder through a NOT gate, the output end of the adder is connected to the input end of the second-order loop filter, the output end of the second-order loop filter is connected to the second input end of the N-bit ADC and the second input end of the combiner through a comparator, and the output end of the combiner is connected to an external digital back end.

[0009] Preferably, the analog front end includes a PTAT current bias circuit and a Bipolar core circuit, and the output end of the PTAT current bias circuit is connected to the input end of the Bipolar core circuit.

[0010] Preferably, the PTAT current bias circuit includes a PMOS tube M1, a PMOS tube M2, a PNP transistor Q B1 、PNP transistor Q B2 , operational amplifier A, first resistor R bias , the second resistor R bias / m; the resistance ratio of the first resistor and the second resistor is m:1, where m is the transistor Q B2 and Q B1 Ratio of the number of tubes;

[0011] The source of PMOS tube M1 and M2 are connected to the power supply V DD The gates of M1 and M2 are connected and connected to the output of operational amplifier A. The drain of M1 is connected to the in-phase input of operational amplifier A and one end of the first resistor. The other end of the first resistor is connected to the PNP transistor Q. B1 The emitter of M2 and the drain of M2 are connected to the inverting input of op amp A and the PNP transistor Q B2 The emitter, Q B2 The base of Q is connected to one end of the second resistor, and the other end of the second resistor is connected to Q B1 The base of is connected and grounded, Q B1 The collector and Q B2The collector of is grounded;

[0012] The output end of the operational amplifier A serves as the output of the PTAT current bias circuit.

[0013] Preferably, the Bipolar core circuit includes a PMOS tube M3, a PMOS tube M4, a PNP transistor Q B3 、PNP transistor Q B4 ;

[0014] The source of PMOS tube M3 and the source of M4 are connected to the power supply V DD The gates of M3 and M4 are connected and connected to the output of operational amplifier A in the PTAT current bias circuit, and the drain of M3 is connected to the PNP transistor Q B3 The emitter of M4 is connected to the PNP transistor Q B4 The emitter, Q B3 The base and collector of Q B4 The base and collector of M3 are grounded; the drain voltage of M3 is used as the quantized reference voltage ΔV of the positive temperature coefficient BE , the difference between the drain voltages of M3 and M4 is used as the voltage V to be quantified of the negative temperature coefficient BE .

[0015] Preferably, the circuit of the scaling analog-to-digital converter includes an operational amplifier A1, digital-to-analog converters DAC1 and DAC2, inverters INV1 and INV2, a control logic module, a comparator, clocks CLK1.1, CLK1.2, CLK1.3, CLK1.4, CLK1.5, CLK1.6, CLK1.7, CLK1.8, CLK2.1, CLK2.2, CLK2.3, CLK2.4, CLK2.5, CLK2.6, CLK1D.1, CLK1D.2, CLK1D.3, CLK1D.4, CLK2D.1, CLK2D.2, CLK2D.3, CLK2D.4, CLK2D.5, CLK2D.6, RESET1, RESET2, RESET3, RESET4, SBP1, SBP2, CLKG, CLKNG, and a capacitor C G1 , C G2 , C S1 , C S2 , C S3 , C S4 , C INT1 , C INT2 , C INT3 , C INT4 , C F1 , C F2 , C F3 , C F4 , C OS1 , COS2 ;

[0016] The non-inverting input of operational amplifier A1 is connected to capacitor C G1 , C S1 , digital-to-analog converter DAC1, one end of clock CLK1.3 and clock CLK2.3, capacitor C G1 The other end is connected to one end of the clock CLKG, and the capacitor C S1 The other end of the clock CLKG is connected to one end of the clock CLK1.1 and one end of the clock CLK2.1. The other end of the clock CLK2.1 is grounded. The other end of the clock CLKG, the other end of the digital-to-analog converter DAC1 and the other end of the clock CLK1.1 are connected to the output end of the analog front end. The other end of the clock CLK2.3 is connected to the clock RESET1 and the capacitor C INT1 One end of the op amp A1 output is connected to the capacitor C INT1 , the other end of clock RESET1 and clock CLK1.3 and one end of clock SBP1 and clock CLK2D.1, the other end of clock CLK2D.1 is connected to capacitor C F1 , capacitor C S3 and one end of the clock CLK1D.1, capacitor C S3 The other end is connected to capacitor C OS1 , one end of the clock CLK1.5 and the clock CLK2.5, the other end of the clock CLK1D.1 and the other end of the clock CLK2.5 are connected to the ground, and the capacitor C OS1 The other end of the clock CLK1.5 is connected to one end of the inverter INV1 and one end of the clock CLK2D.3, and the other end of the clock CLK1.5 is connected to the capacitor C INT3 One end of the clock RESET3, inverter INV1, clock CLK2D.3, capacitor C INT3 , the other end of the clock RESET3 is connected to one end of the clock CLK1D.3, and the other end of CLK1D.3 is connected to the capacitor C F3 One end of the capacitor C F3 The other end of the clock CLK2D.5 is connected to one end of the clock CLK1.7, and the other end of the clock CLK2D.5 is connected to the other end of the clock CLK1.7 and grounded;

[0017] The inverting input of operational amplifier A1 is connected to capacitor C G2 , C S2 , digital-to-analog converter DAC2, one end of clock CLK1.4 and clock CLK2.4, capacitor C G2 The other end is connected to one end of the clock CLKNG, and the capacitor C S2The other end of the clock CLK1.2 is connected to one end of the clock CLK2.2, and the other end of the clock CLK2.2 is grounded. The other end of the clock CLKNG, the other end of the digital-to-analog converter DAC2 and the other end of the clock CLK1.2 are connected to the output end of the analog front end. The other end of the clock CLK2.4 is connected to the clock RESET2 and the capacitor C INT2 One end of the operational amplifier A1 is connected to the capacitor C INT2 , the other end of clock RESET2 and clock CLK1.4 and one end of clock SBP2 and clock CLK2D.2, the other end of clock CLK2D.2 is connected to capacitor C F2 , capacitor C S4 and one end of the clock CLK1D.2, capacitor C S4 The other end is connected to capacitor C OS2 , one end of the clock CLK1.6 and the clock CLK2.6, the other end of the clock CLK1D.2 and the other end of the clock CLK2.6 are connected to the ground, and the capacitor C OS2 The other end of the clock CLK1.6 is connected to one end of the inverter INV2 and one end of the clock CLK2D.4, and the other end of the clock CLK1.6 is connected to the capacitor C INT4 One end of the clock RESET4, inverter INV2, clock CLK2D.4, capacitor C INT4 , the other end of the clock RESET4 is connected to one end of the clock CLK1D.4, and the other end of CLK1D.4 is connected to the capacitor C F4 One end of the capacitor C F4 The other end of the clock CLK2D.6 is connected to one end of the clock CLK1.8, and the other end of the clock CLK2D.6 is connected to the other end of the clock CLK1.8 and grounded;

[0018] Capacitor C F1 The other end of the clock SBP2 is connected to the first input end of the quantizer, and the capacitor C F2 , C F3 , C F4 The other end of the clock SBP1 is connected to the second input end of the comparator. The output code value k of the comparator in the SAR cycle is input into the combiner. The output bit stream bs of the comparator in the Δ-Σ cycle is input into the control logic module. The control logic module controls the switch device corresponding to each clock according to the clock signal and inputs it into the combiner. The combiner finally outputs the temperature quantization result V of the scaling analog-to-digital converter. BE / ΔV BE .

[0019] The beneficial effects of the utility model are as follows: the scaling analog-to-digital converter circuit adopted by the utility model greatly improves the conversion speed of the sensor by completing sampling and integration within one clock cycle, while reducing the gain requirement of the operational amplifier therein; by using the quantization error of the SAR ADC as the input of the second-order loop filter, the linearity and swing requirements of the integrator are greatly reduced, a smaller current can be used to drive the integrator in the loop filter, and the total power consumption is reduced; and because the gain requirement is reduced, an inverter-based operational amplifier is used, which further reduces the overall power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are merely embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without creative work.

[0021] Figure 1 It is a principle block diagram of a temperature sensor circuit based on a scaling analog-to-digital converter in an embodiment of the utility model;

[0022] Figure 2 It is a schematic diagram of the structure of the analog front-end circuit in the embodiment of the utility model;

[0023] Figure 3 Schematic diagram of the specific structure of a zoom analog-to-digital converter (ZOOM ADC) in an embodiment of the utility model;

[0024] Figure 4 The overall circuit structure diagram of the ZOOM ADC in the embodiment of the utility model;

[0025] Figure 5 Schematic diagram of sampling and integration in the ZOOM ADC fine conversion process in an embodiment of the present invention, (a) sampling stage, (b) integration stage;

[0026] Figure 6 Schematic diagram of signal waveforms of key nodes of ZOOM ADC in an embodiment of the present utility model. DETAILED DESCRIPTION

[0027] The following will be combined with the drawings in the embodiments of the utility model to clearly and completely describe the technical solutions in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, not all of them. Based on the embodiments of the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the protection scope of the utility model.

[0028] like Figure 1 As shown, the utility model discloses a temperature sensor circuit based on a scaling analog-to-digital converter, including a quantized reference voltage ΔV for generating a positive temperature coefficient BE The voltage to be quantized with a negative temperature coefficient V BE The analog front end includes an N-bit SAR ADC, an N-bit DAC, a second-order loop filter, a comparator, and a combiner.

[0029] The output end of the analog front end is respectively connected to the input end of the N-bit SAR ADC and the first input end of the adder, the output end of the N-bit SAR ADC is connected to the first input end of the N-bit ADC and the first input end of the combiner, the output end of the N-bit ADC is connected to the second input end of the first adder through a NOT gate, the output end of the adder is connected to the input end of the second-order loop filter, the output end of the second-order loop filter is connected to the second input end of the N-bit ADC and the second input end of the combiner through a comparator, and the output end of the combiner is connected to an external digital back end.

[0030] The analog front end mainly includes a PTAT current bias circuit and a Bipolar core circuit. The bias current generated by the PTAT current bias circuit has a PTAT characteristic and serves as a transistor bias current in the Bipolar core circuit. The Bipolar core circuit generates a positive temperature coefficient ΔV BE With negative temperature coefficient V BE The PTAT current bias circuit in the analog front end is connected to the Bipolar core circuit, and the output of the Bipolar core circuit is fed into the ZOOM ADC.

[0031] The ZOOM ADC mainly includes an N-bit SAR ADC and a second-order Δ-Σ ADC to simulate the ΔV input of the front end. BE As a quantitative reference voltage, V BE As the quantity to be quantized, the SAR logic is used to roughly quantize the corresponding integer code value, and then the input quantity V BE After subtracting the quantized integer part, it is input into the second-order Δ-Σ ADC for further fine quantization to obtain the quantization code value of the decimal part. Finally, the combination of the two code values ​​is the quantization result of the ADC.

[0032] The external digital backend can use existing equipment to digitally display the quantization results of the ZOOM ADC, which generally includes steps such as downsampling filters, digital signal processing, and correction, which are used to perform corresponding digital processing on the input quantization results to obtain the final digital code that corresponds one-to-one to the temperature.

[0033] Combination Figure 2The circuit structure of the PATA bias circuit is introduced in detail. The source of the PMOS tubes M1 and M2 is connected to the power supply V DD The gate is connected to the output of operational amplifier A, and the drain of M1 is connected to the non-inverting input of operational amplifier A and resistor R bias One end of the resistor R bias The other end is connected to the PNP transistor Q B1 The emitter of M2 and the drain of M2 are connected to the inverting input of operational amplifier A and the PNP transistor Q B2 The emitter, Q B2 The base is connected to the resistor R bias / m is one end, m is Q B2 and Q B1 The ratio of the number of tubes, resistance R bias / m and the other end of Q B1 The base of the B1 and Q B2 The collector of is also grounded.

[0034] Combination Figure 2 The circuit structure of the Bipolar core circuit is introduced in detail. The source of the PMOS tubes M3 and M4 is connected to the power supply V DD The gate is connected to the output of the PTAT current bias circuit, and the drain of M3 is connected to the PNP transistor Q B3 The emitter of M4 is connected to the PNP transistor Q B4 The emitter, Q B3 and Q B4 The base of is connected and grounded, Q B3 and Q B4 The collector of is connected to ground, Q B4 and Q B3 The ratio of the number of tubes is p, V BE1 and V BE2 are the drain voltages of M3 and M4, V BE1 and V BE2 -V BE1 As V BE and ΔV BE Output.

[0035] The PTAT current bias circuit includes two PNP transistors Q B1 and Q B2 The area of ​​the two tubes is the same, the ratio of the number of tubes is m, and the base of the two tubes is connected through the compensation resistor R bias / m connected, R bias The voltage difference between the two ends is clamped at ΔV by the virtual short effect of the operational amplifier. BE , thus generating ΔV BE / R bias The PTAT bias current.

[0036] Q B1 and Q B2 The emitter junction voltage can be expressed as:

[0037]

[0038] Wherein, the subscript bias represents the emitter junction voltage in the PTAT bias circuit;

[0039] Add the compensation resistor R bias / m, the emitter junction voltage ΔV BE,bias It can be written as:

[0040]

[0041] Due to the virtual short effect of the operational amplifier, V X =V Y , we can get:

[0042]

[0043] Therefore, the PTAT bias current generated by the bias circuit can be expressed as:

[0044]

[0045] Where, β is the current gain;

[0046] This bias current is used to bias the Bipolar core circuit. The emitter junction voltage ΔV in the Bipolar core circuit BE,core It can be expressed as:

[0047]

[0048] Finally, the unit bias current of the two BJTs in the Bipolar core circuit is independent of the current gain β and can be expressed as:

[0049]

[0050]

[0051]

[0052] Combination Figure 3 The specific structure of ZOOM ADC is introduced in detail. ZOOM ADC includes an N-bit SAR ADC and a second-order Δ-Σ ADC, which share an N-bit DAC. The V generated by the analog front end BE With ΔV BEThe quantity to be quantized and the quantization reference voltage are respectively input to the ZOOM ADC, and the SAR ADC performs coarse conversion. The output of the SAR ADC is connected to the input of the second-order Δ-Σ ADC, and the second-order Δ-Σ ADC performs fine conversion, and the conversion result is output to the external digital backend.

[0053] The quantization step size or the least significant bit (LSB) of the ZOOM ADC is ΔV BE , the code value k obtained by SAR ADC quantization is used to dynamically adjust the reference value of the fine DAC:

[0054]

[0055] Therefore, the input signal Vx to the second-order delta-sigma ADC can be expressed as:

[0056]

[0057] This shows that the smaller swing of V X The integrator used to realize the loop filter can be realized with a smaller current, so the total power consumption is smaller.

[0058] Finally, since the feedback loop forces the net integrated charge to be approximately zero, the bitstream average s can be expressed as:

[0059]

[0060] Therefore, by combining the quantization results of the SAR ADC and the second-order Δ-Σ ADC, the quantization result Y of the ZOOM ADC can be obtained:

[0061]

[0062] The digital output Y is processed by the digital backend and a correction algorithm is added to finally obtain a digital code value corresponding to the temperature, thus completing temperature sensing and transmission.

[0063] Figure 4The overall circuit architecture of ZOOM ADC is described in detail. The specific circuit architecture includes operational amplifier A1, digital-to-analog converters DAC1, DAC2, inverters INV1, INV2, clocks CLK1.1, CLK1.2, CLK1.3, CLK1.4, CLK1.5, CLK1.6, CLK1.7, CLK1.8, CLK2.1, CLK2.2, CLK2.3, CLK2.4, CLK2.5, CLK2.6, CLK1D.1, CLK1D.2, CLK1D.3, CLK1D.4, CLK2D.1, CLK2D.2, CLK2D.3, CLK2D.4, CLK2D.5, CLK2D.6, RESET1, RESET2, RESET3, RESET4, SBP1, SBP2, CLKG, CLKNG, comparator CLK_COM, capacitor C G1 , C G2 , C S1 , C S2 , C S3 , C S4 , C INT1 , C INT2 , C INT3 , C INT4 , C F1 , C F2 , C F3 , C F4 , C OS1 , C OS2 .

[0064] The non-inverting input of operational amplifier A1 is connected to capacitor C G1 , C S1 , digital-to-analog converter DAC1, one end of clock CLK1.3 and clock CLK2.3, capacitor C G1 The other end is connected to one end of the clock CLKG, and the capacitor C S1 The other end of the clock CLKG is connected to one end of the clock CLK1.1 and one end of the clock CLK2.1. The other end of the clock CLK2.1 is grounded. The other end of the clock CLKG, the other end of the digital-to-analog converter DAC1 and the other end of the clock CLK1.1 are connected and connected to the input V in The other end of the clock CLK2.3 is connected to the clock RESET1 and the capacitor C INT1 One end of the operational amplifier A1 output is connected to the capacitor C INT1 , the other end of clock RESET1 and clock CLK1.3 and one end of clock SBP1 and clock CLK2D.1, the other end of clock CLK2D.1 is connected to capacitor C F1 , capacitor C S3 and one end of the clock CLK1D.1, capacitor C S3 The other end is connected to capacitor COS1 , one end of the clock CLK1.5 and the clock CLK2.5, the other end of the clock CLK1D.1 and the other end of the clock CLK2.5 are connected to the ground, and the capacitor C OS1 The other end of the clock CLK1.5 is connected to one end of the inverter INV1 and one end of the clock CLK2D.3, and the other end of the clock CLK1.5 is connected to the capacitor C INT3 One end of the clock RESET3, inverter INV1, clock CLK2D.3, capacitor C INT3 , the other end of the clock RESET3 is connected to one end of the clock CLK1D.3, and the other end of CLK1D.3 is connected to the capacitor C F3 One end of the capacitor C F3 The other end of the clock CLK2D.5 is connected to one end of the clock CLK1.7, and the other end of the clock CLK2D.5 is connected to the other end of the clock CLK1.7 and grounded.

[0065] The inverting input of operational amplifier A1 is connected to capacitor C G2 , C S2 , digital-to-analog converter DAC2, one end of clock CLK1.4 and clock CLK2.4, capacitor C G2 The other end is connected to one end of the clock CLKNG, and the capacitor C S2 The other end of the clock CLKNG is connected to one end of the clock CLK1.2 and one end of the clock CLK2.2. The other end of the clock CLK2.2 is grounded. The other end of the clock CLKNG, the other end of the digital-to-analog converter DAC2 and the other end of the clock CLK1.2 are connected and connected to the input V in The other end of the clock CLK2.4 is connected to the clock RESET2 and the capacitor C INT2 One end of the operational amplifier A1 is connected to the capacitor C INT2 , the other end of clock RESET2 and clock CLK1.4 and one end of clock SBP2 and clock CLK2D.2, the other end of clock CLK2D.2 is connected to capacitor C F2 , capacitor C S4 and one end of the clock CLK1D.2, capacitor C S4 The other end is connected to capacitor C OS2 , one end of the clock CLK1.6 and the clock CLK2.6, the other end of the clock CLK1D.2 and the other end of the clock CLK2.6 are connected to the ground, and the capacitor C OS2 The other end of the clock CLK1.6 is connected to one end of the inverter INV2 and one end of the clock CLK2D.4, and the other end of the clock CLK1.6 is connected to the capacitor C INT4 One end of the clock RESET4, inverter INV2, clock CLK2D.4, capacitor C INT4, the other end of the clock RESET4 is connected to one end of the clock CLK1D.4, and the other end of CLK1D.4 is connected to the capacitor C F4 One end of the capacitor C F4 The other end of is connected to one end of the clock CLK1.8, and the other end of the clock CLK2D.6 is connected to the other end of the clock CLK1.8 and grounded.

[0066] Capacitor C F1 The other end of the capacitor C is connected to the other end of the clock SBP2 and connected to the first input end of the comparator. F2 , C F3 , C F4 The other end is connected to the second input end of the comparator, and the output code value k of the comparator in the SAR cycle is input into the combiner. The output bit stream bs of the comparator in the Δ-Σ cycle is input into the control logic module. The control logic module controls the switch device corresponding to each clock according to the clock signal and inputs it into the combiner. The combiner finally outputs the quantization result V of the ZOOM ADC BE / ΔV BE .

[0067] Figure 5 The process of charge change on the capacitor during fine conversion is described in detail. During fine conversion, when the output of the comparator is 0 or 1, V X Integrate the proportional charge (V BE -zΔV BE ) is integrated, where z is equal to k or k+1 depending on the polarity of bs. BE and ΔV BE They are sampled at the same time and integrated within the same period.

[0068] During the sampling phase (CLK1), -ΔV BE Sampled to zC S Up, V BE is sampled to C S Therefore, the charge accumulated on the capacitor during the sampling phase is:

[0069] Q s =C S V BE -zC S ΔV BE

[0070] Then in the integration phase (CLK2), the input polarity is reversed, ΔV BE Sampled to zC S Up, -V BE is sampled to C STherefore, the charge accumulated on the capacitor during the integration phase is:

[0071] Q iNT =-C S V BE +zC S ΔV BE

[0072] Therefore, after the sampling and integration phases, the total change in charge on the sampling capacitor is:

[0073] ΔQ=Q S -Q INT =2(V BE -zΔV BE )C S

[0074] Due to the law of charge conservation, an equal amount of charge accumulates on the integrating capacitor, and the final output voltage becomes:

[0075]

[0076] Among them, C INT =2C S .

[0077] Figure 6 for Figure 4 The corresponding timing diagram. CLK1 and CLK2 are non-overlapping clocks to avoid simultaneous conduction and integrator reset. SBP is the control clock for switching between SAR cycle and Δ-Σ cycle, RESET is the integrator reset signal, and CLK_COM is the comparator comparison enable signal. During the coarse conversion step, the second integrator is shorted by switch SBP, thereby connecting the output of the first integrator directly to the comparator. In addition, at the beginning of each comparison step, the first integrator is reset, so it plays the role of sampling and holding.

[0078] The working sequence flow of the temperature sensor circuit based on the scaling analog-to-digital converter includes the following steps:

[0079] (1) The PTAT current bias circuit generates a bias current with PTAT characteristics, which is copied to the Bipolar core circuit as the bias current of the transistor. The Bipolar core circuit generates a positive temperature coefficient ΔV BE With negative temperature coefficient V BE ;

[0080] (2) Scaling ADC with ΔV BE As a quantitative reference voltage, V BE As the quantity to be quantified, the quantity to be quantified V BEThe corresponding integer code value k is obtained by coarse quantization through the N-bit SAR ADC, and then the reference value of the fine DAC is dynamically adjusted using the N-bit DAC. BE After deducting the quantized integer part code value, the code value is input into the second-order loop filter for further fine quantization to obtain the decimal part quantization code value, which is combined as the quantization result of the scaling analog-to-digital converter;

[0081] (3) The quantization result is input to an external digital backend for digital processing to obtain a final digital code corresponding to the temperature.

[0082] The specific embodiments described above further illustrate the purpose, technical solutions and beneficial effects of the utility model. It should be noted that the above are only specific embodiments of the utility model and are not intended to limit the utility model. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the utility model should be included in the protection scope of the utility model.

Claims

1. A temperature sensor circuit based on a scaling analog-to-digital converter, characterized in that: Includes a quantized reference voltage ΔV for generating a positive temperature coefficient BE The voltage to be quantized with a negative temperature coefficient V BE The analog front end and the scaling analog-to-digital converter including N-bit SARADC, N-bit DAC, second-order loop filter, comparator, and combiner; The output end of the analog front end is respectively connected to the input end of the N-bit SAR ADC and the first input end of the adder, the output end of the N-bit SAR ADC is connected to the first input end of the N-bit ADC and the first input end of the combiner, the output end of the N-bit ADC is connected to the second input end of the first adder through a NOT gate, the output end of the adder is connected to the input end of the second-order loop filter, the output end of the second-order loop filter is connected to the second input end of the N-bit ADC and the second input end of the combiner through a comparator, and the output end of the combiner is connected to an external digital back end.

2. The temperature sensor circuit based on a scaling analog-to-digital converter according to claim 1, characterized in that: The analog front end comprises a PTAT current bias circuit and a Bipolar core circuit, and the output end of the PTAT current bias circuit is connected to the input end of the Bipolar core circuit.

3. The temperature sensor circuit based on a scaling analog-to-digital converter according to claim 2, characterized in that: The PTAT current bias circuit includes a PMOS tube M1, a PMOS tube M2, a PNP transistor Q B1 、PNP transistor Q B2 , operational amplifier A, first resistor R bias , the second resistor R bias / m; the resistance ratio of the first resistor and the second resistor is m:1, where m is the transistor Q B2 and Q B1 Ratio of the number of tubes; The source of PMOS tube M1 and M2 are connected to the power supply V DD The gates of M1 and M2 are connected and connected to the output of operational amplifier A. The drain of M1 is connected to the in-phase input of operational amplifier A and one end of the first resistor. The other end of the first resistor is connected to the PNP transistor Q. B1 The emitter of M2 and the drain of M2 are connected to the inverting input of op amp A and the PNP transistor Q B2 The emitter, Q B2 The base of Q is connected to one end of the second resistor, and the other end of the second resistor is connected to Q B1 The base of is connected and grounded, Q B1 The collector and Q B2 The collector of is grounded; The output end of the operational amplifier A serves as the output of the PTAT current bias circuit.

4. The temperature sensor circuit based on a scaling analog-to-digital converter according to claim 2, characterized in that: The Bipolar core circuit includes a PMOS tube M3, a PMOS tube M4, a PNP transistor Q B3 、PNP transistor Q B4 ; The source of PMOS tube M3 and the source of M4 are connected to the power supply V DD The gates of M3 and M4 are connected and connected to the output of operational amplifier A in the PTAT current bias circuit, and the drain of M3 is connected to the PNP transistor Q B3 The emitter of M4 is connected to the PNP transistor Q B4 The emitter, Q B3 The base and collector of Q B4 The base and collector of M3 are grounded; the drain voltage of M3 is used as the quantized reference voltage ΔV of the positive temperature coefficient BE , the difference between the drain voltages of M3 and M4 is used as the voltage V to be quantified of the negative temperature coefficient BE .

5. The temperature sensor circuit based on a scaling analog-to-digital converter according to claim 1, characterized in that: The circuit of the zoomable analog-to-digital converter includes an operational amplifier A1, digital-to-analog converters DAC1 and DAC2, inverters INV1 and INV2, a control logic module, a comparator, clocks CLK1.1, CLK1.2, CLK1.3, CLK1.4, CLK1.5, CLK1.6, CLK1.7, CLK1.8, CLK2.1, CLK2.2, CLK2.3, CLK2.4, CLK2.5, CLK2.6, CLK1D.1, CLK1D.2, CLK1D.3, CLK1D.4, CLK2D.1, CLK2D.2, CLK2D.3, CLK2D.4, CLK2D.5, CLK2D.6, RESET1, RESET2, RESET3, RESET4, SBP1, SBP2, CLKG, CLKNG, and a capacitor C G1 , C G2 , C S1 , C S2 , C S3 , C S4 , C INT1 , C INT2 , C INT3 , C INT4 , C F1 , C F2 , C F3 , C F4 , C OS1 , C OS2 ; The non-inverting input of operational amplifier A1 is connected to capacitor C G1 , C S1 , digital-to-analog converter DAC1, one end of clock CLK1.3 and clock CLK2.3, capacitor C G1 The other end is connected to one end of the clock CLKG, and the capacitor C S1 The other end of the clock CLKG is connected to one end of the clock CLK1.1 and one end of the clock CLK2.

1. The other end of the clock CLK2.1 is grounded. The other end of the clock CLKG, the other end of the digital-to-analog converter DAC1 and the other end of the clock CLK1.1 are connected to the output end of the analog front end. The other end of the clock CLK2.3 is connected to the clock RESET1 and the capacitor C INT1 One end of the op amp A1 output is connected to the capacitor C INT1 , the other end of clock RESET1 and clock CLK1.3 and one end of clock SBP1 and clock CLK2D.1, the other end of clock CLK2D.1 is connected to capacitor C F1 , capacitor C S3 and one end of the clock CLK1D.1, capacitor C S3 The other end is connected to capacitor C OS1 , one end of the clock CLK1.5 and the clock CLK2.5, the other end of the clock CLK1D.1 and the other end of the clock CLK2.5 are connected to the ground, and the capacitor C OS1 The other end of the clock CLK1.5 is connected to one end of the inverter INV1 and one end of the clock CLK2D.3, and the other end of the clock CLK1.5 is connected to the capacitor C INT3 One end of the clock RESET3, inverter INV1, clock CLK2D.3, capacitor C INT3 , the other end of the clock RESET3 is connected to one end of the clock CLK1D.3, and the other end of CLK1D.3 is connected to the capacitor C F3 One end of the capacitor C F3 The other end of the clock CLK2D.5 is connected to one end of the clock CLK1.7, and the other end of the clock CLK2D.5 is connected to the other end of the clock CLK1.7 and grounded; The inverting input of operational amplifier A1 is connected to capacitor C G2 , C S2 , digital-to-analog converter DAC2, one end of clock CLK1.4 and clock CLK2.4, capacitor C G2 The other end is connected to one end of the clock CLKNG, and the capacitor C S2 The other end of the clock CLK1.2 is connected to one end of the clock CLK2.2, and the other end of the clock CLK2.2 is grounded. The other end of the clock CLKNG, the other end of the digital-to-analog converter DAC2 and the other end of the clock CLK1.2 are connected to the output end of the analog front end. The other end of the clock CLK2.4 is connected to the clock RESET2 and the capacitor C INT2 One end of the operational amplifier A1 is connected to the capacitor C INT2 , the other end of clock RESET2 and clock CLK1.4 and one end of clock SBP2 and clock CLK2D.2, the other end of clock CLK2D.2 is connected to capacitor C F2 , capacitor C S4 and one end of the clock CLK1D.2, capacitor C S4 The other end is connected to capacitor C OS2 , one end of the clock CLK1.6 and the clock CLK2.6, the other end of the clock CLK1D.2 and the other end of the clock CLK2.6 are connected to the ground, and the capacitor C OS2 The other end of the clock CLK1.6 is connected to one end of the inverter INV2 and one end of the clock CLK2D.4, and the other end of the clock CLK1.6 is connected to the capacitor C INT4 One end of the clock RESET4, inverter INV2, clock CLK2D.4, capacitor C INT4 , the other end of the clock RESET4 is connected to one end of the clock CLK1D.4, and the other end of CLK1D.4 is connected to the capacitor C F4 One end of the capacitor C F4 The other end of the clock CLK2D.6 is connected to one end of the clock CLK1.8, and the other end of the clock CLK2D.6 is connected to the other end of the clock CLK1.8 and grounded; Capacitor C F1 The other end of the clock SBP2 is connected to the first input end of the quantizer, and the capacitor C F2 , C F3 , C F4 The other end of the clock SBP1 is connected to the second input end of the comparator. The output code value k of the comparator in the SAR cycle is input into the combiner. The output bit stream bs of the comparator in the Δ-Σ cycle is input into the control logic module. The control logic module controls the switch device corresponding to each clock according to the clock signal and inputs it into the combiner. The combiner finally outputs the temperature quantization result V of the scaling analog-to-digital converter. BE / ΔV BE .

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