Video zooming device
By using two processing chips in the video scaling device to process timing control and scaling superposition, the processing of multi-pixel data stream is achieved, which solves the problem of insufficient FPGA clock frequency, improves the video data processing speed and reduces the clock frequency requirement. Efficient processing of high-definition videos.
Patent Information
- Application Number
- CN202323429573.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-15
- Publication Date
- 2024-12-17
- Estimated Expiration
- 2033-12-15
AI Technical Summary
The clock frequency of existing FPGAs cannot meet the video reduction needs, especially when the reduction ratio is large, it is difficult to achieve efficient video scaling processing.
Two processing chips are used to undertake timing control and scaling and superimposing processing respectively, and the multi-pixel data stream is processed through high-speed serial link communication connection to reduce the need for clock frequency.
It improves the video data processing speed, can cope with the large data stream of high-definition video, reduces the clock frequency requirements, has reliable design principles, simple structure, and has a wide range of application prospects.
Smart Images
Figure CN222192453U_ABST
Abstract
Description
Technical Field
[0001] The utility model belongs to the technical field of video processing, and in particular relates to a video zooming device. Background Art
[0002] Video scaling refers to zooming in or out the video for display. The specific process includes the input video first entering the DDR for caching, and then the Video Fetch module obtains the original video data from the DDR and sends it to the Video Scaler module for scaling. The scaled video enters the Video Mixer module for superposition, and the superimposed video is finally output through the Video Display module.
[0003] Video scaling is usually handled by an FPGA, whose hardware architecture is as follows Figure 1 As shown. The input pin of FPGA receives a single pixel, and stores pixel P1 in the first cycle and pixel P2 in the second cycle in the corresponding row cache in accordance with the beat of storing a single pixel in a single clock cycle. After storing enough data in the row cache according to the actual configured scaling source / destination size, the scaling algorithm module reads the data in the row cache in parallel to perform scaling operations and then outputs a single pixel data stream, thereby realizing the image scaling function.
[0004] In the application scenario of image scaling and overlay, the reduction and overlay require a higher operating frequency of the input interface of the scaling module. When the scaling ratio is 2:1, the input interface clock frequency of the scaling module is required to operate at 248MHz. When the reduction ratio is larger, a higher clock frequency is required. However, it is difficult for common FPGAs on the market to meet the clock frequency of 248MHz and above. Utility Model Content
[0005] In view of the above-mentioned deficiencies in the prior art, the utility model provides a video scaling device to solve the technical problem that the clock frequency of the existing FPGA cannot meet the video reduction requirement.
[0006] In a first aspect, the utility model provides a video zooming device, comprising:
[0007] A first processing chip, a dual-port memory, and a second processing chip, wherein a plurality of input pins of the first processing chip are connected to a processor for processing video data to obtain a plurality of pixel data; the first processing chip includes a write data pin, and the write data pin is connected to one port of the dual-port memory; the second processing chip includes a read data pin, and a read data pin of the second processing chip is connected to another port of the dual-port memory;
[0008] A timing control program is stored in the register of the first processing chip; a zooming and overlaying processing program is stored in the register of the second processing chip; and an output pin of the second processing chip is connected to a display.
[0009] In an optional embodiment, the first processing chip and the second processing chip are both complex programmable logic devices, which include computing modules, registers, and core crystal oscillators; the write data pins of the first processing chip are multiple IO pins of the first processing chip.
[0010] In a second aspect, the utility model provides a video zooming device, comprising:
[0011] a first processing chip, a dual-port memory, and a second processing chip, wherein a plurality of input pins of the first processing chip and the second processing chip are connected to a processor for processing video data to obtain a plurality of pixel data; the first processing chip includes a data read / write port, the data read / write port is connected to one port of the dual-port memory; the second processing chip includes a data read / write port, the data read / write port is connected to another port of the dual-port memory;
[0012] The registers of the first processing chip and the second processing chip both store a timing control program and a zooming and overlaying processing program; the output pins of the first processing chip and the second processing chip are both connected to a display;
[0013] The first processing chip and the second processing chip are communicatively connected via a high-speed serial link.
[0014] In an optional implementation, the first processing chip and the second processing chip are both complex programmable logic devices, and the complex programmable logic devices include a computing module, a register, and a core crystal oscillator.
[0015] The beneficial effect of the present invention lies in that the video scaling device provided by the present invention can improve the video data processing speed to cope with the large data stream of high-definition video by selecting two processing chips to respectively undertake timing control and scaling overlay processing. In addition, multiple IO pins of the processing chip that undertakes timing control are connected to the video data processor, so that the processing chip can simultaneously obtain multiple pixel data streams, and periodically cache the multiple pixel data streams based on the timing control program, which can reduce the demand for clock frequency.
[0016] In addition, the utility model has a reliable design principle, a simple structure and a very broad application prospect. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] In order to more clearly illustrate the embodiments of the utility model or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0018] Figure 1 It is a schematic diagram of the architecture of a conventional video scaling device.
[0019] Figure 2 It is a schematic diagram of the architecture of a video scaling device according to an embodiment of the utility model.
[0020] Figure 3 2 is another schematic diagram of the structure of the video zooming device according to an embodiment of the present invention. DETAILED DESCRIPTION
[0021] In order to enable those skilled in the art to better understand the technical solutions in the present invention, the following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.
[0022] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention.
[0023] The key terms appearing in the present invention are explained below.
[0024] The timing control program stores a pixel input stream into the scaling module and stores the pixel P1 in the first cycle and the pixel P2 in the second cycle in the corresponding row buffer in sequence according to the beat of storing a single pixel in a single clock cycle.
[0025] The zooming and overlay processing program includes image zooming algorithm and pixel overlay algorithm. The simplest method in the image zooming algorithm is neighborhood interpolation, which is to copy and map each original pixel intact to the corresponding four pixels after expansion: this method retains all the information of the original image while enlarging the image, but it will produce aliasing. The effect of bilinear interpolation is smoother than that of neighborhood interpolation for the enlarged image, but it makes the image blurred and still has some aliasing. The pixel overlay algorithm is one of the common image processing techniques. It calculates the pixel values of two or more images to generate a new image. In Python, you can use libraries such as OpenCV or Pillow to implement image processing through pixel overlay.
[0026] In one embodiment of the present utility model, a video scaling device is provided, such as Figure 2 As shown, including:
[0027] A first processing chip, a dual-port memory, and a second processing chip, wherein a plurality of input pins of the first processing chip are connected to a processor for processing video data to obtain multiple pixel data; the first processing chip includes a write data pin, which is connected to a port of the dual-port memory; the second processing chip includes a read data pin, and a read data pin of the second processing chip is connected to another port of the dual-port memory; a timing control program is stored in a register of the first processing chip; a zoom overlay processing program is stored in the register of the second processing chip; and an output pin of the second processing chip is connected to a display.
[0028] The FPGA includes multiple groups of IO pins, so multiple IO pins are connected to the upstream video data processor as input pins of pixel data, so that the first processing chip can receive multiple pixel data streams at the same time.
[0029] The first processing chip runs the timing control program, and can write two pixels of two pixel data streams to the row cache of the dual-port memory in each clock cycle. Compared with the single-pixel stream processing architecture in the prior art, the multi-pixel data stream architecture of the present application caches more pixels in the same clock cycle. Therefore, when there is a requirement for the number of pixels, the present invention can reduce the requirement for the clock frequency, and the internal crystal oscillator of the FPGA can meet the clock requirement.
[0030] In order to avoid a processing chip freezing, resulting in the inability to implement video scaling or video data loss, in another embodiment of the present invention, a video scaler with a high stability architecture is provided, such as Figure 3 As shown, including:
[0031] A first processing chip, a dual-port memory, and a second processing chip, wherein multiple input pins of the first processing chip and the second processing chip are connected to a processor for processing video data to obtain multiple pixel data; the first processing chip includes a data read and write port, which is connected to one port of the dual-port memory; the second processing chip includes a data read and write port, which is connected to another port of the dual-port memory; the registers of the first processing chip and the second processing chip both store timing control programs and zoom overlay processing programs; the output pins of the first processing chip and the second processing chip are both connected to a display; the first processing chip and the second processing chip are connected via a high-speed serial link communication. The first processing chip and the second processing chip are both complex programmable logic devices, which include computing modules, registers, and core crystal oscillators.
[0032] Both the first processing chip and the second processing chip have the functions of timing control and pixel scaling and superposition. The first processing chip and the second processing chip are connected through a high-speed serial link communication, and can read each other's register data. Assuming that the first processing chip assumes the timing control function and the second processing chip assumes the pixel scaling and superposition function, once the first processing chip is stuck or fails, the second processing chip takes over the timing control function, reads the remaining data from the register of the first processing chip for timing processing, and obtains new pixel data from the video data processor for timing processing after the remaining data processing is completed, and performs scaling and superposition processing on the pixel data in the dual-port memory at the same time, that is, the second processing chip assumes all services. In this way, even if one chip is stuck, the other chip can also undertake the video scaling processing business.
[0033] Although the utility model is described in detail by referring to the accompanying drawings and in combination with the preferred embodiments, the utility model is not limited thereto. Without departing from the spirit and essence of the utility model, ordinary technicians in the field can make various equivalent modifications or substitutions to the embodiments of the utility model, and these modifications or substitutions should be within the scope of the utility model / any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed by the utility model, which should be included in the protection scope of the utility model. Therefore, the protection scope of the utility model shall be based on the protection scope of the claims.
Claims
1. A video scaling device, characterized in that: include: A first processing chip, a dual-port memory, and a second processing chip, wherein a plurality of input pins of the first processing chip are connected to a processor for processing video data to obtain a plurality of pixel data; the first processing chip includes a write data pin, and the write data pin is connected to one port of the dual-port memory; the second processing chip includes a read data pin, and a read data pin of the second processing chip is connected to another port of the dual-port memory; A timing control program is stored in the register of the first processing chip; a zooming and overlaying processing program is stored in the register of the second processing chip; and an output pin of the second processing chip is connected to a display.
2. The video scaling device according to claim 1, characterized in that: The first processing chip and the second processing chip are both complex programmable logic devices, which include a computing module, a register and a core crystal oscillator; the write data pins of the first processing chip are multiple IO pins of the first processing chip.
3. A video scaling device, characterized in that: a first processing chip, a dual-port memory, and a second processing chip, wherein a plurality of input pins of the first processing chip and the second processing chip are connected to a processor for processing video data to obtain a plurality of pixel data; the first processing chip includes a data read / write port, the data read / write port is connected to one port of the dual-port memory; the second processing chip includes a data read / write port, the data read / write port is connected to another port of the dual-port memory; The registers of the first processing chip and the second processing chip both store a timing control program and a zooming and overlaying processing program; the output pins of the first processing chip and the second processing chip are both connected to a display; The first processing chip and the second processing chip are communicatively connected via a high-speed serial link.
4. The video scaling device according to claim 3, characterized in that: The first processing chip and the second processing chip are both complex programmable logic devices, and the complex programmable logic devices include a computing module, a register, and a core crystal oscillator.