Semiconductor packaging structure

Abstract

The utility model provides a semiconductor packaging structure, and relates to the technical field of chip packaging, the semiconductor packaging structure comprises a substrate wiring layer, a first chip, a first plastic packaging layer, a switching wiring layer, a substrate, a second chip and a second plastic packaging layer, the first chip is pasted on the substrate wiring layer; the first plastic package layer is arranged on the substrate wiring layer and wraps the first chip; the switching wiring layer is arranged on the plastic packaging layer; the substrate is arranged on the switching wiring layer; the second chip is attached to the substrate; the second plastic package layer is arranged on the substrate and wraps the second chip; wherein a heat dissipation metal column is further arranged between the substrate and the first chip, and the heat dissipation metal column is connected to the substrate. Compared with the prior art, the semiconductor packaging structure provided by the utility model is additionally provided with the heat dissipation metal column, and the heat dissipation metal column is connected to the substrate, so that heat generated by the second chip can be transmitted to the heat dissipation channel and taken away, the heat dissipation capability is greatly improved, and the product performance is ensured.

Description

Technical Field

[0001] The utility model relates to the technical field of chip packaging, in particular to a semiconductor packaging structure. Background Art

[0002] With the rapid development of the semiconductor industry, wafer-level packaging structures are widely used in the semiconductor industry. It generally cuts a single chip from the wafer and then packages it onto a carrier wafer. Its main advantages are high-density integration, small packaged product size, superior product performance, and fast signal transmission frequency. In actual packaging, it is usually necessary to arrange multiple layers of rewiring layers to connect the functional pads and ground pads on the chip to the outside. Especially with the rise of mobile communication devices, the integration of system-on-chip (SoC) technology and memory technology has almost become a standard for high-end products. In order to further save packaging space, reduce package size, and simplify interconnection, integrated fan-out stacked packaging has also emerged. However, the more integrated chips there are, the worse the heat dissipation performance is, and the heat cannot be dissipated smoothly, which will affect product performance. Utility Model Content

[0003] The purpose of the utility model is to provide a semiconductor packaging structure, which can improve the heat dissipation performance of the packaged product and ensure product performance.

[0004] The embodiment of the utility model is achieved as follows:

[0005] In a first aspect, the utility model provides a semiconductor packaging structure, comprising:

[0006] Base wiring layer;

[0007] A first chip, wherein the first chip is attached to the base wiring layer;

[0008] A first plastic encapsulation layer, which is disposed on the base wiring layer and covers the first chip;

[0009] A transfer wiring layer, wherein the transfer wiring layer is arranged on the plastic packaging layer;

[0010] A substrate, wherein the substrate is disposed on the transfer wiring layer;

[0011] a second chip, the second chip being attached to the substrate;

[0012] A second plastic sealing layer, wherein the second plastic sealing layer is disposed on the substrate and covers the second chip;

[0013] A solder ball is provided at the bottom of the substrate, and the solder ball is connected to the transfer wiring layer to separate the substrate from the transfer wiring layer. A heat dissipation metal column is also provided between the substrate and the first chip, and the heat dissipation metal column is connected to the substrate and / or the first chip.

[0014] In an optional implementation, a chip opening penetrating to the first plastic packaging layer is provided on the transfer wiring layer, the chip opening is provided corresponding to the first chip, and the heat dissipation metal column extends to the chip opening.

[0015] In an optional embodiment, the heat dissipation metal column is disposed on a side of the substrate close to the first chip and extends toward the first chip into the chip opening, and the heat dissipation metal column is spaced apart from the first plastic packaging layer.

[0016] In an optional embodiment, the heat dissipation metal column is disposed on a side of the first chip away from the base wiring layer and extends toward the substrate into the chip opening, and the heat dissipation metal column is spaced apart from the substrate.

[0017] In an optional embodiment, a heat-conducting metal layer is disposed on a surface of the first chip on a side away from the base wiring layer, and the heat-dissipating metal column is disposed on the heat-conducting metal layer.

[0018] In an optional embodiment, the heat dissipation metal column includes a first metal column and a second metal column, the first metal column is arranged on a side of the substrate close to the first chip and extends toward the first chip into the chip opening, the second metal column is arranged on a side of the first chip away from the base wiring layer and extends toward the substrate into the chip opening, and the first metal column and the second metal column are arranged correspondingly.

[0019] In an optional embodiment, an end of the first metal column close to the first chip and an end of the second metal column close to the substrate are welded together.

[0020] In an optional embodiment, a conductive column is provided in the first plastic encapsulation layer, and two ends of the conductive column are respectively connected to the base wiring layer and the transfer wiring layer, so that the base wiring layer and the transfer wiring layer are electrically connected through the conductive column.

[0021] In an optional embodiment, a bonding bump is disposed on the bottom side of the first chip, a base pad is disposed on the base wiring layer, and the bonding bump is connected to the base pad.

[0022] In an optional implementation, a filling glue layer is disposed on the bottom side of the first chip, and the filling glue layer wraps around the bonding bumps.

[0023] The beneficial effects of the embodiments of the utility model include:

[0024] The semiconductor packaging structure provided by the embodiment of the utility model attaches the first chip to the base wiring layer, forms a first plastic sealing layer on the base wiring layer, wherein the first plastic sealing layer covers the outside of the first chip, arranges a transfer wiring layer on the first plastic sealing layer, arranges a substrate on the transfer wiring layer, attaches the second chip to the substrate, arranges a second plastic sealing layer on the substrate, and covers the outside of the second chip. The bottom of the substrate is connected to the transfer wiring layer through solder balls, so that the substrate and the transfer wiring layer are spaced apart, and the spacing can form a heat dissipation channel, and a heat dissipation metal column is also arranged between the substrate and the first chip, and the heat dissipation metal column is used to improve the overall heat dissipation capacity. Compared with the prior art, the semiconductor packaging structure provided by the utility model, by additionally arranging a heat dissipation metal column, the heat dissipation metal column is connected to the first chip and / or the substrate, and the heat generated by the first chip and / or the second chip can be transferred to the heat dissipation channel and taken away, thereby greatly improving the heat dissipation capacity and ensuring product performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions of the embodiments of the utility model, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the utility model and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without paying creative work.

[0026] Figure 1 A schematic diagram of a semiconductor packaging structure provided by a first embodiment of the utility model;

[0027] Figure 2 A schematic diagram of a semiconductor packaging structure provided by a second embodiment of the present utility model;

[0028] Figure 3 A schematic diagram of a semiconductor packaging structure provided by a third embodiment of the present invention.

[0029] icon:

[0030] 100-semiconductor packaging structure; 110-base wiring layer; 111-base solder pad; 120-first chip; 121-joining bump; 123-filling glue layer; 125-thermal conductive metal layer; 130-first plastic sealing layer; 131-conductive column; 140-transfer wiring layer; 141-chip opening; 150-substrate; 151-solder ball; 160-second chip; 170-second plastic sealing layer; 190-heat dissipation metal column; 191-first metal column; 193-second metal column. DETAILED DESCRIPTION

[0031] In order to make the purpose, technical scheme and advantages of the embodiments of the utility model clearer, the technical scheme in the embodiments of the utility model will be clearly and completely described below in conjunction with the drawings in the embodiments of the utility model. Obviously, the described embodiments are part of the embodiments of the utility model, not all of the embodiments. Generally, the components of the embodiments of the utility model described and shown in the drawings here can be arranged and designed in various different configurations.

[0032] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the present invention to be protected, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0033] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0034] In the description of the present utility model, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inside", "outside", etc. indicate the orientation or position relationship based on the orientation or position relationship shown in the accompanying drawings, or the orientation or position relationship in which the utility model product is usually placed when in use, which is only for the convenience of describing the utility model and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present utility model. In addition, the terms "first", "second", "third", etc. are only used to distinguish the description, and cannot be understood as indicating or implying relative importance.

[0035] In addition, the terms "horizontal", "vertical" and the like do not mean that the components are required to be absolutely horizontal or suspended, but can be slightly tilted. For example, "horizontal" only means that its direction is more horizontal than "vertical", and does not mean that the structure must be completely horizontal, but can be slightly tilted.

[0036] In the description of the present invention, it is also necessary to explain that, unless otherwise clearly specified and limited, the terms "set", "install", "connect", and "connect" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0037] First embodiment

[0038] Please refer to Figure 1 This embodiment provides a semiconductor packaging structure 100, which can improve the heat dissipation performance of the packaged product and ensure product performance, while achieving good structural support and ensuring the stability of the welding structure.

[0039] The semiconductor packaging structure 100 provided in this embodiment includes a base wiring layer 110, a first chip 120, a first plastic packaging layer 130, a transfer wiring layer 140, a substrate 150, a second chip 160 and a second plastic packaging layer 170. The first chip 120 is attached to the base wiring layer 110; the first plastic packaging layer 130 is arranged on the base wiring layer 110 and covers the first chip 120; the transfer wiring layer 140 is arranged on the plastic packaging layer; the substrate 150 is arranged on the transfer wiring layer 140; the second chip 160 is attached to the substrate 150; the second plastic packaging layer 170 is arranged on the substrate 150 and covers the second chip 160; wherein a solder ball 151 is arranged at the bottom of the substrate 150, and the solder ball 151 is connected to the transfer wiring layer 140 so that the substrate 150 and the transfer wiring layer 140 are spaced apart, and a heat dissipation metal column 190 is also arranged between the substrate 150 and the first chip 120, and the heat dissipation metal column 190 is connected to the substrate 150.

[0040] In this embodiment, the base wiring layer 110 can be formed by wiring on the carrier, the first chip 120 is electrically connected to the base wiring layer 110, and the transfer wiring layer 140 is electrically connected to the base wiring layer 110. The second chip 160 is disposed on the substrate 150 and is electrically connected to the transfer wiring layer 140 through the substrate 150. The bottom of the substrate 150 is connected to the transfer wiring layer 140 through the solder ball 151, so that the substrate 150 and the transfer wiring layer 140 are spaced apart, and the spacing can form a heat dissipation channel, and a heat dissipation metal column 190 is also disposed between the substrate 150 and the first chip 120. The heat dissipation metal column 190 is connected to the substrate 150, and the heat released by the second chip 160 and the substrate 150 can be transferred to the heat dissipation metal column 190, and the heat dissipation metal column 190 is used to improve the overall heat dissipation capacity.

[0041] In this embodiment, a chip opening 141 penetrating to the first plastic encapsulation layer 130 is provided on the transfer wiring layer 140, the chip opening 141 is provided corresponding to the first chip 120, and the heat dissipation metal column 190 extends to the chip opening 141. Specifically, the opening position of the chip opening 141 corresponds to the position of the first chip 120. By providing the chip opening 141, on the one hand, the accommodation space of the heat dissipation metal column 190 can be increased, and on the other hand, the lower first plastic encapsulation layer 130 can be exposed, and the thickness of the upper surface of the first chip 120 can be reduced, thereby improving the heat dissipation performance of the first chip 120.

[0042] In this embodiment, the heat dissipation metal column 190 is disposed on a side of the substrate 150 close to the first chip 120, and extends toward the first chip 120 to the chip opening 141, and the heat dissipation metal column 190 is spaced apart from the first plastic encapsulation layer 130. Specifically, a mounting pad is disposed on the bottom side of the substrate 150, and the heat dissipation metal column 190 can be formed by wire bonding or electroplating, and there can be a plurality of heat dissipation metal columns 190, which are spaced apart and are all located in the chip opening 141.

[0043] It should be noted that in this embodiment, the heat dissipation metal column 190 can be a copper column, and the gap width between the heat dissipation metal column 190 and the first plastic packaging layer 130 is relatively small. When the upper substrate 150 structure is actually installed, it is necessary to form a solder ball 151 on the bottom side of the substrate 150 and solder the solder ball 151 to the transfer wiring layer 140. The setting of the heat dissipation metal column 190 can also play a role in supporting the top-level chip, that is, supporting the substrate 150 to improve the solderability of the solder ball and prevent the collapse of the solder ball welding from causing the collapse of the substrate 150.

[0044] In this embodiment, a conductive column 131 is provided in the first plastic encapsulation layer 130, and both ends of the conductive column 131 are respectively connected to the base wiring layer 110 and the transfer wiring layer 140, so that the base wiring layer 110 and the transfer wiring layer 140 are electrically connected through the conductive column 131. Specifically, the conductive column 131 can be a copper column and is formed by an electroplating process. The conductive column 131 is embedded in the first plastic encapsulation layer 130 and realizes the electrical connection between the upper and lower wiring layers.

[0045] Furthermore, a bonding bump 121 is provided on the bottom side of the first chip 120, a base pad 111 is provided on the base wiring layer 110, and the bonding bump 121 is connected to the base pad 111. Specifically, the first chip 120 is fixed on the base wiring layer 110 by a flip-chip process, so as to avoid interference between the wire bonding structure and the conductive pillars 131 on both sides caused by a face-up process.

[0046] In this embodiment, a filling glue layer 123 is disposed on the bottom side of the first chip 120, and the filling glue layer 123 is coated around the bonding bumps 121. Specifically, the filling glue layer 123 can completely fill the gap between the first chip 120 and the base wiring layer 110, and extend to the side walls of the first chip 120 on both sides, thereby protecting the bottom welding structure, so as to improve the bonding and fixing effect of the first chip 120, and prevent the first chip 120 from falling off during plastic packaging.

[0047] In this embodiment, both the base wiring layer 110 and the transfer wiring layer 140 can be formed by sequentially depositing or electroplating a dielectric layer and a wiring layer. The basic structure and formation process thereof can refer to the relevant description in the prior art.

[0048] The embodiment of the present utility model further provides a method for preparing a semiconductor package structure 100, which is used to prepare the aforementioned semiconductor package structure 100. In actual preparation, the semiconductor package structure 100 can be prepared by the following steps:

[0049] First, take a substrate or carrier, use a coater to spin coat to form a liquid adhesive layer, and then use a hot plate to soft bake it to form a film. The carrier can be made of glass, silicon oxide, metal and other materials, and the adhesive layer (thermoplastic) can be a polymer composite material such as epoxy resin, polyimide, benzocyclobutene, etc. Then, the spin coating process is used again on the surface, and the first dielectric layer is formed by exposure and development. The dielectric layer material can be silicon nitride, silicon oxynitride, polyimide, benzocyclobutene, etc. The photomask (pattern layer) is covered on the dielectric layer again, and the pattern layer opening layer is formed by exposure and development process. The electroplating process is used again to form an electroplated metal layer on the pattern layer opening to form a wiring layer. The spin coating process is used again to form a second dielectric layer on the wiring layer. The dry etching process is used again to form an opening on the dielectric layer to expose the bottom wiring layer. The electroplating process is used again to form a conductive metal column on the hole and a metal layer (the material can be TI / TIWU, nickel NI, etc.) is formed on the surface of the metal column to improve the solderability of the solder ball through the metal layer. Finally, the electroplating process is used to form an electroplated metal column on the wiring layer, which is the conductive column 131, and then the first chip 120 is mounted, which is bonded to the metal layer by the reflow process.

[0050] After mounting the first chip 120, the first plastic layer 130 is formed again by the plastic encapsulation process, and the mounted first chip 120 is protected by the plastic encapsulation body. The transfer wiring layer 140 is formed again on the surface of the first plastic layer 130. The basic process is consistent with the base wiring layer 110. It should be noted here that the top surface of the first chip 120 does not need to be coated with a dielectric layer as a heat dissipation area, that is, a chip opening 141 is formed. Then the carrier is removed, and the module of the second chip 160 is mounted again. At this time, the second chip 160 is a packaged chip module, which is designed with a substrate 150. The heat dissipation metal column 190 is formed at the bottom of the substrate 150 by wire bonding. The ball planting process is performed on the copper column bump again by steel screen printing or electroplating tin ball method. The tin ball material can be SnAg, SnAgCu, etc. The cutting process is performed again to form the final product.

[0051] In summary, the present embodiment provides a semiconductor packaging structure 100, wherein a first chip 120 is attached to a base wiring layer 110, a first plastic encapsulation layer 130 is formed on the base wiring layer 110, wherein the first plastic encapsulation layer 130 covers the outside of the first chip 120, a transfer wiring layer 140 is arranged on the first plastic encapsulation layer 130, a substrate 150 is arranged on the transfer wiring layer 140, a second chip 160 is attached to the substrate 150, a second plastic encapsulation layer 170 is arranged on the substrate 150, and the second plastic encapsulation layer 170 covers the outside of the second chip 160. The bottom of the substrate 150 is connected to the transfer wiring layer 140 through a solder ball 151, so that the substrate 150 and the transfer wiring layer 140 are spaced apart, and the spacing can form a heat dissipation channel, and a heat dissipation metal column 190 is also arranged between the substrate 150 and the first chip 120, and the heat dissipation metal column 190 is used to improve the overall heat dissipation capacity. Compared with the prior art, the semiconductor packaging structure 100 provided by the present invention, by additionally setting a heat dissipation metal column 190, which is connected to the substrate 150, can transfer the heat generated by the second chip 160 to the heat dissipation channel and take it away, thereby greatly improving the heat dissipation capacity and ensuring product performance.

[0052] Second embodiment

[0053] See also Figure 2 This embodiment provides a semiconductor packaging structure 100, whose basic structure, principle and technical effects are the same as those of the first embodiment. For the sake of brief description, for parts not mentioned in this embodiment, reference may be made to the corresponding contents in the first embodiment.

[0054] In this embodiment, the heat dissipation metal column 190 is connected to the first chip 120. The heat dissipation metal column 190 can be arranged on a side of the first chip 120 away from the base wiring layer 110, and extend toward the substrate 150 to the chip opening 141, and the heat dissipation metal column 190 is spaced apart from the substrate 150. Specifically, the heat dissipation metal column 190 is embedded in the first plastic packaging layer 130 and exposed to the chip opening 141, which can improve the packaging structure strength of the first chip 120 on the one hand, and directly transfer the heat generated by the first chip 120 to the chip opening 141 and the heat dissipation channel on the other hand, thereby improving the heat dissipation effect.

[0055] In this embodiment, a heat-conducting metal layer 125 is disposed on a surface of the first chip 120 away from the base wiring layer 110, and the heat-dissipating metal column 190 is disposed on the heat-conducting metal layer 125. Specifically, by providing the heat-conducting metal layer 125, the heat dissipated by the first chip 120 can be better collected, further improving the heat dissipation effect.

[0056] Third embodiment

[0057] See also Figure 3This embodiment provides a semiconductor packaging structure 100, whose basic structure, principle and technical effects are the same as those of the first embodiment. For the sake of brief description, for parts not mentioned in this embodiment, reference may be made to the corresponding contents in the first embodiment.

[0058] In this embodiment, the heat dissipation metal column 190 is connected to the first chip 120 and the substrate 150, wherein the heat dissipation metal column 190 includes a first metal column 191 and a second metal column 193, the first metal column 191 is arranged on a side of the substrate 150 close to the first chip 120, and extends toward the first chip 120 to the chip opening 141, the second metal column 193 is arranged on a side of the first chip 120 away from the base wiring layer 110, and extends toward the substrate 150 to the chip opening 141, and the first metal column 191 and the second metal column 193 are arranged correspondingly.

[0059] In this embodiment, the first metal column 191 can improve the heat dissipation effect on the first chip 120, and the second metal column 193 can improve the heat dissipation effect on the second chip 160. Both the first metal column 191 and the second metal column 193 can transfer heat to the heat dissipation channel, thereby improving the heat dissipation effect.

[0060] In this embodiment, one end of the first metal column 191 close to the first chip 120 and one end of the second metal column 193 close to the substrate 150 are welded together. Specifically, by welding, the first metal column 191 and the second metal column 193 are integrally arranged, which can improve the overall structural strength. Of course, in other preferred embodiments of the utility model, the first metal column 191 and the second metal column 193 can also be spaced apart, thereby reducing the welding process.

[0061] The above are only preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention may be subject to various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A semiconductor packaging structure, characterized in that: include: Base wiring layer; A first chip, wherein the first chip is attached to the base wiring layer; A first plastic encapsulation layer, which is disposed on the base wiring layer and covers the first chip; A transfer wiring layer, wherein the transfer wiring layer is arranged on the plastic packaging layer; A substrate, wherein the substrate is disposed on the transfer wiring layer; a second chip, the second chip being attached to the substrate; A second plastic sealing layer, wherein the second plastic sealing layer is disposed on the substrate and covers the second chip; A solder ball is provided at the bottom of the substrate, and the solder ball is connected to the transfer wiring layer to separate the substrate from the transfer wiring layer. A heat dissipation metal column is also provided between the substrate and the first chip, and the heat dissipation metal column is connected to the substrate and / or the first chip.

2. The semiconductor package structure according to claim 1, wherein: The transfer wiring layer is provided with a chip opening penetrating to the first plastic packaging layer, the chip opening is provided corresponding to the first chip, and the heat dissipation metal column extends to the chip opening.

3. The semiconductor package structure according to claim 2, characterized in that: The heat dissipation metal column is arranged on a side of the substrate close to the first chip and extends toward the first chip into the chip opening, and the heat dissipation metal column is spaced apart from the first plastic packaging layer.

4. The semiconductor package structure according to claim 2, wherein: The heat dissipation metal column is arranged on a side of the first chip away from the base wiring layer and extends toward the substrate into the chip opening, and the heat dissipation metal column is spaced apart from the substrate.

5. The semiconductor package structure according to claim 4, characterized in that: A heat-conducting metal layer is disposed on a surface of the first chip on a side away from the base wiring layer, and the heat-dissipating metal column is disposed on the heat-conducting metal layer.

6. The semiconductor package structure according to claim 2, wherein: The heat dissipation metal column includes a first metal column and a second metal column. The first metal column is arranged on a side of the substrate close to the first chip and extends toward the first chip into the chip opening. The second metal column is arranged on a side of the first chip away from the base wiring layer and extends toward the substrate into the chip opening. The first metal column and the second metal column are arranged correspondingly.

7. The semiconductor package structure according to claim 6, characterized in that: An end of the first metal column close to the first chip and an end of the second metal column close to the substrate are welded together.

8. The semiconductor packaging structure according to any one of claims 2 to 7, characterized in that: A conductive column is disposed in the first plastic packaging layer, and two ends of the conductive column are respectively connected to the base wiring layer and the transfer wiring layer, so that the base wiring layer and the transfer wiring layer are electrically connected through the conductive column.

9. The semiconductor packaging structure according to any one of claims 2 to 7, characterized in that: The bottom side of the first chip is provided with a bonding bump, the base pad is provided on the base wiring layer, and the bonding bump is connected to the base pad.

10. The semiconductor package structure according to claim 9, characterized in that: A filling glue layer is disposed on the bottom side of the first chip, and the filling glue layer is coated around the bonding bumps.

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