Encoder circuit

Abstract

The utility model relates to an encoder circuit. The encoder circuit comprises an encoder, a first logic device, a second logic device, a third logic device, a first switching device, a second switching device, a third switching device and a fourth switching device, the first output end of the encoder is electrically connected with the first switching device, the first input end of the second logic device and the first input end of the third logic device; the second output end of the encoder is electrically connected with the second input end of the second logic device and the second input end of the third logic device; the output end of the first logic device is electrically connected with the second switching device; the output end of the second logic device is electrically connected with the third switching device, and the output end of the third logic device is electrically connected with the fourth switching device. Two output modes are integrated, any one of multiple pulse output modes can be realized only by adjusting connection or disconnection of the switching device, the production process is greatly simplified, and the production cost is effectively reduced.

Description

Technical Field

[0001] The present application relates to the technical field of encoders, and in particular to an encoder circuit. Background Art

[0002] The fuel dispenser encoder is the core component of the fuel dispenser system. When the start button of the fuel dispenser is activated, the system's motor is activated, the gasoline enters the flow measurement converter and drives the encoder to rotate, thereby converting the corresponding angular displacement signal into an electrical pulse signal, which is transmitted to the metering MCU end of the fuel dispenser mainboard, thereby obtaining an accurate fuel volume. It should be noted here that different models of fuel dispenser mainboards have different requirements for the two-way electrical pulse signals output by the encoder. Specifically, some fuel dispenser mainboards require that the phase difference between the two-way electrical pulse signals output by the encoder is 180 degrees, and some fuel dispenser mainboards require that the two-way electrical pulse signals output by the encoder be narrow pulse signals. At present, in order to meet the requirements of these two fuel dispenser mainboards, it is necessary to design corresponding encoder circuits for each requirement, which increases the difficulty of encoder generation. Therefore, how to solve the above problems is a technical problem that technical personnel need to solve urgently. Summary of the invention

[0003] In view of this, the present application proposes an encoder circuit suitable for integrating two output modes of pulse signals on the same circuit.

[0004] According to one aspect of the present application, an encoder circuit is provided, characterized in that it includes: an encoder, a first logic device, a second logic device, a third logic device, a first switch device, a second switch device, a third switch device and a fourth switch device;

[0005] The input end of the encoder is suitable for obtaining a mechanical rotation signal corresponding to the refueling amount, and converting the mechanical rotation signal into a pulse signal A90 and a pulse signal B90, wherein the phase difference between the pulse signal A90 and the pulse signal B90 is 90 degrees, and the encoder includes a first output end and a second output end, the first output end is used to output the pulse signal A90, and the second output end is used to output the pulse signal B90;

[0006] The first output terminal of the encoder is electrically connected to the first switch device, so that when the first switch device is turned on, the pulse signal A90 is output through the first switch device, and the input terminal of the first switch device is also electrically connected to the external power supply through the resistor R8;

[0007] The input end of the first logic device is electrically connected to the first output end of the encoder, and is used to receive the pulse signal A90, and invert the pulse signal A90 to obtain a reverse pulse signal A90_FAN. The output end of the first logic device is electrically connected to the second switch device, so that when the second switch device is turned on, the reverse pulse signal A90_FAN is output through the second switch device.

[0008] The first input end of the second logic device is electrically connected to the first output end of the encoder, and is used to receive the pulse signal A90. The second input end of the second logic device is electrically connected to the second output end of the encoder, and is used to receive the pulse signal B90. The second logic device is suitable for performing a phase-OR logic operation on the pulse signal A90 and the pulse signal B90 to obtain a first narrow pulse signal. The output end of the second logic device is electrically connected to the third switch device, so that when the third switch device is turned on, the first narrow pulse signal is output through the third switch device.

[0009] The first input end of the third logic device is electrically connected to the first output end of the encoder for receiving the pulse signal A90. The second input end of the third logic device is electrically connected to the second output end of the encoder for receiving the pulse signal B90. The third logic device is suitable for performing a logical operation of AND and inversion on the pulse signal A90 and the pulse signal B90 to obtain a second narrow pulse signal. The output end of the third logic device is electrically connected to the fourth switch device so that when the fourth switch device is turned on, the second narrow pulse signal is output through the fourth switch device.

[0010] In a possible implementation, the device further includes: a fifth switching device;

[0011] The second output terminal of the encoder is electrically connected to the fifth switching device, so that when the fifth switching device is turned on, the pulse signal B90 is output through the fifth switching device.

[0012] In a possible implementation, it further includes: a signal output module;

[0013] The output end of the first switch device, the output end of the second switch device, the output end of the third switch device, the output end of the fourth switch device, and the output end of the fifth switch device are all electrically connected to the input end of the signal output module, and the output end of the signal output module is suitable for being electrically connected to the input end of the MCU.

[0014] In a possible implementation, the signal output module includes: two or more signal amplification circuits;

[0015] The output end of the first switch device, the output end of the second switch device, the output end of the third switch device, the output end of the fourth switch device, and the output end of the fifth switch device are electrically connected to the MCU through more than two signal amplification circuits respectively.

[0016] In a possible implementation, two signal amplification circuits are provided;

[0017] The output end of the second switch device, the output end of the fourth switch device, and the output end of the fifth switch device are electrically connected to the input end of one of the signal amplifying circuits;

[0018] The output end of the first switching device and the output end of the third switching device are electrically connected to the input end of another signal amplifying circuit.

[0019] In a possible implementation manner, the first logic device is a NOT gate.

[0020] In a possible implementation manner, the second logic device is an OR gate.

[0021] In a possible implementation manner, the third logic device is a NAND gate.

[0022] In a possible implementation, the first switch device, the second switch device, the third switch device, the fourth switch device and the fifth switch device all include: a wiring cap and two wiring nodes;

[0023] One of the wiring nodes is electrically connected to the first output terminal or the second output terminal of the encoder, and the other wiring node is electrically connected to the signal output module;

[0024] The wiring cap is detachably connected to the two wiring nodes; the two wiring nodes can be connected through the wiring cap.

[0025] Beneficial effect: The present application integrates two output modes in one. Different connection modes can be adopted according to different output requirements. The four transmission lines between the encoder and the MCU, the first logic device 100 and the MCU, the second logic device 200 and the MCU, and the third logic device 300 and the MCU can be started and stopped at any time by simply adjusting the connection or disconnection of the switch device. Any of a variety of pulse output modes (two pulse signals with a phase difference of 180 degrees in opposite directions, and two narrow pulse signals with a duty cycle of 1:4) can be realized, which greatly simplifies the production process and effectively reduces production costs.

[0026] Other features and aspects of the present application will become apparent from the following detailed description of exemplary embodiments with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate exemplary embodiments, features, and aspects of the present application and, together with the description, serve to explain the principles of the present application.

[0028] Figure 1A circuit diagram showing an encoder circuit according to an embodiment of the present application;

[0029] Figure 2 A circuit diagram showing a magnetic encoder chip of an encoder according to an embodiment of the present application;

[0030] Figure 3 A circuit diagram showing a first logic device according to an embodiment of the present application;

[0031] Figure 4 A circuit diagram showing a second logic device according to an embodiment of the present application;

[0032] Figure 5 A circuit diagram of a third logic device according to an embodiment of the present application is shown. DETAILED DESCRIPTION

[0033] Various exemplary embodiments, features and aspects of the present application will be described in detail below with reference to the accompanying drawings. The same reference numerals in the accompanying drawings represent elements with the same or similar functions. Although various aspects of the embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise specified.

[0034] Among them, it needs to be understood that the terms "center", "longitudinal", "lateral", "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the utility model or simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the utility model.

[0035] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present utility model, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0036] The word “exemplary” is used exclusively herein to mean “serving as an example, example, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

[0037] In addition, in order to better illustrate the present application, numerous specific details are given in the following specific embodiments. It should be understood by those skilled in the art that the present application can also be implemented without certain specific details. In some examples, methods, means, components and circuits well known to those skilled in the art are not described in detail in order to highlight the subject matter of the present application.

[0038] Figure 1 A circuit diagram showing an encoder circuit according to an embodiment of the present application; Figure 2 A circuit diagram showing a magnetic encoder chip of an encoder according to an embodiment of the present application; Figure 3 A circuit diagram showing a first logic device according to an embodiment of the present application; Figure 4 A circuit diagram showing a second logic device according to an embodiment of the present application; Figure 5The circuit diagram of the third logic device of the embodiment of the present application is shown. The encoder circuit includes: an encoder, a first logic device 100, a second logic device 200, a third logic device 300, a first switch device, a second switch device, a third switch device and a fourth switch device; the input end of the encoder obtains a mechanical rotation signal corresponding to the refueling amount, and the encoder converts the rotation signal into a pulse signal A90 and a pulse signal B90 and outputs them, wherein the phase difference between the pulse signal A90 and the pulse signal B90 is 90 degrees, and the encoder is provided with a first output end and a second output end, the first output end is used to output the pulse signal A90, and the second output end is used to output the pulse signal B90. The first output terminal of the encoder is electrically connected to the first switch device, so that when the first switch device is turned on, the pulse signal A90 is output through the first switch device, and the input terminal of the first switch device is also electrically connected to the external power supply through the resistor R8; the input terminal of the first logic device 100 is electrically connected to the first output terminal of the encoder, and is used to receive the pulse signal A90, and invert the pulse signal A90 to obtain the reverse pulse signal A90_FAN, and the output terminal of the first logic device 100 is electrically connected to the second switch device, so that when the second switch device is turned on, the pulse signal A90 is output through the second switch device. The first input end of the second logic device 200 is electrically connected to the first output end of the encoder for receiving the pulse signal A90, and the second input end of the second logic device 200 is electrically connected to the second output end of the encoder for receiving the pulse signal B90. The second logic device 200 is suitable for performing a phase-OR logic operation on the pulse signal A90 and the pulse signal B90 to obtain a first narrow pulse signal. The output end of the second logic device 200 is electrically connected to the third switch device so that when the third switch device is turned on, the third narrow pulse signal is output through the third switch device. a narrow pulse signal; a first input end of the third logic device 300 is electrically connected to the first output end of the encoder for receiving the pulse signal A90; a second input end of the third logic device 300 is electrically connected to the second output end of the encoder for receiving the pulse signal B90; the third logic device 300 is suitable for performing a logical operation of AND and inversion on the pulse signal A90 and the pulse signal B90 to obtain a second narrow pulse signal; an output end of the third logic device 300 is electrically connected to the fourth switch device so that when the fourth switch device is turned on, the second narrow pulse signal is output through the fourth switch device.

[0039] Here, it should be noted that the encoder uses a magnetic position sensor SD3012 based on the Hall principle. When the start button of the gas pump is activated, the flow measurement converter will rotate its mechanical transmission shaft under the action of the liquid flow. Each rotation will drive the rotation of the magnet fixed on the shaft. The rotation of the magnet forms a change in the N and S levels of the magnet. The encoder's magnetic encoder chip U3 can calculate the angle of the magnetic field change based on the change in the magnetic field, thereby determining the angle of the shaft rotation, and then realize the encoder monitoring the angle and number of turns of the mechanical transmission shaft rotation, converting the mechanical transmission into an electrical pulse signal and outputting it. In the initial state, if Figure 2 As shown, the two output ends of the magnetic encoder chip U3 (i.e., the first output end and the second output end of the encoder) output two pulse signals AB with a phase difference of 90 degrees, namely, pulse signal A90 and pulse signal B90; the first output end and the second output end of the encoder are always electrically connected to the first logic device 100, the second logic device 200, and the third logic device 300, and the circuits between the first logic device 100, the second logic device 200, the third logic device 300, the encoder and the MCU are electrically connected by setting switch devices, so that the first logic device 100, the second logic device 200, the third logic device 300, the encoder and the MCU can be arbitrarily connected and disconnected, so that the two output modes can be changed at any time.

[0040] Further, such as Figure 1 As shown, the first output end of the encoder directly outputs a pulse signal A90 to the input end of the MCU through the first switching device; the first output end of the encoder is electrically connected to the first logic device 100 and is suitable for outputting a pulse signal A90 to the first logic device 100, and the pulse signal A90_FAN is obtained by inverting the first logic device 100 and outputting it to the second switching device, and the second switching device outputs a pulse signal A90_FAN to the input end of the MCU; in summary, two pulse signals A90 and pulse signal A90_FAN with a phase difference of 180 degrees in the opposite direction can be output to the input end of the MCU.

[0041] Further, such as Figure 1 As shown, the first output terminal and the second output terminal of the encoder are electrically connected to the second logic device 200 at the same time, and are suitable for simultaneously outputting two pulse signals A90 and pulse signal B90 to the second logic device 200. After the second logic device 200 performs an OR operation, the first narrow pulse signal A_ZHAI is obtained and output to the third switch device; the two output terminals of the encoder are electrically connected to the third logic device 300, and are suitable for simultaneously outputting two pulse signals A90 and pulse signal B90 to the third logic device 300. After the third logic device 300 performs an AND operation on the two pulse signals and then inverts them, the second narrow pulse signal B_ZHAI is obtained and output to the fourth switch device. In summary, two narrow pulse signals with a duty cycle of 1:4 can be output.

[0042] The present application integrates two output modes in one. Different connection modes can be adopted according to different output requirements. The four transmission lines between the encoder and the MCU, the first logic device 100 and the MCU, the second logic device 200 and the MCU, and the third logic device 300 and the MCU can be started and stopped at any time by simply adjusting the connection or disconnection of the switch device. Any of a variety of pulse output modes (two pulse signals with a phase difference of 180 degrees in opposite directions, two narrow pulse signals with a duty cycle of 1:4) can be realized, which greatly simplifies the production process and effectively reduces the production cost.

[0043] In a possible implementation, it also includes: a fifth switch device; the second output terminal of the encoder is electrically connected to the fifth switch device, so that when the fifth switch device is turned on, the pulse signal B90 is output through the fifth switch device. It should be noted that in the initial state, the encoder can output two pulse signals A90 and B90 with a phase difference of 90 degrees, and the first switch device and the fifth switch device are suitable for directly accessing the two pulse signals and directly outputting two pulse signals with a phase difference of 90 degrees. Further, the first output terminal of the encoder is electrically connected to the input terminal of the first switch device, and the output terminal of the first switch device is suitable for outputting a pulse signal A90; the second output terminal of the encoder is electrically connected to the input terminal of the fifth switch device, and the output terminal of the fifth switch device is suitable for outputting a pulse signal B90; so as to output two pulse signals with a phase difference of 90 degrees to the input terminal of the MCU.

[0044] In a possible implementation, it also includes: a mainboard; the first logic device, the second logic device, the third logic device, the first switch device, the second switch device, the third switch device, the fourth switch device, and the fifth switch device are all integrated on a mainboard, and the output of the three pulse signals can be adjusted at any time. The mainboard is suitable for installing and supporting various electronic devices as a carrier. The three output modes are all integrated on a mainboard. According to different output requirements, different connection methods are adopted. Any of a variety of pulse output modes (two pulse signals with a phase difference of 180 degrees, two narrow pulse signals with a duty cycle of 1:4, and two pulse signals with a phase difference of 90 degrees) can be realized by simply changing the jumper wires.

[0045] In a possible implementation, the 6th pin of the magnetic encoder chip U3 is the first output end of the encoder, and the 7th pin of the magnetic encoder chip U3 is the second output end of the encoder. Figure 2As shown, pin 1 of the magnetic encoder chip U3 is connected to the VCC power supply, and pins 2 and 4 of the magnetic encoder chip U3 are grounded; pin 6 of the magnetic encoder chip U3 (the first output end of the encoder) outputs a pulse signal A90, and pin 7 of the magnetic encoder chip U3 (the second output end of the encoder) outputs a pulse signal B90. Furthermore, the 6th pin of the magnetic encoder chip U3 is electrically connected to the input end of the first switch device to directly output the pulse signal A90, the 6th pin of the magnetic encoder chip U3 is electrically connected to the input end of the first logic device 100 to output the pulse signal A90, the 6th pin of the magnetic encoder chip U3 is electrically connected to the input end of the second logic device 200 to output the pulse signal A90, and the 6th pin of the magnetic encoder chip U3 is electrically connected to the input end of the third logic device 300 to output the pulse signal A90; the 7th pin of the magnetic encoder chip U3 is electrically connected to the input end of the fifth switch device to directly output the pulse signal B90, the 7th pin of the magnetic encoder chip U3 is electrically connected to the input end of the second logic device 200 to output the pulse signal B90, and the 7th pin of the magnetic encoder chip U3 is electrically connected to the input end of the third logic device 300 to output the pulse signal B90.

[0046] In a possible implementation, the first logic device 100 is a NOT gate U4. Figure 3 As shown, the first pin of the NOT gate U4 (the first input terminal of the first logic device 100) is electrically connected to the sixth pin of the magnetic encoder chip U3 to access the pulse signal A90, the second pin of the NOT gate U4 is connected to the working power supply through the capacitor C7, and the third pin (ground terminal) of the NOT gate U4 is grounded; the fourth pin of the NOT gate U4 is electrically connected to the input terminal of the second switch device to transmit the inverted pulse signal A90_FAN.

[0047] In a possible implementation, the second logic device 200 is an OR gate U6. Figure 4 As shown, the first pin of the OR gate U6 (the first input end of the second logic device 200) is electrically connected to the sixth pin of the magnetic encoder chip U3 to access the pulse signal A90, the second pin of the OR gate U6 (the second input end of the second logic device 200) is electrically connected to the seventh pin of the magnetic encoder chip U3 to access the pulse signal B90, and the third pin (ground end) of the OR gate U6 is grounded; the fourth pin of the OR gate U6 is electrically connected to the input end of the third switch device to transmit a narrow pulse signal; the fifth pin of the OR gate U6 is connected to the working power supply through the capacitor C5.

[0048] In a possible implementation, the third logic device 300 is a NAND gate U5. Figure 5As shown, the first pin of the NAND gate U5 (the first input end of the third logic device 300) is electrically connected to the sixth pin of the magnetic encoder chip U3 to access the pulse signal A90, the second pin of the NAND gate U5 (the second input end of the third logic device 300) is electrically connected to the seventh pin of the magnetic encoder chip U3 to access the pulse signal B90, and the third pin (ground end) of the NAND gate U5 is grounded; the fourth pin of the NAND gate U5 is electrically connected to the input end of the fourth switch device to transmit another narrow pulse signal; the fifth pin of the NAND gate U5 is connected to the working power supply through the capacitor C6.

[0049] In a possible implementation, the first switch device, the second switch device, the third switch device, the fourth switch device and the fifth switch device all include: a wiring cap and two wiring nodes; one of the wiring nodes is electrically connected to the magnetic encoder chip U3 or each logic device to access the pulse signal, and the other wiring node is electrically connected to the signal output module; the wiring cap is detachably connected to the two wiring nodes; and the two wiring nodes can be connected through the wiring cap.

[0050] Further, such as Figure 1 As shown, the first switch device is a matching wiring cap and wiring node JP4. The wiring cap can be inserted into the wiring node JP4. When the wiring cap is inserted into the wiring node JP4, the first switch device is turned on and a pulse signal A90 can be output. When the wiring cap is removed from the wiring node JP4, the second switch device is cut off and the pulse signal A90 cannot be output.

[0051] Further, such as Figure 1 As shown, the second switch device is a matching wiring cap and wiring node JP2. The wiring cap can be inserted into the wiring node JP2. When the wiring cap is inserted into the wiring node JP2, the second switch device is turned on and a pulse signal A90_FAN can be output; when the wiring cap is removed from the wiring node JP2, the second switch device is cut off and the pulse signal A90_FAN cannot be output.

[0052] Further, such as Figure 1 As shown, the third switch device is a matching wiring cap and wiring node JP5, and the wiring cap can be inserted into the wiring node JP5. When the wiring cap is inserted into the wiring node JP5, the third switch device is turned on, and the first narrow pulse signal A_ZHAI can be output; when the wiring cap is removed from the wiring node JP5, the second switch device is cut off, and the first narrow pulse signal A_ZHAI cannot be output.

[0053] Furthermore, as shown in the figure, the fourth switch device is a matching wiring cap and wiring node JP3, and the wiring cap can be inserted into the wiring node JP3. When the wiring cap is inserted into the wiring node JP3, the fourth switch device is turned on and the second narrow pulse signal B_ZHAI can be output; when the wiring cap is removed from the wiring node JP3, the fourth switch device is cut off and the second narrow pulse signal B_ZHAI cannot be output.

[0054] Furthermore, as shown in the figure, the fifth switch device is a matching wiring cap and wiring node JP1, and the wiring cap can be inserted into the wiring node JP1. When the wiring cap is inserted into the wiring node JP1, the fifth switch device is turned on and a pulse signal B90 can be output; when the wiring cap is removed from the wiring node JP1, the fifth switch device is cut off and the pulse signal B90 cannot be output.

[0055] In another possible implementation, the first switch device, the second switch device, the third switch device, the fourth switch device, and the fifth switch device may also be on-off switches.

[0056] In a possible implementation, it also includes: a signal output module; the output end of the first switching device, the output end of the second switching device, the output end of the third switching device, the output end of the fourth switching device, and the output end of the fifth switching device are all electrically connected to the input end of the signal output module, and the output end of the signal output module is suitable for being electrically connected to the input end of the MCU.

[0057] In a possible implementation, the signal output module includes: more than two signal amplifying circuits; the output end of the first switch device, the output end of the second switch device, the output end of the third switch device, the output end of the fourth switch device, and the output end of the fifth switch device are electrically connected to the MCU through more than two signal amplifying circuits. It should be noted that in order to improve the stability of signal transmission, multiple signal amplifying circuits are set to amplify the signal strength of the electrical signals on the two output lines in different modes, so that the signal can be better transmitted in the circuit and the signal output quality is improved.

[0058] In one possible implementation, two signal amplifying circuits are provided; the output end of the second switching device, the output end of the fourth switching device, and the output end of the fifth switching device are electrically connected to the output end of one of the signal amplifying circuits, that is, the first signal amplifying circuit 400 is suitable for accessing one of the pulse signals; the output end of the first switching device and the output end of the third switching device are electrically connected to the output end of another signal amplifying circuit, that is, the second signal amplifying circuit 500 is suitable for accessing another pulse signal.

[0059] In a possible implementation, the first signal amplifying circuit 400 includes a transistor Q1; Figure 1As shown, the base (pin 1) of the transistor Q1 on the first signal amplifying circuit 400 is electrically connected to the input end of the second switch device, the input end of the fourth switch device, and the input end of the fifth switch device, and is suitable for receiving a pulse signal; the collector (pin 3) of the transistor Q1 is suitable for receiving a working power supply and outputting a pulse signal; the emitter (pin 2) of the transistor Q1 is grounded. It should be noted that Figure 1 Point B of the first signal amplifying circuit 400 is a pulse signal output terminal.

[0060] In a possible implementation, the first signal amplifying circuit 400 is provided with a resistor R1 , one end of the resistor R1 is connected to the power signal, and the other end of the resistor R1 is electrically connected to the collector (pin 3 ) of the transistor Q1 .

[0061] In a possible implementation, the first signal amplifying circuit 400 is provided with a resistor R3, one end of the resistor R3 is electrically connected to the base (pin 1) of the transistor Q1, and the other end of the resistor R3 is electrically connected to the output end of the second switching device, the output end of the fourth switching device, and the output end of the fifth switching device.

[0062] In a possible implementation, the first signal amplifying circuit 400 is provided with a resistor R4, one end of the resistor R4 is electrically connected to the connection circuit between the base (pin 1) of the transistor Q1 and the resistor R3, and the other end of the resistor R4 is grounded.

[0063] In a possible implementation, the first signal amplifying circuit 400 is provided with a resistor R6, one end of the resistor R6 is electrically connected to the connection circuit of the resistor R3 connected to the switch device, and the other end of the resistor R6 is connected to the power supply.

[0064] In a possible implementation, the second signal amplifying circuit 500 is provided with a transistor Q2; Figure 1 As shown, the base (pin 1) of the transistor Q2 on the second signal amplifying circuit 500 is electrically connected to the output end of the first switching device and the output end of the third switching device; the collector (pin 3) of the transistor Q2 is suitable for outputting a pulse signal and connecting to a power supply; the emitter (pin 2) of the transistor Q2 is grounded. It should be noted that Figure 1 Point A of the second signal amplifying circuit 500 is a pulse signal output port.

[0065] In a possible implementation, the second signal amplifying circuit 500 is provided with a resistor R7, one end of the resistor R7 is connected to the power signal, and the other end of the resistor R7 is electrically connected to the collector (pin 3) of the transistor Q2.

[0066] In a possible implementation, the second signal amplifying circuit 500 is provided with a resistor R9, one end of which is electrically connected to the base (pin 1) of the transistor Q2, and the other end of which is electrically connected to the output end of the first switching device and the output end of the third switching device.

[0067] In a possible implementation, the second signal amplifying circuit 500 is provided with a resistor R10, one end of the resistor R10 is electrically connected to the connection circuit between the base (pin 1) of the transistor Q2 and the resistor R9, and the other end of the resistor R10 is grounded.

[0068] When it is necessary to output two pulse signals with a phase difference of 180 degrees: turn on the first switch device and the second switch device, and cut off the third switch device, the fourth switch device and the fifth switch device. The input end of the first switch device is directly electrically connected to the 6th pin of the magnetic encoder chip U3 to access a pulse signal A90, and the output end of the first switch device directly outputs a pulse signal A90; the input end of the second switch device is electrically connected to the 4th pin of the first logic device 100 to access a converted pulse signal A90_FAN, and the output end of the second switch device outputs a pulse signal A90_FAN; at this time, two pulse signals with a phase difference of 180 degrees can be output.

[0069] When it is necessary to output two narrow pulse signals: turn on the third switch device and the fourth switch device, and cut off the first switch device, the second switch device and the fifth switch device; the input end of the third switch device is electrically connected to the 4th pin of the second logic device 200 to access the converted first narrow pulse signal A_ZHAI; the output end of the third switch device outputs the first narrow pulse signal A_ZHAI; the input end of the fourth switch device is electrically connected to the 4th pin of the third logic device 300 to access the converted second narrow pulse signal B_ZHAI; the output end of the third switch device outputs the second narrow pulse signal B_ZHAI; at this time, two narrow pulse signals can be output.

[0070] When it is necessary to output two pulse signals with a phase difference of 90 degrees: turn on the first switch device and the fifth switch device, and cut off the second switch device, the third switch device and the fourth switch device; the input end of the first switch device is directly electrically connected to the 6th pin of the magnetic encoder chip U3 to access a pulse signal A90, and the output end of the first switch device directly outputs a pulse signal A90; the input end of the fifth switch device is directly electrically connected to the 7th pin of the magnetic encoder chip U3 to access a pulse signal B90, and the output end of the fifth switch device directly outputs a pulse signal B90; that is, two pulse signals with a phase difference of 90 degrees can be output.

[0071] The embodiments of the present application have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or improvements to the technology in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. An encoder circuit, characterized in that: include: An encoder, a first logic device, a second logic device, a third logic device, a first switching device, a second switching device, a third switching device and a fourth switching device; The input end of the encoder is suitable for obtaining a mechanical rotation signal corresponding to the refueling amount, and converting the mechanical rotation signal into a pulse signal A90 and a pulse signal B90, wherein the phase difference between the pulse signal A90 and the pulse signal B90 is 90 degrees, and the encoder is provided with a first output end and a second output end, wherein the first output end is used to output the pulse signal A90, and the second output end is used to output the pulse signal B90; The first output terminal of the encoder is electrically connected to the first switch device, so that when the first switch device is turned on, the pulse signal A90 is output through the first switch device, and the input terminal of the first switch device is also electrically connected to an external power supply through a resistor R8; The input end of the first logic device is electrically connected to the first output end of the encoder, and is used to receive the pulse signal A90, and invert the pulse signal A90 to obtain a reverse pulse signal A90_FAN. The output end of the first logic device is electrically connected to the second switch device, so that when the second switch device is turned on, the reverse pulse signal A90_FAN is output through the second switch device. The first input end of the second logic device is electrically connected to the first output end of the encoder for receiving the pulse signal A90, the second input end of the second logic device is electrically connected to the second output end of the encoder for receiving the pulse signal B90, the second logic device is suitable for performing a phase OR logic operation on the pulse signal A90 and the pulse signal B90 to obtain a first narrow pulse signal, and the output end of the second logic device is electrically connected to the third switch device, so as to output the first narrow pulse signal through the third switch device when the third switch device is turned on; The first input end of the third logic device is electrically connected to the first output end of the encoder for receiving the pulse signal A90. The second input end of the third logic device is electrically connected to the second output end of the encoder for receiving the pulse signal B90. The third logic device is suitable for performing a logical operation of AND and inversion on the pulse signal A90 and the pulse signal B90 to obtain a second narrow pulse signal. The output end of the third logic device is electrically connected to the fourth switch device so that when the fourth switch device is turned on, the second narrow pulse signal is output through the fourth switch device.

2. An encoder circuit according to claim 1, characterized in that: Also includes: a fifth switching device; The second output terminal of the encoder is electrically connected to the fifth switching device, so that when the fifth switching device is turned on, the pulse signal B90 is output through the fifth switching device.

3. An encoder circuit according to claim 2, characterized in that: Also includes: signal output module; The output end of the first switching device, the output end of the second switching device, the output end of the third switching device, the output end of the fourth switching device, and the output end of the fifth switching device are all electrically connected to the input end of the signal output module, and the output end of the signal output module is suitable for being electrically connected to the input end of the MCU.

4. An encoder circuit according to claim 3, characterized in that: The signal output module includes: more than two signal amplification circuits; The output end of the first switching device, the output end of the second switching device, the output end of the third switching device, the output end of the fourth switching device, and the output end of the fifth switching device are electrically connected to the MCU through more than two of the signal amplification circuits.

5. An encoder circuit according to claim 4, characterized in that: The signal amplification circuit is provided with two; The output end of the second switch device, the output end of the fourth switch device, and the output end of the fifth switch device are electrically connected to the input end of one of the signal amplifying circuits; The output end of the first switching device and the output end of the third switching device are electrically connected to the input end of another signal amplifying circuit.

6. An encoder circuit according to claim 1, characterized in that: The first logic device is a NOT gate.

7. An encoder circuit according to claim 1, characterized in that: The second logic device is an OR gate.

8. An encoder circuit according to claim 1, characterized in that: The third logic device is a NAND gate.

9. An encoder circuit according to claim 4, characterized in that: The first switch device, the second switch device, the third switch device, the fourth switch device and the fifth switch device each include: a wiring cap and two wiring nodes; One of the wiring nodes is electrically connected to the first output terminal or the second output terminal of the encoder, and the other wiring node is electrically connected to the signal output module; The wiring cap is detachably connected to the two wiring nodes; the two wiring nodes can be connected through the wiring cap.

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