Multi-channel memory chip test aging structure
By designing a multi-channel memory chip to test the aging structure, using multiple experimental boxes and temperature and humidity controllers, the problem of only testing a single vector in the existing technology is solved, and a comprehensive acquisition of test data is achieved, which significantly improves the testing Efficiency and accuracy.
Patent Information
- Application Number
- CN202420058876.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-01-09
- Publication Date
- 2024-12-31
- Estimated Expiration
- 2034-01-09
AI Technical Summary
Existing memory chip testing devices can only test a single vector, which results in a long time-consuming test process and affects efficiency.
Design a multi-channel memory chip test aging structure, including multiple experimental boxes and test boards, which can perform aging tests in multiple vector environments at the same time, and obtain all-round test data through multiple experimental boxes and temperature and humidity controllers.
It reduces the test cycle, improves detection efficiency and accuracy, and can test multiple vectors at the same time, significantly improving the testing efficiency.
Smart Images
Figure CN222281590U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of memory chip testing and aging, in particular to a multi-channel memory chip testing and aging structure. Background Art
[0002] When testing the aging of storage chips, it is necessary to arrange the chip array in the card slot of the aging test board, and then put the test board into the aging test box of the equipment, and then close the door of the aging test box to form a sealed environment inside the test box. During the experiment, the test vector is input to the chip from the digital channel of the aging test box to put the entire chip in a working state. For the accuracy of the data, it is necessary to test a variety of different vector data. However, during the test process of the current device, only a single vector can be tested and compared, so multiple tests are required, which consumes more time and greatly affects the test efficiency.
[0003] Based on this, a multi-channel memory chip test aging structure is now provided to eliminate the drawbacks of existing devices. Utility Model Content
[0004] The utility model aims to provide a multi-channel memory chip test aging structure to solve the problem that multiple vectors cannot be tested in the background technology.
[0005] In order to achieve the above purpose, the utility model provides the following technical solutions:
[0006] A multi-channel memory chip test aging structure comprises a box structure and an experimental box, wherein the box structure comprises a body, the bottom of the body is fixedly connected with supporting feet, and the front of the body is provided with an experimental box, and the experimental box is used for side-viewing the chip.
[0007] On the basis of the above technical solutions, the present invention also provides the following optional technical solutions:
[0008] In an optional solution, there are at least three experimental boxes.
[0009] In an optional solution: the surface of the test box is rotatably connected to the sealed box door, the surface of the sealed box door is fixedly connected to the door handle, the inner wall of the test box is fixedly connected to the protrusion, and the surface of the protrusion is slidably mounted with a test plate.
[0010] In an optional solution: five test boards are provided in the same experimental box, a handle is fixedly connected to the side of the test board, and a plurality of slots are opened on the surface of the test board, and the slots are used to place chips.
[0011] In an optional solution: the surface of the body is fixedly connected to a control screen, the card slot output end is electrically connected to a chip, and the card slot input end is electrically connected to an output end of the control screen.
[0012] In an optional solution: the card slot is a UFS test socket.
[0013] In an optional solution: a temperature controller and a humidity controller are fixedly connected to the upper surface of the inner wall of the experimental box, and the input ends of the temperature controller and the humidity controller are electrically connected to the output end of the control panel.
[0014] In an optional solution: a mounting groove is provided in the center of the door, and a vacuum glass is fixedly connected in the mounting groove.
[0015] Compared with the prior art, the beneficial effects of the present invention are as follows:
[0016] The utility model simultaneously provides a plurality of experimental boxes to carry out aging tests under different vector environments, thereby achieving the effect of obtaining test data in an all-round manner, thereby reducing the test cycle. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] Figure 1 It is a structural schematic diagram of the utility model.
[0018] Figure 2 It is a side structural schematic diagram of the utility model.
[0019] Figure 3 It is a schematic diagram of the structure of the utility model when viewed from above.
[0020] Figure 4 This is a schematic diagram of the inner structure of the box door of the present utility model.
[0021] Figure 5 It is a front view structural schematic diagram of the utility model.
[0022] Figure 6 It is a schematic diagram of the internal structure of the box door of the present utility model.
[0023] Figure 7 This is a schematic diagram of the test board structure of the utility model.
[0024] Notes on the figure numbers: 1. Box structure; 101. Body; 102. Support legs; 103. Control panel; 2. Experimental box; 201. Sealed box door; 202. Door handle; 203. Test board; 204. Card slot; 205. Handle; 206. Bump; 207. Temperature controller; 208. Humidity controller. DETAILED DESCRIPTION
[0025] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments.
[0026] Example 1
[0027] In one embodiment, Figure 1-Figure 7 As shown, a multi-channel memory chip test aging structure includes a box structure 1 and a test box 2. The box structure 1 includes a body 101. The bottom of the body 101 is fixedly connected to a support leg 102. The front of the body 101 is provided with a test box 2. The test box 2 is used to test the chip.
[0028] In one embodiment, Figure 1 As shown, the experimental box 2 is provided with at least three, and three can simultaneously detect data in different vector environments, thereby improving the detection efficiency;
[0029] In one embodiment, Figure 4 and Figure 5 As shown, the surface of the experimental box 2 is rotatably connected to the sealed box door 201, the surface of the sealed box door 201 is fixedly connected to the door handle 202, the inner wall of the experimental box 2 is fixedly connected to the protrusion 206, the surface of the protrusion 206 is slidably mounted with a test board 203, the surface of the test board 203 is placed with a chip for testing, and the test board 203 is slidably connected to the protrusion to facilitate the placement of the chip;
[0030] In one embodiment, Figure 7 As shown, five test boards 203 are provided in the same experimental box 2. A handle 205 is fixedly connected to the side of the test board 203. A plurality of card slots 204 are provided on the surface of the test board 203. The card slots 204 are used to place chips. The handle 205 can be provided to facilitate pulling out the test board 203. The plurality of card slots 204 can increase the number of tests, thereby improving the accuracy of the tests.
[0031] In one embodiment, Figure 5 As shown, the output end of the card slot 204 is electrically connected to the chip, the surface of the body 101 is fixedly connected to the control screen 103, the control screen 103 is used to control and monitor the test process, the input end of the card slot 204 is electrically connected to the output end of the control screen 103, and the test is started through the control screen 103. At this time, the chip in the card slot 204 is powered on and the test can be performed;
[0032] In one embodiment, Figure 7 As shown, the card slot 204 is a UFS test socket, which can provide a flexible connection method to ensure compatibility and versatility and meet the testing requirements of different types of chips;
[0033] In one embodiment, Figure 1As shown, a mounting groove is provided in the center of the sealed box door 201, and a vacuum glass is fixedly connected in the mounting groove. A vacuum glass is provided in the center of the sealed box door 201, which can facilitate the naked eye observation of the internal conditions of the experimental box 2 during the test, and facilitate subsequent recording.
[0034] Example 2
[0035] In one embodiment, Figure 6 As shown, the temperature controller 207 and the humidity controller 208 are fixedly connected to the upper surface of the inner wall of the test box 2. The temperature controller 207 is used to control and adjust the temperature of the test environment, and the humidity controller 208 is used to control the humidity of the test environment. The input ends of the temperature controller 207 and the humidity controller 208 are electrically connected to the output end of the control panel 103. By operating the control panel 103, the temperature controllers 207 and the humidity controllers 208 in different test boxes 2 are controlled, thereby adjusting different test environments to improve the test efficiency.
[0036] The above embodiment discloses a multi-channel memory chip test aging structure, wherein the chip to be tested is first installed in the card slot 204, and the test board 203 is pushed into the test box 2. At this time, the sealed box door 201 is closed, the control panel 103 is controlled, and the temperature controller 207 and the humidity controller 208 in each test box 2 are adjusted to make the test environment in each test box 2 different. At the same time, the chips under different environmental conditions are tested to improve work efficiency.
[0037] The above is only a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.
Claims
1. A multi-channel memory chip test aging structure, comprising a box structure (1), wherein the box structure (1) comprises a body (101), wherein the bottom end of the body (101) is fixedly connected to a support leg (102), wherein: The front of the body (101) is provided with an experimental box (2) for testing chips; The experimental box (2) is provided with at least three; the surface of the experimental box (2) is rotatably connected to the sealed box door (201); the surface of the sealed box door (201) is fixedly connected to the door handle (202); the inner wall of the experimental box (2) is fixedly connected to a protrusion (206); and a test plate (203) is slidably mounted on the surface of the protrusion (206); Five test boards (203) are provided in the same experimental box (2); a handle (205) is fixedly connected to the side of the test board (203); a plurality of card slots (204) are provided on the surface of the test board (203); the card slots (204) are used to place chips; a temperature controller (207) and a humidity controller (208) are fixedly connected to the upper surface of the inner wall of the experimental box (2); the input ends of the temperature controller (207) and the humidity controller (208) are electrically connected to the output end of the control panel (103).
2. The multi-channel memory chip test aging structure according to claim 1, characterized in that: The surface of the body (101) is fixedly connected to the control screen (103), the output end of the card slot (204) is electrically connected to the chip, and the input end of the card slot (204) is electrically connected to the output end of the control screen (103).
3. The multi-channel memory chip test aging structure according to claim 2, characterized in that: The card slot (204) is a UFS test socket.
4. The multi-channel memory chip test aging structure according to claim 1, characterized in that: A mounting groove is provided in the center of the sealed box door (201), and a vacuum glass is fixedly connected in the mounting groove.