Power MOS field effect transistor and semiconductor packaging structure
By adopting asymmetric gate Pad and rationally layout of polycrystalline gate Bus in silicon carbide device packages, the problem of large parasitic inductance in traditional packages is solved, and the switching performance and system power density of the device are improved.
Patent Information
- Application Number
- CN202323514978.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-22
- Publication Date
- 2024-12-31
- Estimated Expiration
- 2033-12-22
AI Technical Summary
There is a large parasitic inductance in the package structure of traditional silicon carbide devices, which causes the silicon carbide devices with fast switching speed to generate voltage overshoot and oscillation at extremely high di/dt, increasing the electromagnetic interference and loss of the device.
Using a gate Pad asymmetric structure, the length of the gate bonded leads is shortened by rationally layout of the multi-crystalline gate Bus, thereby reducing the parasitic inductance in the package. Specific measures include setting the main channel multi-crystal gate Bus and the gate pad region multi-crystal gate Bus, and electrically connecting it to the main channel multi-crystal gate Bus through the sub-channel multi-crystal gate Bus, optimizing the layout of the multi-crystal gate Bus. to reduce parasitic inductance.
It effectively reduces the package parasitic inductance, improves the switching performance of the device, reduces electromagnetic interference and losses, and improves the overall power density of the system.
Smart Images
Figure CN222281988U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of semiconductor devices, in particular to a semiconductor device of a power MOS field effect transistor, which is a silicon carbide MOS field effect transistor and a semiconductor packaging structure for reducing packaging parasitic inductance. Background Art
[0002] MOS field effect transistor, or metal oxide semiconductor field effect transistor, is a semiconductor device that works on the principle of field effect. Compared with ordinary bipolar transistors, MOS tubes have the advantages of high input impedance, low noise, large dynamic range, low power consumption, and easy integration. They are increasingly widely used in high-frequency power supply fields such as switching power supplies, ballasts, high-frequency induction heating, high-frequency inverter welding machines, and communication power supplies.
[0003] In the past 20 years, silicon carbide, as a wide bandgap power device, has attracted more and more attention. Compared with silicon, silicon carbide has many advantages, such as: wider bandgap width, which makes silicon carbide devices have lower leakage current and higher operating temperature, and improved radiation resistance; higher breakdown field strength, about 10 times that of silicon, so its devices can be designed with higher doping concentration and thinner epitaxial thickness, and lower on-resistance compared with silicon power devices of the same voltage level; higher electron saturation speed, so that the device can operate at a higher operating frequency; at the same time, the higher thermal conductivity of silicon carbide material also helps to improve the overall power density of the system. The high frequency, high voltage, high temperature resistance, low loss, fast switching speed and other characteristics of silicon carbide devices make the efficiency and power density of power electronic systems move towards a higher direction.
[0004] These excellent characteristics of silicon carbide devices can only be more perfectly displayed through packaging and circuit systems to achieve efficient and reliable connection of power and signals. Most of the commercial silicon carbide devices currently use the traditional packaging method of silicon devices. This method first solders the back of the chip to the substrate through solder, then leads the front electrode through metal bonding wires, and finally performs plastic sealing or glue pouring. Traditional packaging technology is mature, low-cost, and can be compatible with and replace the original silicon-based devices. However, due to the existence of long bonding wires, the parasitic inductance of this packaging structure is large. According to experience, the inductance value L of a bonding round lead with a length of l and a diameter of d is calculated by the following formula, L=2lⅹ[ln(4l / d)-0.75]nH, where l and d are both in cm. It can be seen from the formula that the longer the bonding wire, the greater the parasitic lead inductance of the package. For example Figure 1As shown, the chip adopts a gate pad symmetrical structure, in which the gate Pad 21 is equidistant from the upper and lower edges of the chip, and the parasitic inductance of the gate bonding wire is positively correlated with the length of the gate bonding wire, resulting in a problem of larger parasitic wire inductance.
[0005] Silicon carbide devices have small junction capacitance and low gate charge, so the switching speed is extremely fast, and the dv / dt and di / dt during the switching process are extremely high. Although the device loss is significantly lower, the parasitic inductance parameters in traditional packaging are large, which will produce large voltage overshoot and oscillation under extremely high di / dt, causing device voltage stress, increased loss and electromagnetic interference problems. Utility Model Content
[0006] The utility model provides a power MOS field effect transistor for reducing package parasitic inductance. The transistor adopts an asymmetric gate pad structure, which can reduce the length of the gate bonding wire, thereby reducing the package parasitic inductance. In order to solve the above technical problems, the utility model adopts the following technical solutions:
[0007] A power MOS field effect transistor comprises a drain pad, a source pad and a gate pad, and also comprises a polycrystalline gate Bus for electrically connecting the gate pad with the polycrystalline gate of each cell unit, wherein the polycrystalline gate Bus comprises:
[0008] A main channel polycrystalline gate Bus, used to electrically connect the polycrystalline gates of each cell unit; and
[0009] A gate pad region polycrystalline gate Bus is disposed around the gate pad and electrically connected to the gate pad and the surrounding polycrystalline gates, and the gate pad region polycrystalline gate Bus is electrically connected to the main channel polycrystalline gate Bus through a secondary channel polycrystalline gate Bus;
[0010] The length a from the farthest end of the polycrystalline gate around the main channel polycrystalline gate Bus to the main channel polycrystalline gate Bus and the length b1 from the farthest end of the polycrystalline gate in the gate pad region toward the active area boundary to the gate pad region polycrystalline gate Bus have the following relationship: a>b1.
[0011] There are many layouts of the polycrystalline gate Bus, one of which is that the main channel polycrystalline gate Bus extends through all polycrystalline gates, and the distance b2 from the farthest end of the polycrystalline gate of the gate pad region polycrystalline gate Bus toward the main channel polycrystalline gate Bus to the polycrystalline gate Bus of the gate pad region has the following relationship:
[0012] b2=a-b1-c
[0013] Wherein, c is the distance between the polycrystalline gate Bus in the gate pad region and the polycrystalline gate direction.
[0014] Alternatively, the distance b3 between the farthest end of the polycrystalline gate Bus of the gate pad region toward the polycrystalline gate Bus of the main channel and the polycrystalline gate Bus of the gate pad region has the following relationship:
[0015] b3<a
[0016] Wherein, c is the distance between the polycrystalline gate Bus in the gate pad region and the polycrystalline gate direction.
[0017] Preferably, the length b1 is 0.1a~0.9a.
[0018] The utility model also provides a semiconductor packaging structure, comprising:
[0019] A lead frame is provided with a plurality of module lead terminals for external electrical connection;
[0020] As for the power MOS field effect transistor mentioned above, its input end and output end are electrically connected to the module lead-out terminal through bonding wires respectively.
[0021] It can be seen from the above technical solutions that the utility model improves the switching performance of the device by reasonably laying out the polycrystalline gate Bus and adopting an asymmetric structure of the gate pad without causing a longer distance from the polycrystalline gate to the polycrystalline gate Bus. BRIEF DESCRIPTION OF THE DRAWINGS
[0022] Figure 1 It is a symmetrical structure of the gate pad in the prior art;
[0023] Figure 2 This is a schematic diagram of the structure of Embodiment 1 of the present utility model, showing the chip structure, but not showing the drain pad and source pad;
[0024] Figure 3 This is a schematic diagram of the structure of Embodiment 2 of the present utility model, showing the chip structure, but not showing the drain pad and source pad;
[0025] Figure 4 It is a schematic diagram of another form of asymmetric gate pad structure, showing the chip structure, but not showing the drain pad and source pad;
[0026] Figure 5 This is a schematic diagram of the chip packaging structure of the present utility model. DETAILED DESCRIPTION
[0027] A preferred embodiment of the present invention is described in detail below in conjunction with the accompanying drawings.
[0028] The power MOS field effect transistor of the utility model can be a silicon carbide MOS field effect transistor, which includes a drain pad, a source pad 22, a gate pad 21, a polycrystalline gate Bus 50 and a polycrystalline gate 60. The drain pad is arranged on the back of the chip, and its function is to provide a welding position for the chip, so that it is connected to the base of the lead frame through solder or conductive silver paste, and the base is electrically connected to the drain PIN pin. The source pad is arranged on the front of the chip, distributed on both sides of the polycrystalline gate Bus, and its function is to provide a welding position for the chip, so that it is electrically connected to the source PIN pin through a bonding wire. The gate pad is arranged on the front of the chip, and its function is to provide a welding position for the chip, so that it is electrically connected to the gate PIN pin through a bonding wire. The function of the polycrystalline gate is to control the opening and closing of the MOSFET cell channel, and the function of the polycrystalline gate Bus is to gather the signals of the polycrystalline gates of all cell structures in the active area. Figures 1 to 4 The metal layer and source pad are omitted, the polycrystalline gate Bus is also connected to the metal bus, and the gate pad is opened on the metal layer.
[0029] The function of the polycrystalline gate Bus 50 is to gather the polycrystalline gates 60 of all the cell structures in the active area. When a signal is input to the device gate, the signal is first introduced through the gate PIN pin, then introduced to the gate pad of the chip through the gate bonding wire, and finally transmitted to the polycrystalline gate 60 of each cell unit through the polycrystalline gate Bus 50, thereby controlling the switching state of the device.
[0030] like Figure 2 and 3 As shown, the polycrystalline gate Bus50 of the utility model includes a main channel polycrystalline gate Bus51 and a sub-channel polycrystalline gate Bus52, and the polycrystalline gate Bus will be formed into a gate pad area polycrystalline gate Bus53 around the gate pad21, wherein the main channel polycrystalline gate Bus is used to electrically connect the polycrystalline gates 60 of each cell unit, the gate pad area polycrystalline gate Bus53 is electrically connected to the gate pad21 and the surrounding polycrystalline gates, and the gate pad area polycrystalline gate Bus53 is electrically connected to the main channel polycrystalline gate Bus51 through the sub-channel polycrystalline gate Bus52.
[0031] For the sake of clear description, it is necessary to define the meaning of each distance in the figure below, where a is the length of the farthest end of the polycrystalline gate 60 around the main channel polycrystalline gate Bus51 from the main channel polycrystalline gate Bus, b is the distance from the farthest end of a single polycrystalline gate 60 to the gate bus21, b1 is the length of the farthest end of the polycrystalline gate of the gate pad region polycrystalline gate Bus53 toward the boundary of the active area from the polycrystalline gate Bus of the gate pad region, and b2 is the length of the farthest end of the polycrystalline gate of the gate pad region polycrystalline gate Bus53 toward the main channel polycrystalline gate Bus51 from the polycrystalline gate Bus of the gate pad region.
[0032] The gate pad 21 of the utility model adopts an asymmetric structure at the position of the chip. The gate pad is arranged closer to the position of the gate PIN pin, so that the length of the gate bonding wire formed is shortened and the corresponding parasitic inductance is reduced. While the asymmetric structure of the gate pad reduces the parasitic inductance, it also brings new problems. Figure 4 As shown, such an asymmetric gate pad structure will cause the distance b between the farthest end of a single polycrystalline gate 60 and the gate bus 21 to be greater than the distance a of the asymmetric gate pad structure. Since the polycrystalline gate 60 has resistance, when the distance a is relatively long, the parasitic resistance of the polycrystalline gate cannot be ignored. Therefore, the opening time of the cell unit corresponding to the distance b will lag behind the cell unit corresponding to the distance a, thereby affecting the switching performance of the device. Therefore, it is necessary to reasonably layout the polycrystalline gate Bus on the chip so that the asymmetric gate pad structure does not cause a longer distance from the polycrystalline gate to the polycrystalline gate Bus, thereby not affecting the switching performance of the device.
[0033] The utility model adopts two embodiments to solve the problem of too long gate bonding wire length by reasonably setting the secondary channel polycrystalline gate Bus, wherein the length a of the farthest end of the polycrystalline gate around the main channel polycrystalline gate Bus 51 from the main channel polycrystalline gate Bus and the length b1 of the farthest end of the polycrystalline gate of the gate pad area polycrystalline gate Bus 53 toward the active area boundary from the gate pad area polycrystalline gate Bus need to have the following relationship: a>b1. Preferably, the length b1 is 0.1a~0.9a.
[0034] Example 1
[0035] like Figure 2 As shown, the main channel polycrystalline gate Bus 51 extends through all polycrystalline gates 60, and the distance b2 between the farthest end of the polycrystalline gate of the gate pad region polycrystalline gate Bus 53 toward the main channel polycrystalline gate Bus and the polycrystalline gate Bus of the gate pad region has the following relationship: b2=a-b1-c, wherein c is the distance of the gate pad region polycrystalline gate Bus in the direction of the polycrystalline gate.
[0036] Such a polycrystalline gate Bus layout makes the polycrystalline gate length around the polycrystalline gate Bus in the gate pad region shorter, which can reduce the parasitic inductance of the gate bonding wire.
[0037] Example 2
[0038] like Figure 3 As shown, the main channel polycrystalline gate Bus51 does not directly extend through all the polycrystalline gates 60, but is terminated at the corresponding area of the gate pad21, the upper edge of the main channel polycrystalline gate Bus51 is electrically connected to the gate pad area polycrystalline gate Bus53 through the sub-channel polycrystalline gate Bus52, and the lower edge of the main channel polycrystalline gate Bus51 is connected to another L-shaped bent sub-channel polycrystalline gate Bus54.
[0039] The distance b3 between the farthest end of the polycrystalline gate Bus53 in the gate pad region and the polycrystalline gate Bus51 in the main channel and the polycrystalline gate Bus51 is as follows:
[0040] b3<a
[0041] Wherein, c is the distance between the polycrystalline gate Bus in the gate pad region and the polycrystalline gate direction.
[0042] Such a polycrystalline gate bus layout also shortens the length of the polycrystalline gate around the polycrystalline gate bus in the gate pad region, thereby reducing the parasitic inductance of the gate bonding wire.
[0043] like Figure 5 As shown, the utility model also provides a semiconductor packaging structure, including:
[0044] The lead frame 11 is provided with a plurality of module lead terminals 12 for electrical connection with the outside;
[0045] As for the above-mentioned power MOS field effect transistor, its input end and output end are electrically connected to the module lead-out terminal 12 through the bonding wire 13 respectively.
[0046] The module lead-out terminal 12 may be a package PIN pin, including a drain PIN pin, a source PIN pin, a Kelvin source PIN pin, and a gate PIN pin. Figure 5 The bonding wires 13 in the embodiment include a gate bonding wire, a Kelvin source bonding wire and a source bonding wire.
[0047] The above-described embodiments are merely descriptions of preferred embodiments of the present invention, and are not intended to limit the scope of the present invention. Without departing from the design spirit of the present invention, various modifications and improvements made to the technical solutions of the present invention by ordinary technicians in this field should all fall within the protection scope determined by the claims of the present invention.
Claims
1. A power MOS field effect transistor, comprising a drain pad, a source pad and a gate pad, characterized in that: Also included is a polycrystalline gate Bus for electrically connecting the gate pad to the polycrystalline gate of each cell unit, the polycrystalline gate Bus comprising: A main channel polycrystalline gate Bus, used to electrically connect the polycrystalline gates of each cell unit; and A gate pad region polycrystalline gate Bus is disposed around the gate pad and electrically connected to the gate pad and the surrounding polycrystalline gates, and the gate pad region polycrystalline gate Bus is electrically connected to the main channel polycrystalline gate Bus through a secondary channel polycrystalline gate Bus; The length a from the farthest end of the polycrystalline gate around the main channel polycrystalline gate Bus to the main channel polycrystalline gate Bus and the length b1 from the farthest end of the polycrystalline gate in the gate pad region toward the active area boundary to the gate pad region polycrystalline gate Bus have the following relationship: a>b1.
2. The power MOS field effect transistor according to claim 1, characterized in that: The main channel polycrystalline gate Bus extends through all polycrystalline gates, and the distance b2 from the farthest end of the polycrystalline gate Bus of the gate pad region toward the polycrystalline gate Bus of the main channel polycrystalline gate Bus to the polycrystalline gate Bus of the gate pad region has the following relationship: b2=a-b1-c Wherein, c is the distance between the polycrystalline gate Bus in the gate pad region and the polycrystalline gate direction.
3. The power MOS field effect transistor according to claim 1, characterized in that: The distance b3 between the farthest end of the polycrystalline gate Bus of the gate pad region toward the polycrystalline gate Bus of the main channel and the polycrystalline gate Bus of the gate pad region has the following relationship: b3<a Wherein, c is the distance between the polycrystalline gate Bus in the gate pad region and the polycrystalline gate direction.
4. The power MOS field effect transistor according to claim 1, characterized in that: The length b1 is 0.1a~0.9a.
5. The power MOS field effect transistor according to any one of claims 1 to 4, characterized in that: The power MOS field effect transistor is a silicon carbide MOS field effect transistor.
6. A semiconductor packaging structure, characterized in that: include: A lead frame is provided with a plurality of module lead terminals for external electrical connection; The power MOS field effect transistor according to any one of claims 1 to 5, wherein the input end and the output end are electrically connected to the module lead-out terminal through bonding wires respectively.