Low-dropout linear voltage stabilizing source circuit and low-dropout linear voltage stabilizer

Abstract

The utility model discloses a low-dropout linear voltage stabilizing source circuit which comprises two operational amplifiers, four resistors, six NMOS (N-channel Metal Oxide Semiconductor) tubes and eleven PMOS (P-channel Metal Oxide Semiconductor) tubes. On the basis of a traditional circuit, a shunt feedback circuit is added to realize current buffer compensation, and can be matched with the change of load current to inject a certain proportion of output current into a first amplification path so as to change the size of a second pole of a low-dropout linear voltage stabilization source circuit, and a secondary dominant pole is adjusted to be enlarged while the output current and the output pole are enlarged; according to the low-dropout linear voltage stabilization source circuit, the low-dropout linear voltage stabilization source circuit is designed to ensure that only one pole is contained in a loop unit gain bandwidth, a secondary dominant pole is large enough, stable phase margin is achieved in the full range of load current of the low-dropout linear voltage stabilization source circuit, and stability is achieved under the condition that no low-frequency zero point is used. Meanwhile, an overcurrent protection circuit is added, so that a feedback loop can be cut off when load current is too large, and short-circuit current caused by the fact that output is mistakenly connected to a power supply and the ground is prevented.

Description

Technical Field

[0001] The utility model belongs to the field of analog integrated circuits and relates to a low-voltage difference linear voltage regulator source circuit and a low-voltage difference linear voltage regulator. Background Art

[0002] In the field of power management, low dropout linear regulators are widely used in application scenarios requiring small size, low power ripple, and high transient response.

[0003] The output of a traditional low-dropout linear regulator usually contains a microfarad-level load capacitor to provide the transient large current of the power supply device of the low-dropout linear regulator, thereby achieving the function of voltage regulation. However, the output pole caused by the large load capacitor and the internal pole of the low-dropout linear regulator will cause stability problems, especially the output pole will change with the change of the output load current. Utility Model Content

[0004] The purpose of the utility model is to overcome the above-mentioned shortcomings of the prior art and provide a low voltage drop linear voltage regulator circuit and a low voltage drop linear voltage regulator.

[0005] In order to achieve the above purpose, the utility model adopts the following technical solutions:

[0006] In a first aspect, the utility model provides a low voltage difference linear voltage regulator circuit, including a first operational amplifier OTA1, a second operational amplifier OTA2, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a first NMOS tube NM1, a second NMOS tube NM2, a third NMOS tube NM3, a fourth NMOS tube NM4, a fifth NMOS tube NM5, a sixth NMOS tube NM6, a first PMOS tube PM1, a second PMOS tube PM2, a third PMOS tube PM3, a fourth PMOS tube PM4, a fifth PMOS tube PM5, a sixth PMOS tube PM6, a seventh PMOS tube PM7, an eighth PMOS tube PM8, a ninth PMOS tube PM9, a tenth PMOS tube PM10 and an eleventh PMOS tube PM11;

[0007] The negative terminal of the first operational amplifier OTA1 is connected to the middle node where the third resistor R3 and the fourth resistor R4 are connected, and the output is connected to the gate terminal of the second NMOS transistor NM2; the negative terminal of the second operational amplifier OTA2 is connected to one end of the second resistor R2, and the output is connected to the gate terminal of the first NMOS transistor NM1;

[0008] The drain terminal of the first NMOS tube NM1 is connected to the source terminal of the second NMOS tube NM2; the drain terminal of the second NMOS tube NM2 is connected to both the drain terminal and the gate terminal of the first PMOS tube PM1; the gate terminal of the third NMOS tube NM3 is connected to the gate terminal of the fourth NMOS tube NM4; the gate terminal and the drain terminal of the fourth NMOS tube NM4 are connected;

[0009] The drain terminal and gate terminal of the first PMOS tube PM1 are connected, and the source terminal is connected to one end of the first resistor R1; the drain terminal of the second PMOS tube PM2 and the third PMOS tube PM3 are both connected to the other end of the first resistor R1; the gate terminal of the third PMOS tube PM3 is connected to the gate terminal of the fourth PMOS tube PM4; the gate terminal of the fourth PMOS tube PM4 is connected to the gate terminal of the fifth PMOS tube PM5, and the drain terminal is connected to the other end of the second resistor R2; the drain terminal of the fifth PMOS tube PM5 is connected to the gate terminal of the fifth PMOS tube PM5 and the drain terminal of the third NMOS tube NM3; the drain terminal of the sixth PMOS tube PM6 is connected to the source terminal of the ninth PMOS tube PM9; the gate terminal of the seventh PMOS tube PM7 is connected to the drain terminal of the first PMOS tube PM1, and the drain terminal is connected to the other end of the second resistor R2. The gate terminal of the eighth PMOS tube PM8 is connected to the gate terminal of the seventh PMOS tube PM7, and the drain terminal is connected to the source terminal of the eleventh PMOS tube PM11 and the other end of the third resistor R3; the gate terminal of the ninth PMOS tube PM9 is connected to the drain terminal of the eleventh PMOS tube PM11, the drain terminal is connected to the drain terminal of the fourth NMOS tube NM4, and the source terminal is connected to the source terminal of the tenth PMOS tube PM10; the drain terminal of the tenth PMOS tube PM10 is connected to the gate terminal of the tenth PMOS tube PM10 and the drain terminal of the fifth NMOS tube NM5; the gate terminal of the eleventh PMOS tube PM11 is connected to the gate terminal of the tenth PMOS tube PM10, and the drain terminal is connected to the drain terminal of the sixth NMOS tube NM6.

[0010] Optionally, the width-to-length ratio of the third NMOS transistor NM3 and the fourth NMOS transistor NM4 is 1:1.

[0011] Optionally, the width-to-length ratio of the third PMOS tube PM3 , the fourth PMOS tube PM4 , and the fifth PMOS tube PM5 is 2:1:1, and the width-to-length ratio of the seventh PMOS tube PM7 and the eighth PMOS tube PM8 is 1:100.

[0012] Optionally, the positive terminal of the second operational amplifier OTA2 is configured as an input signal input terminal for inputting an input signal VREF.

[0013] Optionally, source ends of the second PMOS tube PM2, the third PMOS tube PM3, the fourth PMOS tube PM4, the fifth PMOS tube PM5, the sixth PMOS tube PM6, the seventh PMOS tube PM7 and the eighth PMOS tube PM8 are all configured to be power supply connecting terminals connected to the power supply terminal VDD.

[0014] Optionally, the other end of the second resistor R2 and source ends of the first NMOS transistor NM1, the second NMOS transistor NM2, the third NMOS transistor NM3, the fourth NMOS transistor NM4, the fifth NMOS transistor NM5 and the sixth NMOS transistor NM6 are all provided with grounding terminals for grounding.

[0015] Optionally, the gate terminal of the second PMOS transistor PM2, the gate terminal of the sixth PMOS transistor PM6, the gate terminals of the fifth NMOS transistor NM5 and the sixth NMOS transistor NM6 are all configured as bias voltage terminals for inputting a bias voltage NBIAS.

[0016] A second aspect of the utility model provides a low voltage dropout linear regulator, comprising the above-mentioned low voltage dropout linear voltage regulator source circuit.

[0017] Compared with the prior art, the utility model has the following beneficial effects:

[0018] The utility model discloses a low-voltage-difference linear voltage-stabilizing source circuit, which realizes current buffer compensation through a shunt feedback circuit formed by a third PMOS tube PM3, and can cooperate with the change of load current to inject a certain proportion of output current into a first amplification path formed by a first operational amplifier OTA1, a second operational amplifier OTA2, a first NMOS tube NM1, a second NMOS tube NM2, a first PMOS tube PM1, a second PMOS tube PM2 and a third PMOS tube PM3, so as to change the size of the second pole of the low-voltage-difference linear voltage-stabilizing source circuit, and adjust the secondary main pole to be larger while the output current is increased and the output pole is increased, so as to ensure that only one pole is included in the loop unit gain bandwidth, and the secondary main pole is large enough, so as to realize a stable phase margin in the full range of the load current of the low-voltage-difference linear voltage-stabilizing source circuit, and realize stability without using any low-frequency zero point. At the same time, an overcurrent protection circuit is formed based on the fourth PMOS tube PM4, the second resistor R2, the second operational amplifier OTA2 and the first NMOS tube NM1, so that when the load current is too large, the feedback loop can be cut off by turning off the first NMOS tube NM1 to prevent the output from being mistakenly connected to the power supply and the ground and causing a short-circuit current. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 The utility model is a circuit topology diagram of a low voltage difference linear voltage regulator. DETAILED DESCRIPTION

[0020] In order to enable those skilled in the art to better understand the solution of the utility model, the technical solution in the embodiment of the utility model will be clearly and completely described below in conjunction with the drawings in the embodiment of the utility model. Obviously, the described embodiment is only a part of the embodiment of the utility model, not all of the embodiments. Based on the embodiment of the utility model, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the utility model.

[0021] It should be noted that the terms "first", "second", etc. in the specification and claims of the utility model and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the utility model described here can be implemented in an order other than those illustrated or described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0022] The utility model is further described in detail below with reference to the accompanying drawings:

[0023] See also Figure 1 In one embodiment of the utility model, a low voltage difference linear voltage regulator circuit is provided, including a first operational amplifier OTA1, a second operational amplifier OTA2, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a first NMOS tube NM1, a second NMOS tube NM2, a third NMOS tube NM3, a fourth NMOS tube NM4, a fifth NMOS tube NM5, a sixth NMOS tube NM6, a first PMOS tube PM1, a second PMOS tube PM2, a third PMOS tube PM3, a fourth PMOS tube PM4, a fifth PMOS tube PM5, a sixth PMOS tube PM6, a seventh PMOS tube PM7, an eighth PMOS tube PM8, a ninth PMOS tube PM9, a tenth PMOS tube PM10 and an eleventh PMOS tube PM11.

[0024] Among them, the negative terminal of the first operational amplifier OTA1 is connected to the middle node where the third resistor R3 and the fourth resistor R4 are connected, and the output is connected to the gate terminal of the second NMOS tube NM2; the negative terminal of the second operational amplifier OTA2 is connected to one end of the second resistor R2, and the output is connected to the gate terminal of the first NMOS tube NM1.

[0025] The drain terminal of the first NMOS tube NM1 is connected to the source terminal of the second NMOS tube NM2; the drain terminal of the second NMOS tube NM2 is connected to both the drain terminal and the gate terminal of the first PMOS tube PM1; the gate terminal of the third NMOS tube NM3 is connected to the gate terminal of the fourth NMOS tube NM4; the gate terminal and the drain terminal of the fourth NMOS tube NM4 are connected.

[0026] The drain terminal and gate terminal of the first PMOS tube PM1 are connected, and the source terminal is connected to one end of the first resistor R1; the drain terminal of the second PMOS tube PM2 and the third PMOS tube PM3 are both connected to the other end of the first resistor R1; the gate terminal of the third PMOS tube PM3 is connected to the gate terminal of the fourth PMOS tube PM4; the gate terminal of the fourth PMOS tube PM4 is connected to the gate terminal of the fifth PMOS tube PM5, and the drain terminal is connected to the other end of the second resistor R2; the drain terminal of the fifth PMOS tube PM5 is connected to the gate terminal of the fifth PMOS tube PM5 and the drain terminal of the third NMOS tube NM3; the drain terminal of the sixth PMOS tube PM6 is connected to the source terminal of the ninth PMOS tube PM9; the gate terminal of the seventh PMOS tube PM7 is connected to the drain terminal of the first PMOS tube PM1, and the drain terminal is connected to the other end of the second resistor R2. The gate terminal of the eighth PMOS tube PM8 is connected to the gate terminal of the seventh PMOS tube PM7, and the drain terminal is connected to the source terminal of the eleventh PMOS tube PM11 and the other end of the third resistor R3; the gate terminal of the ninth PMOS tube PM9 is connected to the drain terminal of the eleventh PMOS tube PM11, the drain terminal is connected to the drain terminal of the fourth NMOS tube NM4, and the source terminal is connected to the source terminal of the tenth PMOS tube PM10; the drain terminal of the tenth PMOS tube PM10 is connected to the gate terminal of the tenth PMOS tube PM10 and the drain terminal of the fifth NMOS tube NM5; the gate terminal of the eleventh PMOS tube PM11 is connected to the gate terminal of the tenth PMOS tube PM10, and the drain terminal is connected to the drain terminal of the sixth NMOS tube NM6.

[0027] When the utility model low voltage difference linear voltage regulator circuit is used, one end of the output capacitance load Cload is connected to the drain of the eighth PMOS tube and the source of the eleventh PMOS tube, and the other end is connected to the ground; one end of the load current Iload is connected to the drain of the eighth PMOS tube and the source of the eleventh PMOS tube, and the other end is connected to the ground. Iout is the current flowing through the eighth PMOS tube, which is approximately equal to the load current Iload.

[0028] In a possible implementation manner, the width-to-length ratio of the third NMOS tube NM3 and the fourth NMOS tube NM4 is 1:1, the width-to-length ratio of the third PMOS tube PM3, the fourth PMOS tube PM4 and the fifth PMOS tube PM5 is 2:1:1, and the width-to-length ratio of the seventh PMOS tube PM7 and the eighth PMOS tube PM8 is 1:100.

[0029] In a possible implementation manner, the positive terminal of the second operational amplifier OTA2 is configured as an input signal input terminal for inputting an input signal VREF.

[0030] Source ends of the second PMOS transistor PM2 , the third PMOS transistor PM3 , the fourth PMOS transistor PM4 , the fifth PMOS transistor PM5 , the sixth PMOS transistor PM6 , the seventh PMOS transistor PM7 and the eighth PMOS transistor PM8 are all arranged to be connected to a power supply terminal connecting terminal of the power supply terminal VDD.

[0031] The other end of the second resistor R2 and source ends of the first NMOS transistor NM1 , the second NMOS transistor NM2 , the third NMOS transistor NM3 , the fourth NMOS transistor NM4 , the fifth NMOS transistor NM5 and the sixth NMOS transistor NM6 are all provided with grounding terminals for grounding.

[0032] The gate end of the second PMOS transistor PM2 , the gate end of the sixth PMOS transistor PM6 , the gate end of the fifth NMOS transistor NM5 and the gate end of the sixth NMOS transistor NM6 are all configured as bias voltage terminals for inputting a bias voltage NBIAS.

[0033] When the utility model low voltage difference linear voltage stabilizing source circuit is used, the input signal input terminal is connected to the input signal VREF, the power supply terminal is connected to the power supply, the ground terminal is grounded, and the bias voltage terminal is connected to the bias voltage.

[0034] The third PMOS transistor PM3 constitutes a shunt feedback circuit, the first operational amplifier OTA1, the second operational amplifier OTA2, the first NMOS transistor NM1, the second NMOS transistor NM2, the first PMOS transistor PM1, the second PMOS transistor PM2 and the third PMOS transistor PM3 constitute a first amplification path, the fourth PMOS transistor PM4, the second resistor R2, the second operational amplifier OTA2 and the first NMOS transistor NM1 constitute an overcurrent protection circuit, and the eighth PMOS transistor PM8, the eleventh PMOS transistor PM11 and the sixth NMOS transistor NM6 constitute a second amplification path.

[0035] The working process of the utility model low voltage difference linear voltage regulator circuit is as follows:

[0036] The basic working process of the low-voltage difference linear voltage regulator circuit of the utility model is: a first amplification path composed of a first operational amplifier OTA1, a second operational amplifier OTA2, a first NMOS tube NM1, a second NMOS tube NM2, a first PMOS tube PM1, a second PMOS tube PM2 and a third PMOS tube PM3, and a second amplification path composed of an eighth PMOS tube PM8, an eleventh PMOS tube PM11 and a sixth NMOS tube NM6, together form an amplifier whose input is the positive terminal of the first operational amplifier OTA1 and whose output is the output terminal Vout, and whose two ends are connected to a feedback network composed of a third resistor R3 and a fourth resistor R4 connected in series, forming an amplifier with a ratio of (R3+R4) / R4, and amplifying the Vref signal to the output terminal Vout through the ratio.

[0037] The innovation of the low-voltage-difference linear voltage-stabilizing source circuit of the utility model is that current buffer compensation is realized by a shunt feedback circuit formed by a third PMOS tube PM3, and a certain proportion of the output current can be injected into a first amplification path formed by a first operational amplifier OTA1, a second operational amplifier OTA2, a first NMOS tube NM1, a second NMOS tube NM2, a first PMOS tube PM1, a second PMOS tube PM2 and a third PMOS tube PM3 in coordination with changes in load current, so as to change the size of the second pole of the low-voltage-difference linear voltage-stabilizing source circuit, and adjust the secondary main pole to be larger while the output current increases and the output pole increases, so as to ensure that only one pole is included in the loop unit gain bandwidth, and the secondary main pole is large enough, so as to realize a stable phase margin in the full range of the load current of the low-voltage-difference linear voltage-stabilizing source circuit, and realize stability without using any low-frequency zero point. At the same time, an overcurrent protection circuit is formed based on the fourth PMOS tube PM4, the second resistor R2, the second operational amplifier OTA2 and the first NMOS tube NM1. When the load current is too large, the first NMOS tube NM1 can be turned off to cut off the feedback loop to prevent the output from being mistakenly connected to the power supply and the ground and causing a short-circuit current.

[0038] In yet another embodiment of the utility model, a low voltage dropout linear regulator is provided. The low voltage dropout linear regulator includes the above-mentioned low voltage dropout linear voltage stabilization source circuit.

[0039] Specifically, the low voltage dropout linear regulator can be obtained by packaging the low voltage dropout linear regulator source circuit described above in combination with some peripheral circuits.

[0040] The above content is only for explaining the technical idea of ​​the utility model and cannot be used to limit the protection scope of the utility model. Any changes made on the basis of the technical solution in accordance with the technical idea proposed by the utility model shall fall within the protection scope of the claims of the utility model.

Claims

1. A low voltage drop linear voltage regulator circuit, characterized in that: Including a first operational amplifier OTA1, a second operational amplifier OTA2, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a first NMOS tube NM1, a second NMOS tube NM2, a third NMOS tube NM3, a fourth NMOS tube NM4, a fifth NMOS tube NM5, a sixth NMOS tube NM6, a first PMOS tube PM1, a second PMOS tube PM2, a third PMOS tube PM3, a fourth PMOS tube PM4, a fifth PMOS tube PM5, a sixth PMOS tube PM6, a seventh PMOS tube PM7, an eighth PMOS tube PM8, a ninth PMOS tube PM9, a tenth PMOS tube PM10 and an eleventh PMOS tube PM11; The negative terminal of the first operational amplifier OTA1 is connected to the middle node where the third resistor R3 and the fourth resistor R4 are connected, and the output is connected to the gate terminal of the second NMOS transistor NM2; the negative terminal of the second operational amplifier OTA2 is connected to one end of the second resistor R2, and the output is connected to the gate terminal of the first NMOS transistor NM1; The drain terminal of the first NMOS tube NM1 is connected to the source terminal of the second NMOS tube NM2; the drain terminal of the second NMOS tube NM2 is connected to both the drain terminal and the gate terminal of the first PMOS tube PM1; the gate terminal of the third NMOS tube NM3 is connected to the gate terminal of the fourth NMOS tube NM4; the gate terminal and the drain terminal of the fourth NMOS tube NM4 are connected; The drain terminal and gate terminal of the first PMOS tube PM1 are connected, and the source terminal is connected to one end of the first resistor R1; the drain terminal of the second PMOS tube PM2 and the third PMOS tube PM3 are both connected to the other end of the first resistor R1; the gate terminal of the third PMOS tube PM3 is connected to the gate terminal of the fourth PMOS tube PM4; the gate terminal of the fourth PMOS tube PM4 is connected to the gate terminal of the fifth PMOS tube PM5, and the drain terminal is connected to the other end of the second resistor R2; the drain terminal of the fifth PMOS tube PM5 is connected to the gate terminal of the fifth PMOS tube PM5 and the drain terminal of the third NMOS tube NM3; the drain terminal of the sixth PMOS tube PM6 is connected to the source terminal of the ninth PMOS tube PM9; the gate terminal of the seventh PMOS tube PM7 is connected to the drain terminal of the first PMOS tube PM1, and the drain terminal is connected to the other end of the second resistor R2. The gate terminal of the eighth PMOS tube PM8 is connected to the gate terminal of the seventh PMOS tube PM7, and the drain terminal is connected to the source terminal of the eleventh PMOS tube PM11 and the other end of the third resistor R3; the gate terminal of the ninth PMOS tube PM9 is connected to the drain terminal of the eleventh PMOS tube PM11, the drain terminal is connected to the drain terminal of the fourth NMOS tube NM4, and the source terminal is connected to the source terminal of the tenth PMOS tube PM10; the drain terminal of the tenth PMOS tube PM10 is connected to the gate terminal of the tenth PMOS tube PM10 and the drain terminal of the fifth NMOS tube NM5; the gate terminal of the eleventh PMOS tube PM11 is connected to the gate terminal of the tenth PMOS tube PM10, and the drain terminal is connected to the drain terminal of the sixth NMOS tube NM6.

2. The low voltage drop linear voltage regulator circuit according to claim 1, characterized in that: The width-to-length ratio of the third NMOS transistor NM3 and the fourth NMOS transistor NM4 is 1:

1.

3. The low voltage difference linear voltage regulator circuit according to claim 2, characterized in that: The width-to-length ratio of the third PMOS tube PM3 , the fourth PMOS tube PM4 and the fifth PMOS tube PM5 is 2:1:1, and the width-to-length ratio of the seventh PMOS tube PM7 and the eighth PMOS tube PM8 is 1:

100.

4. The low voltage drop linear voltage regulator circuit according to claim 1, characterized in that: The positive terminal of the second operational amplifier OTA2 is configured as an input signal input terminal for inputting an input signal VREF.

5. The low voltage drop linear voltage regulator circuit according to claim 1, characterized in that: Source ends of the second PMOS transistor PM2 , the third PMOS transistor PM3 , the fourth PMOS transistor PM4 , the fifth PMOS transistor PM5 , the sixth PMOS transistor PM6 , the seventh PMOS transistor PM7 and the eighth PMOS transistor PM8 are all arranged to be connected to a power supply terminal connecting terminal of the power supply terminal VDD.

6. The low voltage drop linear voltage regulator circuit according to claim 1, characterized in that: The other end of the second resistor R2 and source ends of the first NMOS transistor NM1 , the second NMOS transistor NM2 , the third NMOS transistor NM3 , the fourth NMOS transistor NM4 , the fifth NMOS transistor NM5 and the sixth NMOS transistor NM6 are all provided with grounding terminals for grounding.

7. The low voltage drop linear voltage regulator circuit according to claim 1, characterized in that: The gate end of the second PMOS transistor PM2 , the gate end of the sixth PMOS transistor PM6 , the gate end of the fifth NMOS transistor NM5 and the gate end of the sixth NMOS transistor NM6 are all configured as bias voltage terminals for inputting a bias voltage NBIAS.

8. A low voltage dropout linear regulator, characterized in that: A low voltage difference linear voltage regulator source circuit comprising any one of claims 1 to 7.

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