Single photon detector

Abstract

The utility model discloses a single-photon detector, which comprises a controller, a bias voltage generating circuit, a refrigeration temperature control circuit, a gating voltage generating circuit, an avalanche signal extraction circuit and an avalanche photodiode (APD) refrigeration box, and is characterized in that one end of the bias voltage generating circuit, one end of the gating voltage generating circuit and one end of the avalanche signal extraction circuit are connected to the controller; one end of the refrigeration temperature control circuit is connected to a TEC of the APD refrigeration box, the other end of the refrigeration temperature control circuit is connected to the controller, the other end of the avalanche signal extraction circuit is connected to an anode of an APD in the APD refrigeration box through an alternating current coupling capacitor C2, the anode of the APD is grounded through a sampling resistor R2, the other end of the bias voltage generation circuit is connected to a cathode of the APD through a resistor R1, and the APD refrigeration box is connected to the APD refrigeration box. And the other end of the gating voltage generation circuit is connected to the cathode of the APD through an alternating current coupling capacitor C1. According to the technical scheme of the utility model, the passive quenching of the free operation working mode is realized, the dead time processing circuit is simplified, and the noise level of the detector is reduced.

Description

Technical Field

[0001] The utility model relates to the field of quantum communication, and more specifically, to a single photon detector. Background Art

[0002] Single-photon detectors are ultra-sensitive detectors that reach the limit of weak light detection. They can capture and convert light energy at the level of a single photon and are widely used in "high-precision" scientific and technological fields. Single-photon detectors are not only key components of quantum communication systems, but also key components of systems in the fields of quantum measurement, laser radar, fluorescence lifetime detection, space exploration, etc.

[0003] Current single-photon detectors mainly include superconducting detectors, frequency up-conversion detectors, and semiconductor avalanche diode detectors. The first two types of detectors are large in size, high in cost, and not very practical; semiconductor avalanche diode detectors are small in size and low in cost, but they have high noise and cannot be used directly, so corresponding measures need to be taken to reduce the noise level.

[0004] The principle of single-photon detection by avalanche photodiode (APD) is as follows: APD works in Geiger mode to obtain sufficiently high gain. When a photon is detected, an avalanche current will be generated in the APD and continue spontaneously. Being in avalanche state for a long time will affect the service life and stability of the APD. Therefore, after triggering an avalanche, it is necessary to actively or passively reduce the reverse bias voltage of the APD to below the avalanche voltage to exit the Geiger mode to quench the avalanche current. The detection efficiency, noise (dark counts and afterpulses), and count rate of single-photon detectors based on APDs are mutually constrained. Prolonging the APD avalanche duration or increasing the reverse bias voltage can improve the detection efficiency, but it will increase the dark counts and afterpulses; lowering the cooling temperature will reduce the dark counts, but it will increase the afterpulses; increasing the dead time length can suppress the probability of afterpulses, but it will reduce the count rate. Therefore, if it is based on different application requirements and scenario requirements, maintaining the highest possible detection efficiency and suppressing the avalanche noise of the APD is an important research and development direction.

[0005] Patent document with publication number CN101650227A discloses a gigahertz sinusoidal gated low-pass filtered infrared single-photon detector, and provides a universal circuit composition, in which a sinusoidal gated power source outputs a sinusoidal wave with a frequency of gigahertz (GHz) as a gating signal of an indium gallium arsenide indium phosphide avalanche photodiode circuit, and a low-pass filter is used to low-pass filter the spike noise caused by the differential effect of the junction capacitance, for GHz high-speed infrared single-photon detection. However, there is no amplitude adjustment or closed-loop stabilization function for the sinusoidal gated signal, and the continuous stability of the detection efficiency cannot be guaranteed. The gated signal cannot be revoked, and the bias voltage is generated using a high-precision programmable power supply with an output range of only 40-50V, which does not exceed the reverse breakdown voltage of the APD. Therefore, the single-photon detector can only operate in a gated detection working mode (also called a gated mode).

[0006] Patent document with publication number CN113405677A discloses a high-speed sinusoidally gated single-photon detector, including a dual-sine gate, dual-APD tube detection circuit and a reference circuit. A self-differential cancellation scheme is used to eliminate the noise signal and carrier generated by the detection circuit, so that the high-speed sinusoidally gated single-photon detector can extract avalanche pulse electrical signals from the noise signal generated by the detection circuit. However, the dual APD tube circuit is relatively expensive and is not suitable for application scenarios with strict cost requirements.

[0007] The patent document with publication number CN115452145A discloses a test device for a single-photon detector, which realizes the test calibration switching process between the gated mode and the free-running mode, but requires auxiliary means such as a switch, a bias device, and an adjustable resistor to realize the switching between the two modes. Since the switching circuit has circuit parasitic parameters (such as impedance mismatch and other problems) that have a great impact on the high-speed circuit, it is not suitable for high-speed detectors above GHz. In addition, the use of an adjustable resistor to adjust the APD bias voltage has the problem of low automation, which is not suitable for product-level applications.

[0008] Currently, related technologies generally only optimize part of the performance of the detector, without considering the mutual constraints between different performances of the detector, and without providing a universal circuit composition. Utility Model Content

[0009] The technical problem to be solved by the utility model is how to provide a single photon detector taking into account the mutual restriction between different performances of the detector.

[0010] The utility model solves the above technical problems through the following technical means: a single-photon detector, including a controller, a bias voltage generating circuit, a refrigeration temperature control circuit, a gate voltage generating circuit, and an APD refrigeration box, wherein one end of the refrigeration temperature control circuit is connected to the TEC of the APD refrigeration box, and the other end is connected to the controller, and the single-photon detector also includes an avalanche signal extraction circuit, wherein one end of the bias voltage generating circuit, the gate voltage generating circuit and the avalanche signal extraction circuit are connected to the controller, and the other end of the avalanche signal extraction circuit is connected to the anode of the APD in the APD refrigeration box through an AC coupling capacitor C2, and the anode of the APD is grounded through a sampling resistor R2, the other end of the bias voltage generating circuit is connected to the cathode of the APD through a resistor R1, and the other end of the gate voltage generating circuit is connected to the cathode of the APD through an AC coupling capacitor C1.

[0011] As a further optimized technical solution, the series resistor R1 has a resistance of 1 kΩ, the sampling resistor R2 has a resistance of 50 Ω, and the capacitance values ​​of the AC coupling capacitors C1 and C2 are both 100 nF.

[0012] As a further optimized technical solution, the bias voltage generating circuit includes a first digital-to-analog converter DAC1 and a boost converter, wherein the input end of the first digital-to-analog converter DAC1 is connected to the controller, and the output end is connected to the boost converter, and one output end of the boost converter serves as the output end of the bias voltage generating circuit.

[0013] As a further optimized technical solution, the bias voltage generating circuit also includes a first operational amplifier and a first analog-to-digital converter ADC1. The other output end of the boost converter is connected to the controller through the first operational amplifier and the first analog-to-digital converter ADC1 in sequence, and the output end of the boost converter is connected to the first operational amplifier.

[0014] As a further optimized technical solution, the refrigeration temperature control circuit includes a switching power supply, a second digital-to-analog converter DAC2, a second analog-to-digital converter ADC2 and a second operational amplifier, wherein the controller is connected to the TEC of the APD refrigeration box through the second digital-to-analog converter DAC2 and the switching power supply in sequence, and the NTC on the TEC is connected to the controller through the second operational amplifier and the second analog-to-digital converter ADC2 in sequence.

[0015] As a further optimized technical solution, the gate voltage generating circuit includes a PLL and a phase shift controller which are sequentially connected from the synchronous clock input terminal to the gate voltage output terminal.

[0016] As a further optimized technical solution, the PLL adopts a phase-locked loop with an enabling function, and the phase shift controller adopts an adjustable phase shifter.

[0017] As a further optimized technical solution, the gate voltage generating circuit also includes a gate amplitude stabilization control circuit, which includes an attenuator, a power amplifier, and a coupler connected in sequence behind the phase shift controller, and a first detector and a third analog-to-digital converter ADC3 connected between the output end of the coupler and the controller, and also includes a third digital-to-analog converter DAC3 and a third operational amplifier connected in sequence between the controller and the input end of the attenuator, wherein the controller is connected to the PLL_EN port of the PLL.

[0018] As a further optimized technical solution, the avalanche signal extraction circuit includes a cascade filter amplifier circuit and a discrimination circuit connected in sequence, wherein the cascade filter amplifier circuit adopts "3-stage filtering + 2-stage amplification", and its topology structure is "filter-amplification-filter-filter-amplification".

[0019] As a further optimized technical solution, the first, second and third stage filters use low-pass filters, the first stage amplifier uses a low-noise amplifier, the second stage amplifier uses a gain amplifier, and the discrimination circuit uses a high-speed comparator.

[0020] The advantages of the utility model are:

[0021] 1. A general high-efficiency single-photon detector solution designed by the utility model comprehensively considers the combination of bias voltage, gate voltage, cooling control, and avalanche signal extraction, loads appropriate gate voltage and bias voltage at both ends of APD to ensure detection efficiency, realizes passive quenching of free-running working mode (also called free-running mode) through series resistance, sets an avalanche signal extraction point at the APD anode, simplifies the dead time processing circuit, reduces APD thermal noise by setting a cooling temperature control circuit, and realizes the suppression of gate differential noise by setting an avalanche signal extraction circuit, which can greatly reduce the detector noise level;

[0022] 2. The avalanche signal extraction circuit designed by the utility model can extract the avalanche signal by only using a 3-stage filtering and a 2-stage amplification structure, which simplifies the circuit, reduces the circuit volume, and can achieve deep suppression of noise signals (such as gated differential signals) and amplification of avalanche signals;

[0023] 3. The designed bias voltage generation circuit has the ability to automatically adjust the bias signal amplitude and detect bias current. By detecting the APD working bias voltage and current, it is used as a judgment condition to identify whether there is a strong light attack. When the bias current is too large, the bias voltage loaded on the APD can be reduced in time to avoid overcurrent damage caused by a long avalanche time of the APD.

[0024] 4. The gate voltage generation circuit designed takes into account the gate width stability at different phase points, which can maintain the stability of the detection efficiency of the single-photon detector;

[0025] 5. The single-photon detector designed by the utility model has a simple structure, is easy to implement in engineering, and has low cost. According to different application scenarios, the gate voltage can be turned off by disabling the phase-locked loop, and the single-photon detector can be flexibly switched between the gated detection mode and the free-running mode. It has high working adaptability and working reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 This is a structural block diagram of a single-photon detector according to an embodiment of the utility model;

[0027] Figure 2 This is a working flow diagram of switching between the gated mode and the free running mode in the embodiment of the utility model;

[0028] Figure 3 is an overall circuit function relationship diagram of a single photon detector circuit in an embodiment of the utility model;

[0029] Figure 4 It is a circuit diagram of bias voltage generation in an embodiment of the utility model;

[0030] Figure 5 This is a refrigeration temperature control circuit diagram in an embodiment of the utility model;

[0031] Figure 6 This is a gate voltage generation circuit diagram in an embodiment of the utility model;

[0032] Figure 7 This is a circuit diagram of an avalanche signal extraction in an embodiment of the utility model;

[0033] Figure 8 It is a schematic diagram of a detection mode in which a bias voltage is superimposed on a gate voltage in an embodiment of the utility model;

[0034] Fig. 9 This is a working diagram of a single photon detector in a gated detection working mode in an embodiment of the present invention;

[0035] Fig.10 This is a working flow diagram of a single photon detector in a free-running working mode in an embodiment of the utility model. DETAILED DESCRIPTION

[0036] In order to make the purpose, technical solution and advantages of the embodiments of the utility model clearer, the technical solution in the embodiments of the utility model will be clearly and completely described below in combination with the embodiments of the utility model. Obviously, the described embodiments are part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments of the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.

[0037] The controller in the utility model can be implemented as a general processor, a programmable logic controller (PLC), a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, a discrete gate or transistor logic device, a discrete hardware component or any appropriate combination thereof for performing the functions described in the present disclosure. In the embodiment, the FPGA controller is used as an example for description.

[0038] Figure 1 This is the overall structural block diagram of the single-photon detector of the embodiment of the utility model, including an FPGA controller, a bias voltage generating circuit, a cooling temperature control circuit, a gate voltage generating circuit, an APD (Avalanche Photo Diode) cooling box, and an avalanche signal extraction circuit. The bias voltage generating circuit and the gate voltage generating circuit are respectively connected to the cathode of the APD in the APD cooling box at one end and connected to the FPGA controller at the other end, the avalanche signal extraction circuit is connected to the anode of the APD in the APD cooling box at one end and connected to the FPGA controller at the other end, and the cooling temperature control circuit is connected to the multi-stage TEC (Thermoelectric cooler, semiconductor cooler) of the APD cooling box at one end and connected to the FPGA controller at one end.

[0039] Bias voltage generation circuit: realizes the reverse bias voltage loading to APD. The loaded reverse bias voltage has the characteristics of adjustable and high precision, and can load a bias voltage lower or higher than the avalanche breakdown voltage;

[0040] Gate voltage generation circuit: realizes the generation of gate voltage, the gate voltage amplitude is adjustable and the output can be turned off. The combination of different gate voltage amplitudes and bias voltages can make the voltage finally loaded on both ends of the APD higher or lower than the avalanche breakdown voltage, so that the APD can achieve alternation between the two processes of avalanche or quenching;

[0041] Cooling temperature control circuit: TEC cooling is completed by detecting the TEC cold surface temperature and applying control voltage to the multi-stage TEC, thereby cooling the APD operating temperature to reduce the APD thermal noise level;

[0042] APD refrigeration box: The refrigeration box adopts an airtight sealing design, with built-in APD, multi-stage TEC, negative temperature coefficient thermistor (NTC) and other resistors and capacitors. The APD and NTC resistors are placed on the cold side of the TEC. The TEC refrigeration current and NTC detection results are connected to the refrigeration temperature control circuit. The bias voltage signal generated by the bias voltage generation circuit is combined and loaded to the APD cathode through the series resistor R1 (1kΩ) and the gate voltage generated by the gate voltage generation circuit through the AC coupling capacitor C1 (100nF). The APD anode is connected to the avalanche signal extraction circuit through the AC coupling capacitor C2. One end of the sampling resistor R2 (50Ω) is connected to the APD anode and the AC coupling capacitor C2, and the other end is grounded. The avalanche signal is IV converted through the sampling resistor R2, and then output to the avalanche signal extraction circuit through the AC coupling capacitor C2 (100nF);

[0043] Avalanche signal extraction circuit: suppresses gate noise, amplifies avalanche signals, and performs compliance filtering on unexpected signals to achieve noise suppression and avalanche signal extraction;

[0044] FPGA controller: As the control unit of the single-photon detector, it is mainly used to control the generation and stabilization of the bias voltage and gate voltage, adjust the TEC temperature, receive avalanche signals, and evaluate the detector working status in real time by sampling the bias working current of the mirror image and take corresponding measures in abnormal situations to ensure the safety of APD operation.

[0045] The above circuit architecture can adjust the gate voltage working mode and bias voltage amplitude through the FPGA controller, and realize the two working modes of gated detection and free running in combination. The FPGA controller controls the gate voltage generation circuit to be turned off, and adjusts the bias voltage generated by the bias voltage generation circuit to be higher than the avalanche breakdown voltage. The passive quenching is completed by the resistor R1 connected in series with the APD. At this time, the detector works in the free running mode; the FPGA controller controls the gate voltage generation circuit to be turned on, and adjusts the bias voltage generated by the bias voltage generation circuit to be lower than the avalanche breakdown voltage. The gate voltage is loaded so that the voltage across the APD exceeds the avalanche breakdown voltage and the gate voltage completes the active quenching. At this time, the detector works in the gated mode.

[0046] In the utility model, the automatic switching of the two working modes of the detector is realized through FPGA control instructions, the degree of automation is high, and single-photon detectors with different performances can be reconstructed according to different application scenarios.

[0047] The working process of switching between the gated mode and the free-running mode of the single-photon detector of the utility model is as follows Figure 2 As shown, the specific steps include:

[0048] Step 1: Power on the detector;

[0049] Step 2, by controlling the register PLL_EN in the gate voltage generating circuit through FPGA, the gate voltage output is turned off, thereby only retaining the bias voltage output of the bias voltage generating circuit;

[0050] Step 3, setting the bias voltage higher than the avalanche breakdown voltage;

[0051] Step 4: The detector enters the free-running working mode;

[0052] Step 5, determine whether the detector receives the gate mode command, if the gate mode command is received, go to step 6, otherwise return to step 4;

[0053] Step 6: lower the target bias voltage to below the avalanche breakdown voltage;

[0054] Step 7, control the register PLL_EN in the gate voltage generation circuit to be high (set to 1) through the FPGA controller, and turn on the gate voltage output;

[0055] Step 8: The detector enters the gated detection working mode;

[0056] Step 9: Determine whether the detector receives a free-running mode instruction. If the detector receives a free-running mode instruction, return to step 2; otherwise, return to step 8.

[0057] See also Figure 3 , is a diagram showing the overall circuit function relationship of the single photon detector in the embodiment of the utility model. The circuit diagram of the bias voltage generating circuit, the cooling temperature control circuit, the gate voltage generating circuit, and the avalanche signal extraction circuit in the utility model is shown in FIG. Figures 4 to 7 shown.

[0058] See also Figure 4 The bias voltage generating circuit described in the embodiment of the utility model includes a first digital-to-analog converter DAC1, a boost converter, a first operational amplifier, and a first analog-to-digital converter ADC1, wherein the input end of the first digital-to-analog converter DAC1 is connected to the FPGA controller, and the output end is connected to the boost converter. One output end of the boost converter serves as the output end of the bias voltage generating circuit, outputs the bias voltage to the APD, and one end is connected to the FPGA controller through the first operational amplifier and the first analog-to-digital converter ADC1 in sequence.

[0059] The FPGA controller sets the bias voltage control value through the first digital-to-analog converter DAC1, and uses a boost converter with current detection function (such as model: SGM41285A). Under the action of the control voltage, a bias voltage in the range of 10V-70V can be generated, and the step value is less than 10mV. When the boost converter uses external voltage control, the maximum control voltage is 1.2V. When the external input exceeds 1.2V, the boost converter will force the use of the internal 1.2V reference voltage to protect the bias voltage output maximum value of 70V. The current output by the boost converter to the APD can also be mirrored at a ratio of 1:1. The mirrored bias working current (called "bias current") enters the first analog-to-digital converter ADC1 for digital sampling after IV conversion by the first operational amplifier. The sampled voltage value is read in real time by the FPGA controller, and the magnitude of the APD injection light intensity is identified by monitoring the change amplitude of the bias current, and further determines whether there is strong light injection behavior.

[0060] See also Figure 5 As shown, the refrigeration temperature control circuit described in the embodiment of the utility model includes a switching power supply, a second digital-to-analog converter DAC2, a second analog-to-digital converter ADC2 and a second operational amplifier, wherein the FPGA controller is connected to the TEC of the APD refrigeration box through the second digital-to-analog converter DAC2 and the switching power supply in sequence, and the NTC on the TEC is connected to the FPGA controller through the second operational amplifier and the second analog-to-digital converter ADC2 in sequence.

[0061] The FPGA controller sets the voltage control value of the switching power supply (DC-DC) through the second digital-to-analog converter DAC2, and the switching power supply provides a large cooling current (greater than 5A) for TEC; the NTC detection output end is amplified by the second operational amplifier and enters the second analog-to-digital converter ADC2 (the reference voltage is 4.096V, 16bit) for digital sampling. The sampled voltage value is read by the FPGA controller in real time. When the sampled NTC temperature is cooled to the target temperature range, the target bias voltage is loaded. At the same time, the FPGA controller uses a closed-loop feedback control algorithm to achieve temperature stabilization control capability, reduce the APD thermal noise level, and the temperature stabilization accuracy can reach ±0.1℃.

[0062] See also Figure 6As shown, the gated voltage generating circuit described in the embodiment of the utility model includes a PLL (phase locked loop), a phase shift controller, an attenuator, a power amplifier, and a coupler connected in sequence from the synchronous clock input terminal to the gated voltage output terminal, and also includes a first detector and a third analog-to-digital converter ADC3 connected in sequence between the output terminal of the coupler and the FPGA controller, and also includes a third digital-to-analog converter DAC3 and a third operational amplifier connected in sequence between the FPGA controller and the input terminal of the attenuator, wherein the FPGA controller is connected to the PLL_EN port of the PLL.

[0063] Taking the example of receiving a low-frequency synchronous clock (100kHz) to generate a single-frequency sinusoidal gate voltage, the gate voltage generation circuit can generate a sinusoidal gate voltage with an amplitude range of 5-20V, adjustable phase, and stable gate amplitude. Among them, as an optional device combination, the PLL adopts a phase-locked loop with an enable function (for example, model: AD9520) to phase-lock and multiply the 100kHz low-frequency synchronous clock to 1.25GHz, and the phase shift controller adopts an adjustable phase shifter (for example, model: MAPS-011007) with a 360° phase shift capability and a minimum adjustment range of 12.5ps. The attenuator adopts a voltage-controlled attenuator (for example, model: RFSA2013) to meet the attenuation range control. Of course, it is known to those skilled in the art that many other types of devices can still achieve the functions or capabilities described in the above-mentioned devices. Therefore, the above-mentioned devices can also use other existing devices that can achieve the same or similar functions.

[0064] The attenuator, power amplifier, coupler, first detector, third analog-to-digital converter ADC3, third digital-to-analog converter DAC3, third operational amplifier and FPGA controller form a closed-loop gate amplitude stabilization control circuit, which can maintain the stability of the gate voltage at different phase points. The gate amplitude stabilization working process is as follows: the gate voltage after passing through the attenuator and the power amplifier (point A) outputs a part of the power to the first detector for detection through the coupler (30dB). The detection voltage enters the FPGA controller for algorithm adjustment after passing through the third analog-to-digital converter ADC3. The FPGA controller compares the real-time detection voltage with the target detection voltage. If the detection voltage is lower than the target detection voltage, the output of the third analog-to-digital converter DAC3 is changed, and the attenuator is acted on through the third operational amplifier to reduce the attenuation value to increase the gate voltage value output from the gate voltage output terminal (point B). If the detection voltage is higher than the target detection voltage, the output of the third analog-to-digital converter DAC3 is changed, and the attenuator is acted on through the third operational amplifier to increase the attenuation value to reduce the gate voltage value output from the gate voltage output terminal (point B), thereby maintaining the stability of the gate voltage.

[0065] Furthermore, the FPGA controller can set PLL_EN of the PLL to low, disable the PLL, turn off the gate voltage function, and increase the bias voltage to make the APD work in the free-running working mode.

[0066] See also Figure 7 The avalanche signal extraction circuit in the embodiment of the utility model includes a cascade filter amplifier circuit and a discrimination circuit connected in sequence, wherein the cascade filter amplifier circuit adopts "3-stage filtering + 2-stage amplification", and its topology is "filter-amplification-filter-filter-amplification". The circuit topology of the utility model reduces the volume of the avalanche extraction circuit and the number of filters and amplifiers used, thereby reducing the parasitic parameters of the avalanche extraction circuit, reducing the jitter of the avalanche signal front edge, and effectively reducing the noise level of the detector.

[0067] When the detector works in the gated detection mode, since the main energy frequency of the avalanche signal is below 1GHz, the first-stage filter uses a low-pass filter to filter out the gated differential noise (1.25GHz) and higher-frequency external crosstalk signals while retaining useful avalanche signals; since the filter has a certain insertion loss that will reduce the originally small avalanche signal, a low-noise amplifier is used to amplify the avalanche signal after the first-stage filter. Since the gated voltage suppressed by the first-stage filter will be amplified again by the low-noise amplifier, the second and third-stage filters are added after the low-noise amplifier to filter the gated noise to the level of white noise, and the avalanche signal can be extracted after a first-stage gain amplification. Among them, the first, second and third stage filters use low-pass filters (for example, model: LFCN-800+) with a 3dB cut-off frequency of 990MHz; the first stage amplifier uses a low-noise amplifier (for example, model: WHM02AE) with a noise factor NF=0.7dB; the second stage amplifier uses a gain amplifier (for example, model: SGA4486A), and the amplified avalanche signal is identified by a high-speed comparator (8GHz), which can retain the leading edge information of the avalanche signal as much as possible, and the identified signal is output as a detection pulse.

[0068] When the detector works in free-running mode, due to the use of passive quenching, there is no gated differential noise in the avalanche signal. The three-stage filter can still filter out noise signals in unexpected frequency bands and suppress external high-frequency crosstalk from entering the avalanche amplification circuit. The two-stage amplifier can amplify the avalanche signal to an appropriate level. The amplified avalanche signal is identified by a high-speed comparator (8GHz), which can retain the leading-edge information of the avalanche signal as much as possible. The identified signal is output as a detection pulse.

[0069] As the control unit of the single-photon detector, the FPGA controller is used to control the generation of bias voltage and bias current detection, the generation and stabilization of gate voltage, the TEC temperature stabilization control, etc. It can control the single-photon detector to work in gated detection mode or free-running mode, and evaluate the detector working status in real time and take corresponding measures in abnormal situations to ensure the safety of APD operation; Fig. 9 , Fig.10 The overall workflow of the single-photon detector in two working modes is demonstrated respectively.

[0070] like Fig. 9 As shown, combined Figure 3 , for the gated detection working mode, the workflow of the single photon detector includes:

[0071] Step S1, powering on the single photon detector;

[0072] Step S2, loading a default bias voltage (40V);

[0073] Step S3, starting the cooling temperature control circuit to perform cooling control on the TEC. Specifically, the FPGA controller sets the voltage control value of the switching power supply (DC-DC) through the second digital-to-analog converter DAC2, and the switching power supply provides a large cooling current (greater than 5A) for the TEC.

[0074] Step S4, collecting NTC temperature. Specifically, the NTC detection output terminal is amplified by the second operational amplifier and enters the second analog-to-digital converter ADC2 (reference voltage is 4.096V, 16bit) for digital sampling, and the sampled voltage value is read in real time by the FPGA controller;

[0075] Step S5, the FPGA controller determines whether the cooling temperature is within the target temperature range, if so, proceeds to step S6, otherwise returns to step S3;

[0076] Step S6, the FPGA controller sends a target bias voltage. Specifically, the FPGA controller sets the value of the first digital-to-analog converter DAC1, and generates a target bias voltage (such as 62V) after the boost converter. The set bias voltage is slightly lower than the avalanche breakdown voltage (such as 64V). The bias voltage acts on the cathode of the APD at point C. At the same time, the APD bias current change is monitored to identify whether there is strong light injection behavior;

[0077] Step S7, the FPGA controller detects a PLL lock indication (i.e., sets PLL_EN high);

[0078] Step S8, the FPGA controller determines whether the PLL receives a lock indication, and if the PLL is locked, it proceeds to step S9, otherwise it returns to step S7;

[0079] Step S9, when the PLL lock indication is detected, the target gate voltage amplitude signal (such as 10V) is issued. Specifically, the FPGA controller sets PLL_EN high, accepts the synchronous clock input, and generates an initial gate voltage through the PLL and phase shift controller, which acts on the cathode of the APD through the AC coupling capacitor C1 at point B. The bias voltage is superimposed on the gate voltage to make the voltage amplitude loaded on the APD greater than the avalanche breakdown voltage. When the bias voltage superimposed on the gate voltage exceeds the avalanche breakdown voltage, avalanche can occur and single photon detection can be performed. When the bias voltage superimposed on the gate voltage does not exceed the avalanche breakdown voltage, the avalanche process is quenched, such as Figure 8 As shown;

[0080] Step S10, start gate amplitude stabilization. Specifically, the gate amplitude stabilization working process is as follows: the gate voltage after the initial gate voltage passes through the attenuator and the power amplifier (point A) outputs a part of the power to the first detector through the coupler (30dB) for detection. The detection voltage enters the FPGA controller for algorithm adjustment after passing through the third analog-to-digital converter ADC3. The FPGA controller compares the real-time detection voltage with the target detection voltage. If the detection voltage is lower than the target detection voltage, the output of the third analog-to-digital converter DAC3 is changed, and the attenuator is acted on by the third operational amplifier to reduce the attenuation value to increase the gate voltage value outputted from the gate voltage output terminal (point B). If the detection voltage is higher than the target detection voltage, the output of the third analog-to-digital converter DAC3 is changed, and the attenuator is acted on by the third operational amplifier to increase the attenuation value to reduce the gate voltage value outputted from the gate voltage output terminal (point B), thereby maintaining the stability of the gate voltage.

[0081] Step S11, when a single photon signal is incident, start delayed scanning to find the maximum detection efficiency point;

[0082] Step S12, entering the normal single-photon detection state, the avalanche signal is output from point D, the avalanche signal extraction circuit filters out the gated noise and amplifies the avalanche signal, adopts the circuit topology of "filtering-low noise amplification-filtering-filtering-amplification", reduces the number of filters and amplifiers used, and reduces the leading edge jitter of the avalanche signal.

[0083] like Fig.10 As shown, combined Figure 3 , for the free-running mode, the workflow of the single-photon detector includes:

[0084] Step S10, the single photon detector is powered on, and the FPGA controller outputs a PLL_EN signal to control the phase-locked loop so that the PLL has no output, and the gate voltage at point B has no output;

[0085] Step S20, loading a default bias voltage (40V);

[0086] Step S30, start the cooling temperature control circuit to perform cooling control on the TEC. Specifically, the FPGA controller sets the voltage control value of the switching power supply (DC-DC) through the second digital-to-analog converter DAC2, and the switching power supply provides a large cooling current (greater than 5A) for the TEC.

[0087] Step S40, collecting NTC temperature. Specifically, the NTC detection output terminal is amplified by the second operational amplifier and then enters the second analog-to-digital converter ADC2 (reference voltage is 4.096V, 16bit) for digital sampling, and the sampled voltage value is read in real time by the FPGA controller;

[0088] Step S50, the FPGA controller determines whether the cooling temperature is within the target temperature range, if so, proceeds to step S60, otherwise returns to step S30;

[0089] Step S60, the FPGA controller sends a target bias voltage. Specifically, the FPGA controller sets the value of the first digital-to-analog converter DAC1, and generates a target bias voltage (such as 68V) after the boost converter. The set bias voltage is higher than the avalanche breakdown voltage (such as 64V). The bias voltage acts on the cathode of the APD at point C. At the same time, the APD bias current change is monitored to identify whether there is strong light injection behavior. When the APD generates a continuous avalanche, as the avalanche current increases, the series resistor R1 (1kΩ) will produce a large voltage drop, so that the reverse bias voltage at both ends of the APD is lower than the breakdown voltage, thereby realizing the avalanche quenching process;

[0090] Step S70: when a single photon signal is incident, start delayed scanning to find the maximum detection efficiency point;

[0091] Step S80, entering the normal single-photon detection state, the avalanche signal is output from point D, the avalanche signal extraction circuit filters out the noise and amplifies the avalanche signal, adopts the circuit topology of "filtering-low-noise amplification-filtering-filtering-amplification", reduces the number of filters and amplifiers used, and reduces the leading edge jitter of the avalanche signal.

[0092] In the circuit designed by the utility model, an avalanche signal is extracted at the APD anode. When the single-photon detector is in a free-running working mode, only the resistor R1 is used to generate a voltage drop, so that the voltage across the APD is lower than the avalanche breakdown voltage, thereby achieving avalanche quenching and simplifying the dead time processing circuit.

[0093] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A single photon detector, comprising a controller, a bias voltage generating circuit, a refrigeration temperature control circuit, a gate voltage generating circuit, and an APD refrigeration box, wherein one end of the refrigeration temperature control circuit is connected to the TEC of the APD refrigeration box, and the other end is connected to the controller, characterized in that: It also includes an avalanche signal extraction circuit, wherein a bias voltage generating circuit, a gate voltage generating circuit and one end of an avalanche signal extraction circuit are connected to a controller, the other end of the avalanche signal extraction circuit is connected to the anode of the APD in the APD refrigeration box through an AC coupling capacitor C2, the anode of the APD is grounded through a sampling resistor R2, the other end of the bias voltage generating circuit is connected to the cathode of the APD through a resistor R1, and the other end of the gate voltage generating circuit is connected to the cathode of the APD through an AC coupling capacitor C1.

2. The single photon detector according to claim 1, characterized in that The resistance value of the resistor R1 is 1 kΩ, the resistance value of the sampling resistor R2 is 50 Ω, and the capacitance values ​​of the AC coupling capacitors C1 and C2 are both 100 nF.

3. The single photon detector according to claim 1, characterized in that The bias voltage generating circuit comprises a first digital-to-analog converter DAC1 and a boost converter, wherein the input end of the first digital-to-analog converter DAC1 is connected to the controller, the output end is connected to the boost converter, and an output end of the boost converter serves as the output end of the bias voltage generating circuit.

4. The single photon detector according to claim 3, characterized in that: The bias voltage generating circuit also includes a first operational amplifier and a first analog-to-digital converter ADC1. The other output end of the boost converter is connected to the controller through the first operational amplifier and the first analog-to-digital converter ADC1 in sequence. The output end of the boost converter is connected to the first operational amplifier.

5. The single photon detector according to claim 1, characterized in that: The refrigeration temperature control circuit includes a switching power supply, a second digital-to-analog converter DAC2, a second analog-to-digital converter ADC2 and a second operational amplifier, wherein the controller is connected to the TEC of the APD refrigeration box through the second digital-to-analog converter DAC2 and the switching power supply in sequence, and the NTC on the TEC is connected to the controller through the second operational amplifier and the second analog-to-digital converter ADC2 in sequence.

6. The single photon detector according to claim 1, characterized in that: The gate voltage generating circuit comprises a PLL and a phase shift controller which are sequentially connected from a synchronous clock input terminal to a gate voltage output terminal.

7. The single photon detector according to claim 6, characterized in that: The PLL adopts a phase-locked loop with an enable terminal, and the phase shift controller adopts an adjustable phase shifter.

8. The single photon detector according to claim 6, characterized in that: The gate voltage generating circuit also includes a gate amplitude stabilization control circuit, which includes an attenuator, a power amplifier, and a coupler connected in sequence behind the phase shift controller, and a first detector and a third analog-to-digital converter ADC3 connected between the output end of the coupler and the controller, and also includes a third digital-to-analog converter DAC3 and a third operational amplifier connected in sequence between the controller and the input end of the attenuator, wherein the controller is connected to the PLL_EN port of the PLL.

9. The single photon detector according to claim 1, characterized in that: The avalanche signal extraction circuit comprises a cascade filter amplifier circuit and a discrimination circuit connected in sequence, wherein the cascade filter amplifier circuit adopts "three-stage filtering + two-stage amplification", and its topology structure is "filter-amplification-filter-filter-amplification".

10. The single photon detector according to claim 9, characterized in that: The first, second and third stage filters use low-pass filters, the first stage amplifier uses a low-noise amplifier, the second stage amplifier uses a gain amplifier, and the discrimination circuit uses a high-speed comparator.

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