CPLD-based responder circuit

Abstract

The utility model relates to a CPLD (Complex Programmable Logic Device)-based responder circuit, which comprises a preemptive answering input module used for latching a preemptive answering signal sent by a first contestant who preemptively answers and making the preemptive answering signals sent by other contestant invalid; the countdown module is used for countdown at the beginning of preemptive answering; the referee voting module is used for acquiring a referee voting result; the scoring pulse generation module is used for generating a scoring pulse signal according to the judgment voting result; the score adding and subtracting module is used for adding or subtracting scores for the successfully responded competitors according to the score pulse signal to obtain the score of each competitor; the nixie tube display module is used for displaying the countdown count value and the score of each player; the host module is used for outputting a preemptive answering control signal when preemptive answering is started, and sending a score adding control signal or a score reducing control signal when score adding and score reducing are needed; and when the score needs to be reset, a score reset signal is sent to the score adding and subtracting module.

Description

Technical Field

[0001] The utility model relates to the field of buzzer answering machines, in particular to a buzzer answering machine circuit based on CPLD. Background Art

[0002] A buzzer is an electronic device used in a multi-person quiz to determine which participant answers the question first. Existing buzzer circuits include PLC-based buzzer circuits, FPGA-based buzzer circuits, and single-chip microcomputer-based buzzer circuits. In the field of experimental teaching, breadboards, wires, and basic circuit components are usually used to implement buzzer circuits, which are limited by the existing components in the laboratory. Utility Model Content

[0003] Based on this, the purpose of the utility model is to provide a CPLD-based buzzer circuit, which has programmability, can break through the limitations of existing laboratory components, and increase flexibility for digital electronic technology experimental teaching.

[0004] The utility model provides a CPLD-based buzzer circuit, comprising a buzzer input module and a host module; the host module is used for outputting a buzzer control signal at the beginning of buzzer to reset the buzzer input module; the buzzer input module comprises: N AND gates, N OR gates, N D flip-flops and N channel NOR gates; N is the number of contestants; the N AND gates of the buzzer input module are respectively recorded as 1st to Nth buzzer AND gates; the N OR gates are respectively recorded as 1st to Nth buzzer OR gates; the N D flip-flops are respectively recorded as 1st to ND flip-flops; each D flip-flop is provided with a trigger signal input terminal, a clock signal input terminal, a same-phase output terminal and a reset signal input terminal; the first input terminal of the i-th buzzer AND gate is connected to the buzzer signal input terminal of the i-th contestant, the second input terminal is connected to the output terminal of the N channel NOR gate, and the output terminal is connected to the first input terminal of the i-th buzzer OR gate; the first input terminal of the i-th buzzer OR gate is connected to the output terminal of the i-th buzzer AND gate, and the second input terminal is connected to the output terminal of the i-th buzzer The in-phase output end of the D flip-flop is connected to the trigger signal input end of the ith D flip-flop; the trigger signal input end of the ith D flip-flop is connected to the output end of the ith quick-answer OR gate, the clock signal input end is connected to the external clock signal, the reset signal input end is connected to the quick-answer control signal output by the host module, and the in-phase output end is connected to the ith input end of the N-channel OR gate; the in-phase output end of the ith D flip-flop is the ith quick-answer signal output end; the ith input end of the N-channel OR gate is connected to the in-phase output end of the ith D flip-flop, and the output end is connected to the second input end of the ith quick-answer AND gate; i is any integer in the interval [1,N].

[0005] The utility model discloses a buzzer circuit based on CPLD, which is implemented by CPLD (Complex Programming logic device) and Quartus II and has programmability, thus being able to break through the limitation of existing laboratory components and increase flexibility for digital electronic technology experimental teaching.

[0006] Furthermore, it also includes a countdown module; the answer control signal output by the host module is also used to reset the countdown module; the countdown module includes: a countdown counter, an n-channel OR gate and a three-channel AND gate; n is the number of bits of the countdown counter; the countdown counter includes a preset input terminal, a countdown clock input terminal and a countdown count value output terminal; the preset input terminal of the countdown counter is connected to the answer control signal output by the host module; the countdown clock input terminal of the countdown counter is connected to the output terminal of the three-channel AND gate; the countdown count value of the countdown counter is output to the countdown counter. value, connected to the input end of the n-channel OR gate; only when the countdown count value is equal to 0, the output end of the n-channel OR gate is at a low level; the first input end of the three-channel AND gate is connected to the external clock signal, the second input end is connected to the output end of the n-channel OR gate, the third input end is connected to the output end of the N-channel OR gate of the quick answer input module, and the output end is connected to the down-counting clock input end of the countdown counter; the n-channel OR gate includes n input ends, wherein the i'th input end is connected to the i'th count value output end of the countdown counter, and i' is any integer in the interval [1,n].

[0007] Furthermore, it also includes a referee voting module, a scoring pulse generating module and a score addition and subtraction module; the referee voting module is used to obtain the referee voting result; the host module is also used to send a score addition control signal or a score subtraction control signal when it is necessary to add or subtract points; the scoring pulse generating module includes a score addition pulse generating module and a score subtraction pulse generating module; the score addition pulse generating module generates a score addition pulse signal according to the score addition control signal issued by the host module and the referee voting result; the score subtraction pulse generating module generates a score subtraction pulse signal according to the score subtraction control signal issued by the host module and the referee voting result; the score addition and subtraction module is used to add or subtract points for the contestants who successfully answer the questions according to the score addition control signal or the score subtraction control signal, so as to obtain the score of each contestant.

[0008] Furthermore, the deduction pulse generation module includes a pulse number counter, a first NOT gate, a second NOT gate, a third NOT gate, a first AND gate, a second AND gate and a third AND gate; the pulse number counter includes a clock signal input terminal, a pulse number count value output terminal, a reset terminal and a counting control terminal; the deduction control signal sent by the host module is connected to the first input terminal of the first AND gate, the referee voting result is connected to the second input terminal of the first AND gate through the first NOT gate, and the output terminal of the first AND gate is connected to the reset terminal of the pulse number counter; the input terminal of the second NOT gate is connected to the pulse number count value output terminal of the pulse number counter The first input terminal of the second AND gate is connected to the reset terminal of the pulse counter, the second input terminal is connected to the external clock signal, and the output terminal is connected to the clock signal input terminal of the pulse counter through the third NOT gate; the first input terminal of the third AND gate is connected to the count control terminal of the pulse counter, the second input terminal is connected to the output terminal of the second AND gate, and the output terminal outputs the subtraction pulse signal.

[0009] Furthermore, the host module is also used to send a score reset signal when the score needs to be reset; the addition and subtraction module includes: an addition and subtraction counter, a first addition and subtraction NAND gate and a second addition and subtraction NAND gate; the addition and subtraction counter includes a preset input terminal, an addition count clock input terminal, a subtraction count clock input terminal and a score output terminal; the preset input terminal of the addition and subtraction counter is connected to the score reset signal sent by the host module; the first input terminals of the first addition and subtraction NAND gate and the second addition and subtraction NAND gate are both connected to the in-phase output terminal of the D trigger corresponding to the contestant in the quick answer input module; the second input terminal of the first addition and subtraction NAND gate is connected to the subtraction pulse signal, and the output terminal is connected to the subtraction clock input terminal of the addition and subtraction counter; the second input terminal of the second addition and subtraction NAND gate is connected to the addition pulse signal, and the output terminal is connected to the addition count clock input terminal of the addition and subtraction counter.

[0010] Furthermore, it also includes a digital tube display module; the digital tube display module includes a 7448 decoder and a digital tube; the countdown count value output by the countdown module and the score output by the addition and subtraction module are connected to the corresponding digital tubes through the 7448 decoder respectively.

[0011] Furthermore, the D flip-flop of the quick-answer input module is implemented by a 7474 chip; the countdown module and the countdown counter are implemented by two cascaded 74192 counter chips; the pulse number counter of the subtraction pulse generation module is implemented by a 74161 counter chip; and the addition and subtraction counter of the addition and subtraction module is implemented by two cascaded 74192 counter chips.

[0012] Furthermore, the referee voting module includes: a first NAND gate, a second NAND gate, and a third NAND gate; the first input end of the first NAND gate is connected to the chief referee voting signal, and the second input end is connected to the first deputy referee voting signal; the first input end of the second NAND gate is connected to the chief referee voting signal, and the second input end is connected to the second deputy referee voting signal; the first input end of the third NAND gate is connected to the output end of the first NAND gate, and the second input end is connected to the output end of the second NAND gate; the output end of the third NAND gate outputs the referee voting result.

[0013] In order to better understand and implement the present invention, the present invention is described in detail below with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 This is a module schematic diagram of a CPLD-based buzzer circuit according to Embodiment 1 of the present utility model;

[0015] Figure 2 The schematic diagram of the circuit structure of the answer input module of the answer circuit based on CPLD of the utility model embodiment 1;

[0016] Figure 3 This is a circuit structure diagram of a countdown module of a CPLD-based buzzer circuit according to Embodiment 1 of the present utility model;

[0017] Figure 4 This is a circuit structure diagram of a referee voting module of a CPLD-based buzzer circuit according to Embodiment 1 of the present utility model;

[0018] Figure 5 A schematic diagram of the circuit structure of a subtraction pulse generating module of a CPLD-based buzzer circuit according to Embodiment 1 of the present utility model;

[0019] Figure 6 A schematic diagram of the circuit structure of a score-adding pulse generating module of a CPLD-based answering circuit according to Embodiment 1 of the present utility model;

[0020] Figure 7 The circuit structure diagram of the addition and subtraction module of the CPLD-based buzzer circuit of Example 1 of the utility model;

[0021] Figure 8A schematic diagram of the circuit structure of a quick answer input module of a quick answer circuit based on CPLD according to Embodiment 2 of the present utility model;

[0022] Fig. 9 This is a circuit structure diagram of a countdown module of a CPLD-based buzzer circuit according to Embodiment 2 of the present utility model;

[0023] Fig.10 This is a circuit structure diagram of a subtraction pulse generation module of a CPLD-based buzzer circuit according to Embodiment 2 of the present utility model;

[0024] Fig.11 The present invention is a schematic diagram of the circuit structure of the addition and subtraction module of the CPLD-based buzzer circuit according to Example 2 of the present invention. DETAILED DESCRIPTION

[0025] The utility model is a CPLD-based buzzer circuit, which is applied in multi-player quiz activities. The multi-player quiz activities involved in the utility model involve several contestants, judges and hosts, and the competition process is as follows: the host announces the topic, and the contestants answer within the set answer time; the first contestant who presses the answer button answers successfully, and the answers of other contestants who press the answer button later are invalid. Then the contestant who successfully answers the question answers the question and gives the answer. The judges vote according to the answers given by the contestants to obtain the referee voting results. Finally, according to the referee voting results, the scores of the corresponding contestants are added or subtracted, and the scores of each contestant are calculated and displayed.

[0026] The CPLD-based buzzer circuit of the utility model is implemented by CPLD (Complex Programming logic device) and Quartus II, and has programmability, so it can break through the limitations of existing laboratory components and increase flexibility for digital electronic technology experimental teaching. Furthermore, the CPLD-based buzzer circuit of the utility model has comprehensive functions, and compared with the traditional buzzer circuit, it adds an integrated design of referee scoring and contestant addition and subtraction of points, and has wider versatility.

[0027] Example 1

[0028] See also Figure 1 , Figure 1The module schematic diagram of the CPLD-based buzzer circuit of the first embodiment of the utility model. The CPLD-based buzzer circuit of the first embodiment of the utility model comprises: a buzzer input module 1, a countdown module 2, a referee scoring module 3, a scoring pulse generation module 4, a score addition and subtraction module 5, a digital tube display module 6 and a host module 7. The buzzer input module 1 is used to latch the buzzer signal sent by the first contestant who answers, and invalidate the buzzer signals sent by other contestants. The countdown module 2 is used to count down at the beginning of the buzzer until the set buzzer time ends or a contestant answers, then stop the countdown. The referee voting module 3 is used to obtain the referee voting result. The scoring pulse generation module 4 is used to generate a scoring pulse signal according to the referee voting result when it is necessary to add or subtract points. The score addition and subtraction module 5 is used to add or subtract points for the contestant who successfully answers according to the scoring pulse signal to obtain the score of each contestant. The digital tube display module 6 is used to display the countdown value output by the countdown module 2 and the score of each contestant output by the score addition and subtraction module 5. The host module 7 is used to output a quick answer control signal CLr at the beginning of the quick answer to reset the quick answer input module and the countdown module; and to send a score addition control signal ZC1 or a score subtraction control signal ZC2 to start the scoring pulse generation module when the score needs to be reset; and to send a score reset signal Z0 to the score addition and subtraction module when the score needs to be reset.

[0029] In this embodiment, the number of contestants is N. The N contestants are respectively recorded as the first to N contestants.

[0030] See also Figure 2 , Figure 2 The circuit structure diagram of the quick answer input module of the CPLD-based quick answer circuit of Example 1 of the utility model. Specifically, the quick answer input module includes N AND gates, N OR gates, N D flip-flops and an N-channel NOR gate. The N AND gates of the quick answer input module are respectively recorded as the 1st to Nth quick answer AND gates AND1 to ANDN. The N OR gates of the quick answer input module are respectively recorded as the 1st to Nth quick answer OR gates OR1 to ORN. The N D flip-flops are respectively recorded as the 1st to ND flip-flops. Each D flip-flop is provided with a trigger signal input terminal D, a clock signal input terminal CLK, a common-phase output terminal Q and a reset signal input terminal CLRN.

[0031] Each contestant has a corresponding quick answer signal input terminal, and the quick answer signal input terminal Ai is normally at a low level; when the i-th contestant presses the quick answer button, the quick answer signal input terminal Ai of the i-th contestant becomes a high level; i is any integer in the interval [1, N].

[0032] The first input end of the i-th quick-answer AND gate ANDi is connected to the quick-answer signal input end Ai of the i-th contestant, the second input end is connected to the output end of the N-channel OR gate NOR, and the output end is connected to the first input end of the i-th quick-answer OR gate; i is any integer in the interval [1,N].

[0033] The first input end of the i-th quick answer OR gate ORi is connected to the output end of the i-th quick answer AND gate, the second input end is connected to the in-phase output end Q of the i-th D trigger, and the output end is connected to the trigger signal input end D of the i-th D trigger; i is any integer in the interval [1,N].

[0034] The trigger signal input terminal D of the i-th D flip-flop is connected to the output terminal of the i-th quick answer OR gate ORi, the clock signal input terminal CLK is connected to the external clock signal, the reset signal input terminal CLRN is connected to the quick answer control signal CLr output by the host module, and the in-phase output terminal Q is connected to the i-th input terminal of the N-channel OR gate. The in-phase output terminal Q of the i-th D flip-flop is the i-th quick answer signal output terminal Yi.

[0035] The i-th input terminal of the N-channel NOR gate is connected to the in-phase output terminal Q of the i-th D flip-flop, and the output terminal is connected to the second input terminal of the i-th quick-answer AND gate; i is any integer in the interval [1, N]. The function of the N-channel NOR gate is to perform an NOR operation on the in-phase output terminals Q of the N D flip-flops, so that when the in-phase output terminal Q of any D flip-flop is at a high level (there is a contestant answering), the N-channel NOR gate outputs a low level, thereby making the output terminals of the N AND gates all become low levels. In the embodiment of N>2, only one two-channel NOR gate is used, and it is impossible to perform an NOR operation on the in-phase output terminals Q of the N D flip-flops at the same time. At this time, those skilled in the art can use N-2 cascaded two-channel OR gates and one two-channel NOR gate to achieve an effect equivalent to that of the N-channel NOR gate. The utility model does not limit the specific implementation of the N-channel NOR gate.

[0036] Based on the structure of the above-mentioned quick answer input module, the quick answer input module latches the quick answer signal sent by the first contestant to answer and invalidates the quick answer signals sent by other contestants as follows:

[0037] 1. In the initial state, the in-phase output terminal Q of each D flip-flop is low, and the output terminal of the N-channel NOR gate is high. Before the first quiz, the quiz signal input terminal corresponding to each contestant is low, so that the output terminal of each quiz AND gate is low, the output terminal of each quiz OR gate is low, and the trigger signal input terminal D of each D flip-flop is low.

[0038] 2. When the ith contestant presses the answer button for the first time, the answer signal input terminal Ai of the ith contestant becomes high level, causing the first input terminal of the ith answer AND gate to become high level. At this time, the output terminal of the N-channel OR gate is still high level, so the second input terminal of the ith answer AND gate is high level, and the answer signal sent by the ith contestant can cause the output terminal of the ith answer AND gate to change from low level to high level. After the output terminal of the ith answer AND gate becomes high level, the output terminal of the ith answer OR gate becomes high level, the trigger signal input terminal D of the ith D flip-flop becomes high level, and the in-phase output terminal Q of the ith D flip-flop becomes high level. The in-phase output terminal Q of the ith D flip-flop becomes high level, which means that the ith contestant has successfully answered. At this time, since the ith input terminal of the N-channel OR gate becomes high level, the output terminal of the N-channel OR gate changes from high level to low level.

[0039] After the in-phase output terminal Q of the ith D flip-flop becomes high level, if the ith contestant releases the quick answer button, the quick answer signal input terminal Ai of the ith contestant, the output terminal of the ith quick answer AND gate, and the first input terminal of the ith quick answer OR gate will return to low level. At this time, since the in-phase output terminal Q of the ith D flip-flop has become high level, the second input terminal of the ith quick answer OR gate becomes high level, so the output terminal of the ith quick answer OR gate will maintain a high level, so that the in-phase output terminal Q of the ith D flip-flop maintains a high level. That is, once the ith contestant successfully answers, the in-phase output terminal Q of the ith D flip-flop will maintain a high level and will no longer follow the level state of the quick answer signal input terminal Ai of the ith contestant.

[0040] 3. After the i-th contestant presses the answer button for the first time and the j-th contestant presses the answer button for the second time, the answer signal input terminal Aj of the j-th contestant becomes high level, and the first input terminal of the j-th answer AND gate becomes high level. However, at this time, the output terminal of the N-channel OR gate has become low level because the i-th contestant successfully answers, so the second input terminal of the j-th answer AND gate is low level, resulting in that no matter what level state the first input terminal of the j-th answer AND gate is, its output terminal is always low level. That is: the answer signal sent by the j-th contestant in the second answer will not cause the output terminal of the j-th answer AND gate to change from low level to high level. The output terminal of the j-th answer OR gate is still low level, the trigger signal input terminal D of the j-th D flip-flop is still low level, and the in-phase output terminal Q of the j-th D flip-flop is still low level. The answer signal sent by the j-th contestant in the second answer will not cause the in-phase output terminal Q of the j-th D flip-flop to become high level, which means that the answer of the j-th contestant in the second answer is invalid. Similarly, except for the i-th contestant who is answering for the first time, the answer signals sent by other contestants who are not answering for the first time are invalid.

[0041] 4. The reset signal input terminal CLRN of the D flip-flop is normally at a high level, and the in-phase output terminal Q of the D flip-flop normally follows the trigger signal input terminal D. When the host module outputs the answer control signal, the reset signal input terminal CLRN of the D flip-flop becomes a low level, and the in-phase output terminal Q of the D flip-flop is forced to become a low level (cleared). Therefore, the answer process of the quiz activity is summarized as follows: the host module sends a answer control signal, clears the answer results of the previous round, and the contestants start this round of answering. When the i-th contestant presses the answer button for the first time, the in-phase output terminal Q of the i-th D flip-flop corresponding to it remains at a high level, and the in-phase output terminals Q of the D flip-flops corresponding to other contestants remain at a low level. Until the host module sends a answer control signal again, the in-phase output terminals Q of all D flip-flops return to a low level, and the contestants start the next round of answering.

[0042] See also Figure 3 , Figure 3 The circuit structure diagram of the countdown module of the CPLD-based buzzer circuit of the utility model embodiment 1 is shown in FIG. Specifically, the countdown module includes a countdown counter, an n-channel OR gate ORa and a three-channel AND gate ANDa; n is the number of bits of the countdown counter.

[0043] The countdown counter includes a preset input terminal LDN, a countdown clock input terminal DN, a set terminal D1 to Dn, and a countdown count value output terminal Q1 to Qn. The set terminal D1 to Dn is used to configure the initial value of the countdown count value Q1 to Qn. When the preset input terminal LDN is at a low level, the countdown counter stops counting, and the countdown count value Q1 to Qn is reset to the initial value configured by the set terminal D1 to Dn. When the preset input terminal LDN is at a high level, each time a signal pulse on the countdown clock input terminal DN arrives, the countdown count value Q1 to Qn decreases by one unit.

[0044] The preset input terminal LDN of the countdown counter is connected to the answer control signal CLr output by the host module. The preset input terminal LDN of the countdown counter is normally high; when the host module sends the answer control signal CLr, it becomes low, and the countdown count values ​​Q1-Qn are reset to the initial value.

[0045] The down-counting clock input terminal DN of the countdown counter is connected to the output terminal of the three-channel AND gate ANDa. The countdown count values ​​Q1-Qn of the countdown counter are connected to the input terminal of the n-channel OR gate ORa; when the countdown count values ​​Q1-Qn are not equal to 0, the output terminal of the n-channel OR gate is high level; when the countdown count values ​​Q1-Qn are equal to 0, the output terminal of the n-channel OR gate is low level.

[0046] The first input end of the three-channel AND gate ANDa is connected to the external clock signal CLK, the second input end is connected to the output end of the n-channel OR gate, the third input end is connected to the output end of the N-channel OR gate NOR of the quick response input module, and the output end is connected to the down-counting clock input end DN of the countdown counter.

[0047] The n-channel OR gate ORa includes n input terminals, wherein the i'th input terminal is connected to the i'th count value output terminal Qi of the countdown counter, i' being any integer in the interval [1, n]. The output terminal of the n-channel OR gate is connected to the second input terminal of the three-channel AND gate.

[0048] The countdown module counts down from the beginning of the quick answer until the set quick answer time ends or a contestant answers the question, and the countdown stops as follows:

[0049] 1. Before the quiz begins, the preset input terminal LDN of the countdown counter is at a high level. At this time, the n-bit count values ​​Q1-Qn output by the countdown counter will not change, and the countdown has not yet begun.

[0050] 2. When the quiz starts, the host module outputs the quiz control signal CLr, and the preset input terminal LDN of the countdown counter becomes a low level. At this time, the n-bit count value Q1~Qn output by the countdown counter will change with the level state of the down-counting clock input terminal DN.

[0051] ① When the set answer time has not yet ended, the n-bit count value Q1~Qn is not equal to 0, and the output end of the n-channel OR gate is high, that is, the second input end of the three-channel AND gate is high. When no contestant answers, the output end of the N-channel OR gate of the answer input module is high, that is, the third input end of the three-channel AND gate is high. Therefore, when the set answer time has not yet ended and no contestant answers, the level state of the output end of the three-channel AND gate follows the level state of its first input end, that is, follows the clock signal CLK. Whenever a pulse of the clock signal CLK arrives, the n-bit count value Q1~Qn output by the countdown counter is reduced by one unit. At this time, the countdown module counts down normally, and the n-bit count value Q1~Qn output by the countdown counter can directly reflect the remaining answer time.

[0052] ② When the set answer time is over, the n-bit count value Q1~Qn output by the countdown counter is equal to 0, and the output end of the n-channel OR gate is low level, that is, the second input end of the three-channel AND gate is low level. When a contestant answers, the output end of the N-channel OR gate of the answer input module becomes low level, that is, the third input end of the three-channel AND gate is low level. Therefore, when the set answer time is over or a contestant answers, the output end of the three-channel AND gate is low level, which has nothing to do with the clock signal CLK. At this time, the countdown module stops counting, and the n-bit count value Q1~Qn output by the countdown counter remains unchanged.

[0053] Specifically, the circuit structure of the referee voting module depends on the judge scoring rules of the quiz activity. In this embodiment, the judge scoring rules of the quiz activity are: the jury consists of a chief referee and two deputy referees; if the chief referee agrees and any deputy referee agrees, the referee voting result is passed; if the chief referee agrees but both deputy referees disagree, the referee voting result is not passed; if the chief referee disagrees, then regardless of whether the deputy referees agree or not, the referee voting result is not passed.

[0054] See also Figure 4 , Figure 4 The circuit structure diagram of the referee voting module of the CPLD-based buzzer circuit of Example 1 of the utility model. Based on the judge scoring rules of this embodiment, the referee voting module 3 includes: a first NAND gate NAND1, a second NAND gate NAND2, and a third NAND gate NAND3. The first input end of the first NAND gate is connected to the chief referee voting signal Chief, and the second input end is connected to the first deputy referee voting signal Deputy1. The first input end of the second NAND gate is connected to the chief referee voting signal Chief, and the second input end is connected to the second deputy referee voting signal Deputy2. The first input end of the third NAND gate is connected to the output end of the first NAND gate, and the second input end is connected to the output end of the second NAND gate. The output end of the third NAND gate outputs the referee voting result JG.

[0055] The chief referee voting signal Chief is at a high level when the chief referee agrees, and at a low level when the chief referee disagrees. The two deputy referees are respectively recorded as the first deputy referee and the second deputy referee. The first deputy referee voting signal Deputy1 is at a high level when the first deputy referee agrees, and at a low level when the first deputy referee disagrees; the second deputy referee voting signal Deputy2 is at a high level when the second deputy referee agrees, and at a low level when the second deputy referee disagrees. The referee voting result JG includes two situations, pass and fail, which are represented by a high level and a low level respectively.

[0056] The working principle of the referee voting module in this embodiment to obtain the referee voting result is as follows:

[0057] 1. When the chief referee disagrees, the chief referee voting signal Chief is at a low level, so the first input terminals of the first and second NAND gates are both at a low level, and the output terminals of the first and second NAND gates are both at a high level, that is, the first input terminal and the second input terminal of the third NAND gate are both at a high level, and the output terminal of the third NAND gate is at a low level. Therefore, when the chief referee disagrees, no matter whether the deputy referee agrees or not, the referee voting result is not passed (low level).

[0058] 2. When the chief referee agrees but both the deputy referees disagree, the chief referee voting signal Chief is high, the first deputy referee voting signal deputy1 and the second deputy referee voting signal deputy2 are both low, that is, the second inputs of the first NAND gate and the second NAND gate are both low, and the outputs of the first NAND gate and the second NAND gate are both high, that is, the first input and the second input of the third NAND gate are both high, and the output of the third NAND gate is low. Therefore, when the chief referee agrees but both the deputy referees disagree, the referee voting result is also not passed (low).

[0059] 3. When the chief referee agrees and any one of the deputy referees agrees, the chief referee voting signal Chief is at a high level, the first deputy referee voting signal deputy1 or the second deputy referee voting signal deputy2 is at a high level, then the first input terminals of the first NAND gate and the second NAND gate are both at a high level, at least one of the second input terminals of the first NAND gate and the second NAND gate is at a high level, at least one of the output terminals of the first NAND gate and the second NAND gate is at a low level, that is, at least one of the first input terminal and the second input terminal of the third NAND gate is at a low level, and the output terminal of the third NAND gate is at a high level. Therefore, when the chief referee agrees and any one of the deputy referees agrees, the referee voting result is passed (high level).

[0060] In other embodiments with different judge scoring rules, those skilled in the art can design the circuit structure of the referee voting module as needed.

[0061] Specifically, the scoring pulse generating module 4 includes a score adding pulse generating module 41 and a score subtracting pulse generating module 42. The score adding pulse generating module 41 generates a score adding pulse signal Uclk according to a score adding control signal ZC1 issued by the host module and a referee voting result JG. The score subtracting pulse generating module 41 generates a score subtracting pulse signal Dclk according to a score subtracting control signal ZC2 issued by the host module and a referee voting result JG. The circuit structure and working principle of the score adding pulse generating module 41 and the score subtracting pulse generating module 42 are basically the same, and the circuit structure and working principle of the score subtracting pulse generating module will be specifically described below.

[0062] See also Figure 5 , Figure 5 The circuit structure diagram of the subtraction pulse generation module of the CPLD-based buzzer circuit of the utility model embodiment 1. The subtraction pulse generation module 42 includes a pulse number counter, a first NOT gate INV1, a second NOT gate INV2, a third NOT gate INV3, a first AND gate ANDb1, a second AND gate ANDb2 and a third AND gate ANDb3.

[0063] The pulse counter includes a clock signal input terminal CLK, a pulse count value output terminal Q1~Qn, a reset terminal CLRN, and a count control terminal ENF. When the reset terminal CLRN is at a high level and the count control terminal ENF is at a high level, the pulse counter counts normally; each time a signal pulse on the clock signal input terminal CLK arrives, the pulse count values ​​Q1~Qn increase by one unit. When the reset terminal CLRN is at a low level, the pulse counter stops counting, and the pulse count values ​​Q1~Qn are reset. When the count control terminal ENF is at a low level, the pulse counter stops counting and keeps the pulse count value unchanged.

[0064] The deduction control signal ZC2 issued by the host module is connected to the first input end of the first AND gate ANDb1, the referee voting result JG is connected to the second input end of the first AND gate ANDb1 through the first NOT gate INV1, and the output end of the first AND gate ANDb1 is connected to the reset end CLRN of the pulse number counter.

[0065] The input end of the second NOT gate INV2 is connected to the pulse count value output end of the pulse counter, and the output end is connected to the count control end ENF of the pulse counter. The connection mode between the input end of the second NOT gate INV2 and the pulse count value output end of the pulse counter depends on the number of pulses contained in the set subtraction pulse signal Dclk. The number of pulses contained in the subtraction pulse signal Dclk depends on the addition and subtraction rules of the quiz activity. In this embodiment, the addition and subtraction rules of the quiz activity are: each time the host module sends out a subtraction control signal, the contestant will get +4 points or -4 points. Therefore, the number of pulses contained in the subtraction pulse signal Dclk is set to 4; and the pulse count value corresponding to "4" is "100", so in this embodiment, the input end of the first NOT gate is connected to the third bit Q3 of the pulse count value of the pulse counter. In other embodiments, if the number of pulses included in the subtraction pulse signal Dclk is set to 15 (the corresponding pulse count value is "1111"); then the input end of the second NOT gate INV2 can be simultaneously connected to the 1st to 4th bits Q1 to Q4 of the pulse count value of the pulse counter through a four-channel AND gate. Those skilled in the art can adjust the connection method between the input end of the second NOT gate INV2 and the pulse count value output end of the pulse counter as required, and the utility model does not specifically limit it.

[0066] The first input terminal of the second AND gate ANDb2 is connected to the reset terminal CLRN of the pulse counter, the second input terminal is connected to the external clock signal CLK2, and the output terminal is connected to the clock signal input terminal CLK of the pulse counter through the third NOT gate INV3.

[0067] The first input end of the third AND gate ANDb3 is connected to the count control end ENF of the pulse counter, the second input end is connected to the output end of the second AND gate ANDb2, and the output end outputs a subtraction pulse signal Dclk. The subtraction pulse signal Dclk will be transmitted to the subsequent addition and subtraction module, and the addition and subtraction module will subtract points from the contestant according to the subtraction pulse signal Dclk.

[0068] The working principle of the subtraction pulse generation module to generate a subtraction pulse signal when subtraction is required is as follows:

[0069] 1. When it is not necessary to deduct points, the deduct point control signal ZC2 is at a low level, or the referee voting result JG is at a high level. At this time, the output end of the first AND gate ANDb1 is at a low level, and the reset end CLRN of the pulse counter and the first input end of the second AND gate ANDb2 are both at a low level. The output end of the second AND gate ANDb2 is at a low level, and the clock signal input end CLK of the pulse counter remains at a high level. At this time, the pulse counter stops counting, and the pulse count value is reset.

[0070] 2. When deduction is required, the deduction control signal ZC2 becomes high level, and the referee voting result JG is low level. At this time, both input terminals of the first AND gate ANDb1 are high level, resulting in the reset terminal CLRN of the pulse counter and the first input terminal of the second AND gate ANDb2 being high level. The level state of the output terminal of the second AND gate ANDb2 follows the external clock signal CLK2, and the level state of the clock signal input terminal CLK of the pulse counter is opposite to the external clock signal CLK2. At this time, the pulse counter starts counting, and each time a signal pulse on the clock signal input terminal CLK arrives, the pulse count value increases by one unit.

[0071] 3. In the initial state, the input end of the second invertor INV2 is at a low level, and the output end is at a high level, that is, the counting control end ENF of the pulse counter is at a high level, and the first input end of the third AND gate ANDb3 is at a high level. During this period, the pulse counter counts normally; the level state of the output end of the third AND gate ANDb3 follows the level state of its second input end, that is, follows the level state of the output end of the second AND gate ANDb2, that is, follows the external clock signal CLK2. At this time, the output end of the third AND gate ANDb3 outputs a subtraction pulse signal Dclk.

[0072] 4. After the third AND gate ANDb3 outputs the set number of pulses included in the subtraction pulse signal Dclk, the pulse count value increases to the binary code corresponding to the set number of pulses. At this time, the input end of the second NOT gate becomes high level and the output end becomes low level, that is, the counting control end ENF of the pulse counter becomes low level, and the first input end of the third AND gate becomes low level. Therefore, the pulse counter stops counting and the pulse count value remains unchanged. The output end of the third AND gate remains low level and stops outputting the subtraction pulse signal Dclk. Until the next time the subtraction control signal ZC2 becomes low level, the output end of the first AND gate ANDb1 becomes low level, the reset end CLRN of the pulse counter becomes low level, and the pulse count value is reset. Until the next time the subtraction control signal ZC2 changes from low level to high level and the referee voting result JG is low level, the subtraction pulse signal Dclk can be output again.

[0073] See also Figure 6 , Figure 6 Schematic diagram of the circuit structure of the plus pulse generation module of the CPLD-based buzzer circuit of Example 1 of the utility model. The circuit structure of the plus pulse generation module 41 is basically the same as that of the minus pulse generation module 42, except that: the plus pulse generation module 41 does not include the first invertor INV1; the plus control signal ZC1 is connected to the first input end of the first AND gate ANDb1; the referee voting result JG is directly connected to the second input end of the first AND gate ANDb1; the output end of the third AND gate ANDb3 outputs the plus pulse signal Uclk. When the plus control signal ZC1 is at a high level and the referee voting result JG is at a high level, the plus pulse generation module 41 outputs a plus pulse signal Uclk with a set number of pulses to be transmitted to the subsequent plus and minus modules. The working principle of the plus pulse generation module 41 is basically the same as that of the minus pulse generation module 42, and the utility model will not repeat it.

[0074] Specifically, there are N score addition and subtraction modules, each corresponding to N contestants, and each of them is recorded as the first to N score addition and subtraction modules. Figure 7 , Figure 7 The circuit structure diagram of the addition and subtraction module of the CPLD-based buzzer circuit of the utility model embodiment 1. Each of the addition and subtraction modules 5 includes an addition and subtraction counter, a first addition and subtraction NAND gate NANDa1 and a second addition and subtraction NAND gate NANDa2.

[0075] The addition and subtraction counter includes a preset input terminal LDN, an addition counting clock input terminal UP, a subtraction counting clock input terminal DN, a setting terminal D1~Dn and a score output terminal Q1~Qn. The score output terminal Q1~Qn outputs the score of the corresponding contestant. When the preset input terminal LDN is at a low level, the score output by the score output terminal is restored to the initial value configured by the setting terminal D1~Dn. When a signal pulse on the addition counting clock input terminal UP arrives, the score output by the score output terminal increases by one unit. When a signal pulse on the subtraction counting clock input terminal DN arrives, the score output by the score output terminal decreases by one unit.

[0076] The preset input terminal LDN of the score addition and subtraction counter is connected to the score reset signal Z0 issued by the host module. The score reset signal Z0 is normally high level and becomes low level when the score needs to be reset.

[0077] The first input ends of the first addition and subtraction points NANDa1 and the second addition and subtraction points NANDa2 are both connected to the in-phase output end of the D flip-flop corresponding to the contestant in the quick answer input module. For example, the i-th addition and subtraction module corresponds to the i-th contestant, then the first input ends of the first addition and subtraction points NANDa1 and the second addition and subtraction points NANDa2 of the i-th addition and subtraction module are both connected to the in-phase output end Yi of the i-th D flip-flop; i is any integer in the interval [1, N]. The second input end of the first addition and subtraction points NANDa1 is connected to the subtraction pulse signal Dclk, and the output end is connected to the subtraction clock input end DN of the addition and subtraction counter. The second input end of the second addition and subtraction points NANDa2 is connected to the addition pulse signal Uclk, and the output end is connected to the addition clock input end UP of the addition and subtraction counter.

[0078] The working principle of the score addition and subtraction module is as follows: when the i-th contestant successfully answers, the in-phase output terminal Yi of the i-th D flip-flop corresponding to it becomes high level, and the first input terminals of the first score addition and subtraction NAND gate NANDa1 and the second score addition and subtraction NAND gate NANDa2 are high level. At this time, if the host module sends a score addition control signal ZC1 or a score subtraction control signal ZC2, the scoring pulse generation module outputs a score addition pulse signal Uclk or a score subtraction pulse signal Dclk, causing the up-counting clock input terminal UP or the down-counting clock input terminal DN of the score addition and subtraction counter to receive a signal of the set number of pulses, and the score output by the score output terminal increases or decreases accordingly. For other contestants who did not successfully answer, the in-phase output terminals of the corresponding D flip-flops are low level, so the first input terminals of the first score addition and subtraction NAND gate NANDa1 and the second score addition and subtraction NAND gate NANDa2 of the corresponding score addition and subtraction module are low level, and the score addition pulse signal Uclk or the score subtraction pulse signal Dclk cannot be transmitted to the up-counting clock input terminal UP or the down-counting clock input terminal DN of the score addition and subtraction counter. Therefore, the scores of other contestants will not change with the score increase control signal ZC1 or the score reduction control signal ZC2.

[0079] When the host module sends a score reset signal Z0, the preset input terminal LDN of the addition and subtraction counter becomes low level, and the scores of all contestants are reset to the initial value. By configuring the setting terminals D1 to Dn of the addition and subtraction counter, the initial value of the score can be adjusted.

[0080] Specifically, the digital tube display module 6 includes a 7448 decoder and a digital tube. The countdown count value output by the countdown module 2 and the score output by the addition and subtraction module are connected to corresponding digital tubes through the 7448 decoder respectively. In one embodiment, the score output by the addition and subtraction module corresponding to each contestant is connected to a group of digital tubes through the 7448 decoder, and the scores of all contestants can be displayed at the same time. In another embodiment, the score output by the addition and subtraction module corresponding to each contestant is multiplied by the corresponding answer signal Yi, and the product is connected to a unique group of digital tubes through an OR gate, and only the score of the contestant who successfully answers can be displayed, thereby saving digital tubes and reducing costs.

[0081] Example 2

[0082] The CPLD-based buzzer circuit of Example 2 of the utility model is basically the same as Example 1, except that: the number of contestants N is 2; the number of digits of the countdown counter and the addition and subtraction counter are both 8; and the number of digits of the pulse number counter is 4.

[0083] In this embodiment, the D flip-flop of the answer input module is implemented by a 7474 chip. Figure 8 , Figure 8 The circuit structure diagram of the answer input module of the CPLD-based answer circuit of Example 2 of the utility model. In the figure, A1 and A2 respectively represent the answer signal input terminal A1 of the first contestant and the answer signal input terminal A2 of the second contestant. The 7474 chip integrates two D flip-flops, namely the first D flip-flop and the second D flip-flop. In the figure, Y1 and Y2 respectively represent the in-phase output terminal Q of the first D flip-flop and the in-phase output terminal Q of the second D flip-flop. The N-channel NOR gate NOR is a two-channel NAND gate, whose first input terminal is connected to the in-phase output terminal Y1 of the first D flip-flop, and whose second input terminal is connected to the in-phase output terminal Y2 of the second D flip-flop.

[0084] In this embodiment, the countdown counter is implemented by two cascaded 74192 counter chips. Fig. 9 , Fig. 9 The circuit structure diagram of the countdown module of the CPLD-based buzzer circuit of Example 2 of the utility model. The two cascaded 74192 counter chips are respectively recorded as the first 74192 counter 74192-1 and the second 74192 counter 74192-2. As shown in the figure, the preset input terminals LDN of the first 74192 counter 74192-1 and the second 74192 counter 74192-2 are both connected to the buzzer control signal CLr output by the host module. The down-counting clock input terminal DN of the first 74192 counter 74192-1 is connected to the output terminal of the three-channel AND gate, the carry output terminal CO is connected to the up-counting clock input terminal UP of the second 74192 counter 74192-2, and the borrow output terminal BO is connected to the down-counting clock input terminal DN of the second 74192 counter 74192-2. The 4-bit count values ​​QA, QB, QC and QD outputted by the first 74192 counter 74192-1 respectively represent the lower 4 bits of the 8-bit countdown values ​​Q1 to Q8. The 4-bit count values ​​QA, QB, QC and QD outputted by the second 74192 counter respectively represent the higher 4 bits of the 8-bit count values ​​Q1 to Q8.

[0085] By controlling the level state of the number setting end of the first 74192 counter 74192-1 and the second 74192 counter 74192-2, the rush answer time can be set. For example, in this embodiment, the second number setting end B of the second 74192 counter 74192-2 is connected to a high level, and the other number setting ends are all suspended, so the countdown module will count down with 0010 0000 as the initial value. By controlling the level state of the number setting end of the counter, the initial value at the start of the countdown can be adjusted, and then the rush answer time can be set.

[0086] In this embodiment, the pulse number counter is implemented by a 4-bit 74161 counter chip. Fig.10 , Fig.10 The circuit structure diagram of the subtraction pulse generation module of the CPLD-based buzzer circuit of Example 2 of the utility model. As shown in the figure, the reset terminal CLRN of the 74161 counter is connected to the output terminal of the first AND gate ANDb1. The 74161 counter includes a carry output terminal RCC. The settable range of the number of pulses included in the subtraction pulse signal Dclk is [1,16]. When the number of pulses included in the set subtraction pulse signal Dclk is 16, the input terminal of the first NOT gate can be connected to the carry output terminal RCC of the 74161 counter.

[0087] In this embodiment, the addition and subtraction counter is implemented by two cascaded 74192 counter chips. Fig.11 , Fig.11 The circuit structure diagram of the addition and subtraction module of the CPLD-based buzzer circuit of Example 2 of the utility model. The two cascaded 74192 counter chips constituting the addition and subtraction counter are respectively the third 74192 counter 74192-3 and the fourth 74192 counter 74192-4. As shown in the figure, the preset input terminals LDN of the third 74192 counter 74192-3 and the fourth 74192 counter 74192-4 are both connected to the score reset signal Z0 issued by the host module. The subtraction count clock input terminal DN of the third 74192 counter 74192-3 is connected to the output terminal of the first addition and subtraction NAND gate NANDa1, and the addition count clock input terminal UP is connected to the output terminal of the second addition and subtraction NAND gate NANDa2. The carry output terminal CO of the third 74192 counter 74192-3 is connected to the up-count clock input terminal UP of the fourth 74192 counter 74192-4, and the borrow output terminal BO is connected to the down-count clock input terminal DN of the fourth 74192 counter 74192-4. The first set terminal A and the third set terminal C of the fourth 74192 counter 74192-4 are connected to a high level, and the other set terminals are all suspended, so the set initial value of the fraction is "0101 0000".

[0088] The utility model has the following technical effects: the CPLD-based buzzer circuit of the utility model is implemented by CPLD (Complex Programming Logic Device) and Quartus II, and has programmability, so it can break through the limitations of existing laboratory components and increase flexibility for digital electronic technology experimental teaching. Furthermore, the CPLD-based buzzer circuit of the utility model has comprehensive functions, and compared with the traditional buzzer circuit, it adds an integrated design of referee scoring and contestant addition and subtraction of points, and has wider versatility.

[0089] The above-mentioned embodiments only express several implementation methods of the utility model, and the description is relatively specific and detailed, but it cannot be understood as limiting the scope of the utility model patent. It should be pointed out that for ordinary technicians in this field, several modifications and improvements can be made without departing from the concept of the utility model, and the utility model is also intended to include these modifications and modifications.

Claims

1. A CPLD-based answering circuit, characterized in that: Including quick answer input module and host module; The host module is used to output a rush-answer control signal to reset the rush-answer input module when the rush-answer begins; The quick answer input module includes: N AND gates, N OR gates, N D flip-flops and N channel NOR gates; N is the number of contestants; the N AND gates of the quick answer input module are respectively recorded as the 1st to Nth quick answer AND gates; the N OR gates are respectively recorded as the 1st to Nth quick answer OR gates; the N D flip-flops are respectively recorded as the 1st to ND flip-flops; each D flip-flop is provided with a trigger signal input terminal, a clock signal input terminal, a common-phase output terminal and a reset signal input terminal; The first input end of the i-th quick answer AND gate is connected to the quick answer signal input end of the i-th contestant, the second input end is connected to the output end of the N-channel OR gate, and the output end is connected to the first input end of the i-th quick answer OR gate; The first input end of the i-th quick answer OR gate is connected to the output end of the i-th quick answer AND gate, the second input end is connected to the in-phase output end of the i-th D trigger, and the output end is connected to the trigger signal input end of the i-th D trigger; The trigger signal input end of the i-th D flip-flop is connected to the output end of the i-th answer OR gate, the clock signal input end is connected to the external clock signal, the reset signal input end is connected to the answer control signal output by the host module, and the in-phase output end is connected to the i-th input end of the N-channel OR gate; the in-phase output end of the i-th D flip-flop is the i-th answer signal output end; The i-th input terminal of the N-channel NOR gate is connected to the in-phase output terminal of the i-th D flip-flop, and the output terminal is connected to the second input terminal of the i-th quick-answer AND gate; i is any integer in the interval [1, N].

2. The CPLD-based answering circuit according to claim 1, characterized in that: It also includes a countdown module; the answer control signal output by the host module is also used to reset the countdown module; The countdown module includes: a countdown counter, an n-channel OR gate and a three-channel AND gate; n is the number of bits of the countdown counter; The countdown counter comprises a preset input terminal, a down-counting clock input terminal and a countdown count value output terminal; The preset input end of the countdown counter is connected to the answer control signal output by the host module; The down-count clock input terminal of the countdown counter is connected to the output terminal of the three-channel AND gate; the countdown count value of the countdown counter is connected to the input terminal of the n-channel OR gate; only when the countdown count value is equal to 0, the output terminal of the n-channel OR gate is at a low level; The first input end of the three-channel AND gate is connected to the external clock signal, the second input end is connected to the output end of the n-channel OR gate, the third input end is connected to the output end of the N-channel OR gate of the quick answer input module, and the output end is connected to the down-counting clock input end of the countdown counter; The n-channel or gate comprises n input terminals, wherein the i'th input terminal is connected to the i'th count value output terminal of the countdown counter, and i' is any integer in the interval [1, n].

3. The CPLD-based answering machine circuit according to claim 2, characterized in that: It also includes a referee voting module, a scoring pulse generation module and a score addition and subtraction module; the referee voting module is used to obtain the referee voting result; the host module is also used to send a score addition control signal or a score subtraction control signal when it is necessary to add or subtract points; The scoring pulse generating module includes a score adding pulse generating module and a score subtracting pulse generating module; the score adding pulse generating module generates a score adding pulse signal according to the score adding control signal sent by the host module and the referee voting result; the score subtracting pulse generating module generates a score subtracting pulse signal according to the score subtracting control signal sent by the host module and the referee voting result; The score adding and subtracting module is used to add or subtract points for the contestants who successfully answer the questions according to the score adding control signal or the score subtracting control signal, so as to obtain the score of each contestant.

4. The CPLD-based answering machine circuit according to claim 3, characterized in that: The subtraction pulse generation module includes a pulse number counter, a first NOT gate, a second NOT gate, a third NOT gate, a first AND gate, a second AND gate and a third AND gate; The pulse number counter comprises a clock signal input terminal, a pulse number count value output terminal, a reset terminal and a count control terminal; The deduction control signal sent by the host module is connected to the first input end of the first AND gate, the referee voting result is connected to the second input end of the first AND gate through the first NOT gate, and the output end of the first AND gate is connected to the reset end of the pulse number counter; The input end of the second NOT gate is connected to the pulse count value output end of the pulse counter, and the output end is connected to the count control end of the pulse counter; the connection mode between the input end of the second NOT gate and the pulse count value output end of the pulse counter depends on the number of pulses contained in the set subtraction pulse signal; The first input end of the second AND gate is connected to the reset end of the pulse counter, the second input end is connected to the external clock signal, and the output end is connected to the clock signal input end of the pulse counter through the third NOT gate; The first input end of the third AND gate is connected to the counting control end of the pulse number counter, the second input end is connected to the output end of the second AND gate, and the output end outputs a subtraction pulse signal.

5. The CPLD-based answering machine circuit according to claim 4, characterized in that: The host module is also used to send a score reset signal when the score needs to be reset; The addition and subtraction module includes: an addition and subtraction counter, a first addition and subtraction NAND gate and a second addition and subtraction NAND gate; The addition and subtraction counter includes a preset input terminal, an addition counting clock input terminal, a subtraction counting clock input terminal and a fraction output terminal; The preset input end of the addition and subtraction counter is connected to the score reset signal sent by the host module; The first input ends of the first addition and subtraction points NAND gate and the second addition and subtraction points NAND gate are both connected to the in-phase output end of the D flip-flop corresponding to the contestant in the quick answer input module; The second input end of the first addition-subtraction NAND gate is connected to the subtraction pulse signal, and the output end is connected to the subtraction counting clock input end of the addition-subtraction counter; The second input end of the second addition-subtraction NAND gate is connected to the addition pulse signal, and the output end is connected to the addition counting clock input end of the addition-subtraction counter.

6. The CPLD-based answering machine circuit according to claim 5, characterized in that: It also includes a digital tube display module; the digital tube display module includes a 7448 decoder and a digital tube; the countdown count value output by the countdown module and the score output by the addition and subtraction module are connected to the corresponding digital tubes through the 7448 decoder respectively.

7. The CPLD-based answering circuit according to claim 6, characterized in that: The D trigger of the quick answer input module is implemented by a 7474 chip; The countdown module and countdown counter are implemented by two cascaded 74192 counter chips; The pulse number counter of the subtraction pulse generation module is implemented by a 74161 counter chip; The addition and subtraction counter of the addition and subtraction module is implemented by two cascaded 74192 counter chips.

8. The CPLD-based answering machine circuit according to claim 3, characterized in that: The referee voting module includes: a first NAND gate, a second NAND gate, and a third NAND gate; the first input end of the first NAND gate is connected to the voting signal of the chief referee, and the second input end is connected to the voting signal of the first deputy referee; the first input end of the second NAND gate is connected to the voting signal of the chief referee, and the second input end is connected to the voting signal of the second deputy referee; the first input end of the third NAND gate is connected to the output end of the first NAND gate, and the second input end is connected to the output end of the second NAND gate; the output end of the third NAND gate outputs the referee voting result.

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