Feedback comparison type ADC circuit with high conversion speed
By introducing internal hysteresis circuit and gear registers into feedback comparison ADCs, and adjusting gear value through multiple comparison results, the problem of slow conversion speed of traditional ADCs is solved, and faster conversion speed and higher efficiency are achieved. Ability to process high frequency input signals.
Patent Information
- Application Number
- CN202421049912.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-05-15
- Publication Date
- 2025-01-07
- Estimated Expiration
- 2034-05-15
AI Technical Summary
The conversion speed of traditional feedback comparison ADCs is slow and cannot effectively process high-frequency input signals because they can only change one step at a time, resulting in slow conversion process and low efficiency.
Use a comparator and gear register with internal hysteresis circuit. By recording the current, last and last comparison results, adjust the value of the gear register. If the three comparison results are the same, the gear register will be upshifted, and if the three comparison results are different, the gear register will be downshifted. , reduce the number of comparison feedback times and improve the conversion speed.
It significantly improves the conversion speed of feedback comparison ADC, can process faster frequency input signals, greatly reduces the number of comparison feedback times, improves work efficiency, and achieves faster analog-to-digital conversion.
Smart Images
Figure CN222321511U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of feedback comparison circuits, in particular to a feedback comparison type ADC circuit with fast conversion speed. Background Art
[0002] ADC is the abbreviation of analog-to-digital converter (or AD converter). ADC is a device that converts analog quantities into digital quantities. Its common application is to convert continuously changing voltage values into digital quantities. The principle is the sampling principle, which can be simply understood as sampling the voltage value at a certain frequency to convert the continuous value into a discrete value, thus obtaining a number of digital quantities.
[0003] The principle of the traditional feedback comparison ADC is that the output of the DIGITAL is converted into an analog quantity through the DAC, and the input signal is compared with this analog quantity. The result of the calculation is sent back to the DIGITAL module for processing. If the input signal is large (or small), the output of the DIGITAL is increased (or decreased) by 1, and the analog quantity converted by the DAC will also increase (or decrease). Then it is compared with the input signal again, and this process is repeated until the output of the DAC is equal to the input signal. At this time, the output in the register is the digital quantity after the input signal is converted. The conversion speed of this ADC is slow. In the most extreme case, it takes 2 to the power of n cycles to complete the conversion. If the input signal frequency is high, this ADC will not keep up with the input signal because it can only change one step at a time and cannot "shift gears". The conversion speed of the traditional feedback comparison ADC is slow. Utility Model Content
[0004] The utility model aims to solve the shortcomings in the prior art and proposes a feedback comparison ADC circuit with fast conversion speed.
[0005] In order to achieve the above-mentioned purpose, the utility model adopts the following technical scheme: a feedback comparison ADC circuit with fast conversion speed, comprising a signal output end, the signal output end is connected to the A end of the comparator, the C end of the comparator is connected to a digital module, one end of the digital module is connected to a register, one end of the register is connected to a digital-to-analog converter, one end of the digital-to-analog converter is connected to the B end of the comparator, the digital module comprises a gear register, and one end of the gear register is connected to a result register.
[0006] As a further description of the above technical solution:
[0007] The comparator has an internal hysteresis circuit.
[0008] As a further description of the above technical solution:
[0009] The initial increment value of the gear register is 1, and the continuous increment value of the gear register is 2. n-2 .
[0010] As a further description of the above technical solution:
[0011] The digital module can record the current, last and last comparison results.
[0012] As a further description of the above technical solution:
[0013] The signal sent by the signal output terminal is a digital signal.
[0014] The utility model has the following beneficial effects:
[0015] 1. In the utility model, the value of the gear register is adjusted together through the current result, the last comparison result, and the last comparison result. If the results of the three comparisons are the same, the gear is "upgraded" and the value of the gear register is increased. The increase of the gear register makes the result register increase (or decrease) faster. If the results of the three comparisons are different, it means that the analog signal of the output of the result register after DAC conversion is close to the input signal. At this time, the gear is "downgraded" and the gear register is waited for to drop to the lowest gear. The analog-to-digital conversion is completed, which greatly reduces the number of comparison feedbacks, has a fast conversion speed, improves work efficiency, and can process input signals with a faster frequency. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] Figure 1 This is a principle block diagram of a feedback comparison ADC circuit with fast conversion speed proposed by the utility model;
[0017] Figure 2 This is a partial principle block diagram of a feedback comparison ADC circuit with fast conversion speed proposed by the utility model;
[0018] Figure 3 This is the functional block diagram of a traditional feedback comparator ADC.
[0019] Legend:
[0020] 1. Signal output terminal; 2. Comparator; 3. Digital module; 4. Register; 5. Digital-to-analog converter; 6. Gear register; 7. Result register. DETAILED DESCRIPTION
[0021] The following will be combined with the drawings in the embodiments of the utility model to clearly and completely describe the technical solutions in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments in the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.
[0022] Reference Figure 1-Figure 3 The utility model provides an embodiment: a feedback comparison ADC circuit with fast conversion speed, including a signal output terminal 1, the signal output terminal 1 is connected to the A terminal of a comparator 2, the C terminal of the comparator 2 is connected to a digital module 3, one end of the digital module 3 is connected to a register 4, one end of the register 4 is connected to a digital-to-analog converter 5, one end of the digital-to-analog converter 5 is connected to the B terminal of the comparator 2, the digital module 3 includes a gear register 6, one end of the gear register 6 is connected to a result register 7, according to the current result, the last comparison result, and the last comparison result, the value of the gear register 4 is adjusted together, if the results of the three comparisons are the same, then "upshift", the value of the gear register 4 increases, the increase of the gear register 6 makes the result register 7 increase (or decrease) faster, if the results of the three comparisons are different, it means that the output of the result register 7 is converted by the digital-to-analog converter 5. The analog-to-digital conversion is completed at this time, waiting for the gear register 6 to drop to the lowest gear.
[0023] Comparator 2 has an internal hysteresis circuit. The initial increase of gear register 6 is 1, and the continuous increase of gear register 6 is 2. n-2 The digital module 3 can record the current, last, and last comparison results. The signal sent by the signal output terminal 1 is a digital signal. The digital module 3 adjusts the value of the gear register 4. If the results of the three comparisons are the same, it is "upshifted", the value of the gear register 4 increases, and the increase of the gear register 6 makes the result register 7 increase (or decrease) faster. If the results of the three comparisons are different, it means that the output of the result register 7 is converted by the digital-to-analog converter 5. The analog signal is close to the input signal, which significantly improves the conversion speed of the feedback comparison ADC, can process faster frequency input signals, greatly reduces the number of comparison feedbacks, has a fast conversion speed, and improves work efficiency.
[0024] Working principle: The traditional feedback comparison ADC only adjusts the value of result register 7 according to the current comparison result. This patent also records the last and last comparison results, such as Figure 2, according to the current result, the last comparison result, and the last comparison result, the value of the gear register 4 is adjusted together. If the results of the three comparisons are the same, then "upshift", the value of the gear register 4 increases, and the increase of the gear register 6 makes the result register 7 increase (or decrease) faster. If the results of the three comparisons are different, it means that the analog signal converted by the digital-to-analog converter 5 of the output of the result register 7 is close to the input signal, and then "downshift" is performed, waiting for the gear register 6 to drop to the lowest gear, and the analog-to-digital conversion is completed. At this time, the result is The output of register 7 is the digital value after the input signal is converted. We simulate a conversion process. Assuming that the input signal is 1050, the initial value of register 4 is 1000 (if a traditional feedback comparison ADC is used, 50 cycles are required). In the first comparison, 1050>1000, register 4 adds 1 and becomes 1001; in the second comparison, 1050>1001, register 4 adds 1 and becomes 1002; in the third comparison, 1050>1002, register 4 adds 2 and becomes 1004 (upshift); in the fourth comparison, 1050>1004, register 4 plus 4, becomes 1008, (upgrade); the fifth comparison, 1050>1008, register 4 plus 8, becomes 1016, (upgrade); the sixth comparison, 1050>1016, register 4 plus 16, becomes 1032, (upgrade); the seventh comparison, 1050>1032, register 4 plus 32, becomes 1064, (upgrade); the eighth comparison, 1050<1064, register 4 minus 16, becomes 1048, (downgrade), at this time the value of register 4 has After being approximately equal to the input signal; the 9th comparison, 1050>1048, register 4 plus 8, becoming 1056, (downshift); the 10th comparison, 1050<1056, register 4 minus 4, becoming 1052, (downshift); the 11th comparison, 1050<1052, register 4 minus 2, becoming 1050, (downshift); the 12th comparison, 1050=1050, the conversion is completed. It can be seen that this scheme will significantly improve the conversion speed of the feedback comparison ADC and can handle input signals with faster frequency.
[0025] Finally, it should be noted that the above is only a preferred embodiment of the present invention and is not intended to limit the present invention. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art can still modify the technical solutions described in the aforementioned embodiments or make equivalent substitutions for some of the technical features therein. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.
Claims
1. A feedback comparison ADC circuit with fast conversion speed, comprising a signal output terminal (1), characterized in that: The signal output end (1) is connected to the A end of the comparator (2), the C end of the comparator (2) is connected to the digital module (3), one end of the digital module (3) is connected to the register (4), one end of the register (4) is connected to the digital-to-analog converter (5), one end of the digital-to-analog converter (5) is connected to the B end of the comparator (2), the digital module (3) comprises a gear register (6), one end of the gear register (6) is connected to the result register (7).
2. The feedback comparison ADC circuit with fast conversion speed according to claim 1, characterized in that: The comparator (2) has an internal hysteresis circuit.
3. The feedback comparison ADC circuit with fast conversion speed according to claim 1, characterized in that: The initial increase or decrease value of the gear register (6) is 1, and the continuous increase or decrease value of the gear register (6) is 2 n-2 .
4. The feedback comparison ADC circuit with fast conversion speed according to claim 1, characterized in that: The digital module (3) can record the current, last and last comparison results.
5. The feedback comparison ADC circuit with fast conversion speed according to claim 1, characterized in that: The signal sent by the signal output terminal (1) is a digital signal.