Dynamic non-return-to-zero differential signal side channel decoding device based on optoelectronic isolation

Abstract

The utility model discloses a dynamic non-return-to-zero differential signal side channel decoding device based on optoelectronic isolation. The dynamic non-return-to-zero differential signal side channel decoding device comprises an MCU module circuit, an IO driving buffer circuit, a high-speed optoelectronic isolation amplification circuit, a differential signal bypass acquisition interface, an analog switch circuit, an external FLASH storage circuit and a power supply / UART. The analog switch circuit is electrically connected with the differential signal bypass acquisition interface, the differential signal bypass acquisition interface is electrically connected with the high-speed photoelectric isolation amplification circuit, the high-speed photoelectric isolation amplification circuit is electrically connected with the IO driving buffer circuit and the analog switch circuit, and the IO driving buffer circuit is connected with the MCU module circuit. The MCU module circuit is electrically connected with the analog switch circuit; and the external FLASH storage circuit and the power supply / UART are electrically connected with the MCU module circuit. According to the utility model, reverse decoding analysis is carried out on a dynamic non-return-to-zero differential signal transmission mode in a side channel zero-interference bypass monitoring intervention mode on the premise of not interfering a detected object, and decoded data are immediately stored to local storage.

Description

Technical Field

[0001] The utility model relates to the technical field of intercommunication, and in particular to a dynamic non-return-to-zero differential signal side channel decoding device based on photoelectric isolation. Background Art

[0002] Differential signal transmission is widely used in various underlying communication chips, communication interfaces and communication devices due to its remarkable characteristics such as high stability, high anti-interference, long-distance communication, high speed and low bit error rate. For example, Ethernet, USB, RS485, RS422, CAN and other interface communications can be used for normal communication interface data interaction. Differential signals can also be transmitted in one direction to drive some special applications that are not intended for two-way data interaction.

[0003] There are two main transmission modes of differential signal: static differential signal and dynamic non-return-to-zero scanning differential signal. Most of the actual applications are based on the former. Dynamic non-return-to-zero scanning differential signal transmission is generally common in scenarios where unidirectional transmission drives certain specific objects. It can be seen that the importance and status of differential signals in the field of electronic technology are self-evident. It is particularly important and urgent to conduct reverse decoding analysis and research on differential signals from a bottom-level perspective. From the perspective of reverse thinking at the bottom of the signal, if you want to reverse decode and analyze a specific differential signal, the traditional method is to directly use an integrated differential signal communication transceiver driver chip that is consistent with the technical characteristics and properties of the differential signal, and analyze the data received and sent by the back-end CPU / MCU module, or use a professional oscilloscope to manually analyze the differential signal. Although the former can meet the needs of differential signal data encoding and decoding analysis, it is only suitable for analyzing the differential signal related to the chip. The differential signal with specific attributes of chip matching is limited to a single differential signal communication scenario, and has not really touched the bottom-level reverse analysis of the differential signal. There are still blind spots in the analysis of the actual transmission characteristics of the bottom-level differential signal; the latter uses an oscilloscope analysis method. Although it has touched the bottom level of the differential signal, it mostly relies on manual analysis of the naked eye, which has the disadvantages of low analysis efficiency, high difficulty, and high error rate. Although many manufacturers provide oscilloscope data communication decoding option support, it is difficult to cover differential signals with different technical characteristics and technical attributes, especially the reverse analysis of dynamic non-return-to-zero scanning differential signals is basically not supported. Therefore, in order to solve the above-mentioned problems, the utility model proposes a dynamic non-return-to-zero differential signal side channel decoding device based on photoelectric isolation. Utility Model Content

[0004] The main purpose of the utility model is to propose a dynamic non-return-to-zero differential signal side channel decoding device based on photoelectric isolation, which adopts a low-power design and an intervention mode of side channel zero-interference bypass monitoring. Under the premise of not affecting or interfering with the object under test, the dynamic non-return-to-zero scanning differential signal transmission mode is reversely decoded and analyzed, and the decoded data is output in real time and saved in local storage at the same time.

[0005] To achieve the above-mentioned purpose, the utility model provides a dynamic non-return-to-zero differential signal side channel decoding device based on photoelectric isolation, wherein the dynamic non-return-to-zero differential signal side channel decoding and analysis device based on photoelectric isolation comprises: an MCU module circuit, an IO drive buffer circuit, a high-speed photoelectric isolation amplifier circuit, a differential signal bypass acquisition interface, an analog switch circuit, an external FLASH storage circuit and a power supply / UART; the output end of the analog switch circuit is electrically connected to the input end of the differential signal bypass acquisition interface, the output end of the differential signal bypass acquisition interface is connected to the input end of the high-speed photoelectric isolation amplifier circuit, the output end of the high-speed photoelectric isolation amplifier circuit is electrically connected to the input ends of the IO drive buffer circuit and the analog switch circuit respectively, the output end of the IO drive buffer circuit is connected to the input end of the MCU module circuit, and the output end of the MCU module circuit is electrically connected to the input end of the analog switch circuit; the external FLASH storage circuit and the power supply / UART are both electrically connected to the MCU module circuit.

[0006] One of the preferred schemes, the analog switch circuit includes a differential signal S-end analog switch circuit; the differential signal S-end analog switch circuit is used to dynamically scan, select, monitor, analyze and formulate differential SI0-SI7 signal channels according to the driving instructions of the MCU module circuit.

[0007] One of the preferred schemes, the analog switch circuit includes a differential signal COM end analog switch circuit; the input end of the differential signal COM end analog switch circuit is electrically connected to the output end of the differential signal S end analog switch circuit, and the output end of the differential signal COM end analog switch circuit is electrically connected to the input end of the differential signal bypass acquisition interface; the differential signal COM end analog switch circuit is used to dynamically scan, select, monitor and analyze the specified differential COM0-COM7 signal channels according to the driving instructions of the MCU module circuit.

[0008] In one of the preferred solutions, the differential signal bypass acquisition interface is accessed in a side channel bypass manner.

[0009] In one of the preferred solutions, the differential signal bypass acquisition interface supports at least 8 channels of differential COM signals.

[0010] In one of the preferred solutions, the differential signal bypass acquisition interface supports at least 8 channels of differential SI signals.

[0011] In one of the preferred solutions, the high-speed photoelectric isolation amplifier circuit adopts a Darlington structure.

[0012] One of the preferred schemes, the high-speed optoelectronic isolation amplifier circuit is provided with at least four optocoupler isolation circuits; the optocoupler isolation circuit includes an optocoupler U6; pin 1 of the optocoupler U6 is connected to resistor R13, pin 3 of the optocoupler U6 is connected to resistor R14, and the other ends of the resistors R13 and R14 are connected to the differential signal bypass acquisition interface; pins 2 and 4 of the optocoupler U6 are both connected to the analog switch circuit; pins 5 and 7 of the optocoupler U6 are grounded; pin 6 of the optocoupler U6 is respectively connected to resistor R4 and the IO drive buffer circuit, and the other end of the resistor R4 is connected to the power supply terminal; pin 8 of the optocoupler U6 is respectively connected to resistor R3 and the IO drive buffer circuit, and the other end of the resistor R3 is connected to the power supply terminal.

[0013] In one of the preferred solutions, the IO drive buffer circuit is provided with at least four buffer conversion circuits; the buffer conversion circuit includes a MOS tube Q3 and a MOS tube Q4; the gate of the MOS tube Q3 is connected to a high-speed photoelectric isolation amplifier circuit, the drain of the MOS tube Q3 is respectively connected to a resistor R19 and an MCU module circuit, and the other end of the resistor R19 is connected to a power supply terminal; the source of the MOS tube Q3 is grounded; the gate of the MOS tube Q4 is connected to a high-speed photoelectric isolation amplifier circuit, the drain of the MOS tube Q4 is respectively connected to a resistor R20 and an MCU module circuit, and the other end of the resistor R20 is connected to a power supply terminal.

[0014] One of the preferred schemes, the dynamic non-return-to-zero differential signal side channel decoding and analysis device based on photoelectric isolation also includes a power-on reset circuit; the output end of the power-on reset circuit is electrically connected to the input end of the MCU module circuit; the power-on reset circuit includes a resistor R2 and a capacitor C9; one end of the resistor R2 is connected to the power supply end, the other end of the resistor R2 is respectively connected to the capacitor C9 and the MCU module circuit, and the other end of the capacitor C9 is grounded.

[0015] In the above technical solution of the utility model, the dynamic non-return-to-zero differential signal side channel decoding and analysis device based on photoelectric isolation includes: an MCU module circuit, an IO drive buffer circuit, a high-speed photoelectric isolation amplifier circuit, a differential signal bypass acquisition interface, an analog switch circuit, an external FLASH storage circuit and a power supply / UART; the output end of the analog switch circuit is electrically connected to the input end of the differential signal bypass acquisition interface, the output end of the differential signal bypass acquisition interface is connected to the input end of the high-speed photoelectric isolation amplifier circuit, the output end of the high-speed photoelectric isolation amplifier circuit is electrically connected to the input ends of the IO drive buffer circuit and the analog switch circuit respectively, the output end of the IO drive buffer circuit is connected to the input end of the MCU module circuit, and the output end of the MCU module circuit is electrically connected to the input end of the analog switch circuit; the external FLASH storage circuit and the power supply / UART are both electrically connected to the MCU module circuit. The utility model integrates high-speed analog matrix switch and high-speed optical coupler isolation dynamic scanning signal amplification technology, and uses the intervention mode of side channel zero interference bypass monitoring. Under the premise of not affecting or interfering with the normal operation of the measured object, it can go deep into the bottom layer of the differential signal to perform reverse decoding analysis on it, and can support reverse decoding analysis of dynamic non-return-to-zero scanning differential signal transmission mode. At the same time, it also supports saving the analyzed and decoded data in local FLASH for later data export and analysis. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the implementation methods of the utility model or the technical solutions in the prior art, the drawings required for use in the implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some implementation methods of the utility model. For ordinary technicians in this field, other drawings can be obtained based on the structures shown in these drawings without paying creative work.

[0017] Figure 1 It is a schematic diagram of a dynamic non-return-to-zero differential signal side channel decoding device based on photoelectric isolation according to an embodiment of the utility model;

[0018] Figure 2 This is a schematic diagram of a differential signal bypass acquisition interface according to an embodiment of the utility model;

[0019] Figure 3 A schematic diagram of a high-speed photoelectric isolation amplifier circuit according to an embodiment of the utility model;

[0020] Figure 4 This is a schematic diagram of a differential signal S-terminal analog switch circuit according to an embodiment of the utility model;

[0021] Figure 5 This is a schematic diagram of a differential signal COM terminal analog switch circuit according to an embodiment of the utility model;

[0022] Figure 6 Schematic diagram of an IO drive buffer circuit according to an embodiment of the present utility model;

[0023] Figure 7 This is a schematic diagram of the MCU module circuit of an embodiment of the utility model;

[0024] Figure 8 A schematic diagram of a power-on reset circuit according to an embodiment of the present utility model;

[0025] Fig. 9 A schematic diagram of an external FLASH storage circuit according to an embodiment of the present utility model;

[0026] Fig.10 Schematic diagram of a power supply / UART interface circuit according to an embodiment of the present utility model.

[0027] The realization of the purpose, functional features and advantages of the utility model will be further explained in conjunction with the implementation methods and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0028] The following will be combined with the drawings in the embodiments of the utility model to clearly and completely describe the technical solutions in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments of the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.

[0029] In addition, in the present invention, the descriptions of "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" or "second" may explicitly or implicitly include at least one of the features.

[0030] Furthermore, the technical solutions between the various implementation modes of the present invention may be combined with each other, but this must be based on the fact that they can be implemented by ordinary technicians in the field. When the combination of technical solutions is mutually contradictory or cannot be implemented, it should be deemed that such combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0031] See also Figure 1-Figure 10According to one aspect of the utility model, the utility model provides a dynamic non-return-to-zero differential signal side channel decoding device based on photoelectric isolation, wherein the dynamic non-return-to-zero differential signal side channel decoding and analysis device based on photoelectric isolation includes: an MCU module circuit, an IO drive buffer circuit, a high-speed photoelectric isolation amplifier circuit, a differential signal bypass acquisition interface, an analog switch circuit, an external FLASH storage circuit and a power supply / UART; the output end of the analog switch circuit is electrically connected to the input end of the differential signal bypass acquisition interface, the output end of the differential signal bypass acquisition interface is connected to the input end of the high-speed photoelectric isolation amplifier circuit, the output end of the high-speed photoelectric isolation amplifier circuit is electrically connected to the input ends of the IO drive buffer circuit and the analog switch circuit respectively, the output end of the IO drive buffer circuit is connected to the input end of the MCU module circuit, and the output end of the MCU module circuit is electrically connected to the input end of the analog switch circuit; the external FLASH storage circuit and the power supply / UART are both electrically connected to the MCU module circuit.

[0032] Specifically, in this embodiment, the dynamic non-return-to-zero differential signal side channel decoding and analysis device based on photoelectric isolation integrates a high-speed analog matrix switch and a high-speed photoelectric isolation dynamic scanning signal amplification technology, and uses the intervention mode of side channel zero-interference bypass monitoring. Under the premise of not affecting or interfering with the normal operation of the object under test, it can go deep into the bottom layer of the differential signal to carry out reverse decoding analysis on it, and can support reverse decoding analysis of the dynamic non-return-to-zero scanning differential signal transmission mode, and can also support the storage of the analyzed and decoded data in the local FLASH storage chip for later data export and analysis; the dynamic non The return-to-zero differential signal is for a differential signal pair consisting of multiple groups of COM terminals and S terminals. When a certain group of differential signals is at a 0 logic level or an invalid logic level, the voltage difference of the differential signals still has a certain amplitude V1. When a certain group of differential signals is at a 1 logic level or a valid logic level, the voltage difference of the differential signals is V2. V1 and V2 satisfy the following relationship: V1 value is not equal to 0V, |V2|>|V1|. At the same time, there is only one group of differential signal levels at a 1 logic level or a valid logic level. A dynamic scanning method is used to drive a certain group of differential signals to a 1 logic level or a valid logic level.

[0033] Specifically, in this embodiment, the differential signal bypass acquisition interface is accessed by side channel bypass mode; the differential signal bypass acquisition interface supports at least 8-channel differential COM signals; the differential signal bypass acquisition interface supports at least 8-channel differential SI signals; the differential signal bypass acquisition interface is a signal access circuit for the dynamic non-return-to-zero differential signal of the measured object, and is accessed by side channel bypass mode. Because the subsequent circuit adopts a high input impedance design, it does not affect the existing working mechanism of the measured differential signal, and has zero interference with it, and supports 8-channel differential COM signals and 8-channel differential SI signal access, based on the original dynamic non-return-to-zero differential signal, a secondary high-speed dynamic scanning reverse analysis is performed on it, which can support up to 8*8=64 dynamic non-return-to-zero differential signal reverse analysis. The differential signal bypass acquisition interface can be led out in a variety of ways to adapt to the interface of the object under test. SI0-SI7 signals are provided to the high-speed optoelectronic isolation amplifier circuit of the subsequent stage as the differential drive signal on the input side of the optoelectronic isolation. COM0-COM7 signals are connected to the differential signal COM end analog switch circuit of the subsequent stage to ensure that a closed loop is formed with the output side signal of the high-speed optoelectronic isolation amplifier circuit.

[0034] Specifically, in the present embodiment, the high-speed photoelectric isolation amplifier circuit adopts a Darlington structure; it meets the requirements of a high light-to-current conversion ratio, and includes three signals, wherein SI0-SI7 signals are photocurrent input side signals, which are provided by the differential signal bypass acquisition interface of the previous stage, and SP0-SP7 signals are photocurrent output side signals, which are output to the differential signal S-end analog switch circuit of the subsequent stage to ensure that an effective closed-loop circuit is formed on the photocurrent input side of the high-speed photoelectric isolation amplifier circuit, and S0-S7 are primary logic output signals of photoelectric conversion of the high-speed photoelectric isolation amplifier circuit, which are output to the IO drive buffer circuit of the subsequent stage to provide input signals for it.

[0035] Specifically, in this embodiment, the high-speed photoelectric isolation amplifier circuit is provided with at least four optocoupler isolation circuits; the high-speed photoelectric isolation amplifier circuit includes a first optocoupler isolation circuit, a second optocoupler isolation circuit, a third optocoupler isolation circuit and a fourth optocoupler isolation circuit;

[0036] The first optocoupler isolation circuit includes an optocoupler U6; pin 1 of the optocoupler U6 is connected to a resistor R13, pin 3 of the optocoupler U6 is connected to a resistor R14, and the other ends of the resistors R13 and R14 are connected to a differential signal bypass acquisition interface to access SI0 and SI1 signals; pins 2 and 4 of the optocoupler U6 are connected to an analog switch circuit to output SP0 and SP1 signals; pins 5 and 7 of the optocoupler U6 are grounded; pin 6 of the optocoupler U6 is respectively connected to a resistor R4 and an IO drive buffer circuit, and the other end of the resistor R4 is connected to a power supply terminal; pin 8 of the optocoupler U6 is respectively connected to a resistor R3 and an IO drive buffer circuit, and the other end of the resistor R3 is connected to a power supply terminal;

[0037] The second optocoupler isolation circuit includes an optocoupler U7; pin 1 of the optocoupler U7 is connected to a resistor R15, pin 3 of the optocoupler U6 is connected to a resistor R16, and the other ends of the resistors R15 and R16 are connected to a differential signal bypass acquisition interface to access SI2 and SI3 signals; pins 2 and 4 of the optocoupler U7 are connected to an analog switch circuit to output SP2 and SP3 signals; pins 5 and 7 of the optocoupler U7 are grounded; pin 6 of the optocoupler U7 is respectively connected to a resistor R6 and an IO drive buffer circuit, and the other end of the resistor R8 is connected to a power supply terminal; pin 8 of the optocoupler U7 is respectively connected to a resistor R5 and an IO drive buffer circuit, and the other end of the resistor R5 is connected to a power supply terminal;

[0038] The third optocoupler isolation circuit includes an optocoupler U8; pin 1 of the optocoupler U8 is connected to a resistor R17, pin 3 of the optocoupler U8 is connected to a resistor R18, and the other ends of the resistors R17 and R18 are connected to a differential signal bypass acquisition interface to access SI4 and SI5 signals; pins 2 and 4 of the optocoupler U8 are connected to an analog switch circuit to output SP4 and SP5 signals; pins 5 and 7 of the optocoupler U8 are grounded; pin 6 of the optocoupler U8 is respectively connected to a resistor R8 and an IO drive buffer circuit, and the other end of the resistor R8 is connected to a power supply terminal; pin 8 of the optocoupler U8 is respectively connected to a resistor R7 and an IO drive buffer circuit, and the other end of the resistor R7 is connected to a power supply terminal;

[0039] The fourth optocoupler isolation circuit includes an optocoupler U9; pin 1 of the optocoupler U9 is connected to resistor R25, pin 3 of the optocoupler U9 is connected to resistor R26, the other ends of the resistors R25 and R26 are connected to the differential signal bypass acquisition interface, and SI6 and SI7 signals are connected; pins 2 and 4 of the optocoupler U9 are connected to the analog switch circuit to output SP6 and SP7 signals; pins 5 and 7 of the optocoupler U9 are grounded; pin 6 of the optocoupler U9 is respectively connected to resistor R28 and the IO drive buffer circuit, and the other end of the resistor R28 is connected to the power supply terminal; pin 8 of the optocoupler U9 is respectively connected to resistor R27 and the IO drive buffer circuit, and the other end of the resistor R27 is connected to the power supply terminal.

[0040] Specifically, in the present embodiment, the analog switch circuit includes a differential signal S-end analog switch circuit; the differential signal S-end analog switch circuit is used to dynamically scan, select, monitor, analyze and formulate a differential SI0-SI7 signal channel according to a driving instruction of the MCU module circuit; the differential signal S-end analog switch circuit is designed with a high-speed analog matrix switch circuit, and the internal channel scan is driven by the MCU module circuit. The differential SI0-SI7 signal channel is dynamically scanned, selected, monitored, analyzed and formulated according to the driving instruction of the MCU module circuit, including two input signals SP0-SP7 and S_SEL_A, S_SEL_B, and S_SEL_C, wherein the SP0-SP7 signal is input by a high-speed optoelectronic isolation amplifier circuit of the previous stage and is used to connect the differential SI0-SI7 signal channel of the previous stage, and S_SEL_A, S_SEL_B, and S_SEL_C are input by a MCU module circuit of the subsequent stage, and the dynamic scanning control selects the currently specified differential SI0-SI7 signal channel, and the output signal S is provided to the differential signal COM-end analog switch circuit of the previous stage to ensure that the driving signal forms a closed loop.

[0041] Specifically, in the present embodiment, the analog switch circuit comprises a differential signal COM end analog switch circuit; the input end of the differential signal COM end analog switch circuit is electrically connected to the output end of the differential signal S end analog switch circuit, and the output end of the differential signal COM end analog switch circuit is electrically connected to the input end of the differential signal bypass acquisition interface; the differential signal COM end analog switch circuit is used to dynamically scan, select, monitor, analyze and specify differential COM0-COM7 signal channels according to the driving instructions of the MCU module circuit; the differential signal COM end analog switch circuit adopts a high-speed analog matrix switch circuit design, and the internal channel scanning is driven by the MCU module circuit, and the differential CO is selected, monitored and analyzed according to the dynamic scanning. M0-COM7 signal channel, the differential signal COM end analog switch circuit includes two input signals S and COM_SEL_A, COM_SEL_B, COM_SEL_C, wherein the signal S is provided by the previous stage differential signal S end analog switch circuit for connecting the differential SI0-SI7 signal channel of the previous stage, COM_SEL_A, COM_SEL_B, COM_SEL_C are provided by the subsequent stage MCU module circuit for input, and the dynamic scanning control selects the currently specified differential COM0-COM7 signal channel, and the signal COM0-COM7 is connected to the COM0-COM7 signal of the differential signal bypass acquisition interface of the previous stage to ensure that the differential drive signal forms a closed-loop monitoring loop.

[0042] Specifically, in the present embodiment, the IO drive buffer circuit is provided with at least four buffer conversion circuits; the IO drive buffer circuit includes a first buffer conversion circuit, a second buffer conversion circuit, a third buffer conversion circuit and a fourth buffer conversion circuit; the S0-S7 signals are output by the high-speed photoelectric isolation amplifier circuit of the previous stage. Since the output capability of the photoelectric conversion output signals S0-S7 of the high-speed photoelectric isolation amplifier circuit of the previous stage is relatively weak, they cannot be directly and accurately identified by the MCU module circuit. Therefore, the IO drive buffer circuit is introduced for buffer conversion, and the S0-S7 photoelectric conversion signals with relatively weak driving capability are buffered and converted into SM0-SM7 signals to be provided to the MCU module circuit for identification. In order to reduce the power consumption of the circuit, the circuit adopts the NPN MOS tube design of the FET architecture, and its high input impedance, high frequency response, low driving voltage and high load driving capability can effectively provide photoelectric output logic signal buffer conversion.

[0043] Specifically, in the present embodiment, the first buffer conversion circuit includes a MOS tube Q3 and a MOS tube Q4; the gate of the MOS tube Q3 is connected to the high-speed photoelectric isolation amplifier circuit, the drain of the MOS tube Q3 is respectively connected to the resistor R19 and the MCU module circuit, and the other end of the resistor R19 is connected to the power supply end; the source of the MOS tube Q3 is grounded; the gate of the MOS tube Q4 is connected to the high-speed photoelectric isolation amplifier circuit, the drain of the MOS tube Q4 is respectively connected to the resistor R20 and the MCU module circuit, and the other end of the resistor R20 is connected to the power supply end.

[0044] Specifically, in the present embodiment, the second buffer conversion circuit includes a MOS transistor Q5 and a MOS transistor Q6; the gate of the MOS transistor Q5 is connected to the high-speed photoelectric isolation amplifier circuit, the drain of the MOS transistor Q5 is respectively connected to the resistor R21 and the MCU module circuit, and the other end of the resistor R21 is connected to the power supply terminal; the source of the MOS transistor Q5 is grounded; the gate of the MOS transistor Q6 is connected to the high-speed photoelectric isolation amplifier circuit, the drain of the MOS transistor Q6 is respectively connected to the resistor R22 and the MCU module circuit, and the other end of the resistor R22 is connected to the power supply terminal.

[0045] Specifically, in the present embodiment, the third buffer conversion circuit includes a MOS tube Q7 and a MOS tube Q8; the gate of the MOS tube Q7 is connected to the high-speed photoelectric isolation amplifier circuit, the drain of the MOS tube Q7 is respectively connected to the resistor R23 and the MCU module circuit, and the other end of the resistor R23 is connected to the power supply terminal; the source of the MOS tube Q7 is grounded; the gate of the MOS tube Q8 is connected to the high-speed photoelectric isolation amplifier circuit, the drain of the MOS tube Q8 is respectively connected to the resistor R24 ​​and the MCU module circuit, and the other end of the resistor R24 ​​is connected to the power supply terminal.

[0046] Specifically, in the present embodiment, the fourth buffer conversion circuit includes a MOS tube Q9 and a MOS tube Q10; the gate of the MOS tube Q9 is connected to the high-speed photoelectric isolation amplifier circuit, the drain of the MOS tube Q9 is respectively connected to the resistor R29 and the MCU module circuit, and the other end of the resistor R29 is connected to the power supply terminal; the source of the MOS tube Q9 is grounded; the gate of the MOS tube Q10 is connected to the high-speed photoelectric isolation amplifier circuit, the drain of the MOS tube Q10 is respectively connected to the resistor R30 and the MCU module circuit, and the other end of the resistor R30 is connected to the power supply terminal.

[0047] Specifically, in this embodiment, the dynamic non-return-to-zero differential signal side channel decoding and analysis device based on photoelectric isolation also includes a power-on reset circuit; the output end of the power-on reset circuit is electrically connected to the input end of the MCU module circuit; the power-on reset circuit includes a resistor R2 and a capacitor C9; one end of the resistor R2 is connected to the power supply end, the other end of the resistor R2 is respectively connected to the capacitor C9 and the MCU module circuit, and the other end of the capacitor C9 is grounded; the power-on reset circuit is used to ensure that the MCU module circuit can operate normally after power-on reset, and the power-on reset circuit implements the power-on reset of the MCU module circuit based on RC design, and at the same time, it can also be implemented using an integrated power-on reset chip.

[0048] Specifically, in this embodiment, the MCU module circuit is used for dynamic scanning control, and the currently specified differential signal SI0-SI7 and differential signal COM0-COM7 channels are selected to ensure the acquisition of specific differential signals. The differential signal COM0-COM7 channels are configured by COM_SEL_A, COM_SEL_B, and COM_SEL_C control signals, and the differential SI0-SI7 signal channels are configured by S_SEL_A, S_SEL_B, and S_SEL_C control signals. The scanning period is controlled by the MCU module circuit according to the technical characteristics of the measured differential signal to ensure the real-time performance of the reverse analysis and decoding of the differential signal. At the same time, the SM0-SM7 signals output by the front-stage IO drive buffer circuit are collected, and the measured differential signal is converted into a single-ended signal. This circuit identifies and collects, and decodes and outputs in a targeted manner according to the characteristics of the differential signal under test. The RST_SIG signal is provided by the power-on reset circuit to ensure that the circuit of this module can operate normally. At the same time, the external FLASH storage circuit is driven through the I2C interface to store the reverse analysis and decoding result data of the measured differential signal inside the external FLASH chip to ensure that the data is not lost during power failure, which is convenient for later data export and analysis. In addition, this circuit is also connected to the power supply / UART interface circuit. The PWR signal is the +3V external power supply interface, and the MODE signal is the working mode selection signal of this circuit, which is convenient for manual real-time configuration of the current working mode of the MCU. UART is a serial communication signal, which is convenient for outputting the reverse analysis and decoding result of the measured differential signal to the display terminal through the UART interface.

[0049] Specifically, in this embodiment, the external FLASH storage circuit; the external FLASH storage circuit is connected to the MCU module circuit through the I2C interface, and is driven by the MCU module circuit using the I2C interface, and is used to save the result data of the reverse decoding analysis of the measured differential signal into the external FLASH chip, so that the decoded data can be exported and analyzed again after power failure. Depending on the storage capacity, the decoding and analysis result data can also be saved in the MCU internal FLASH.

[0050] Specifically, in this embodiment, the power supply / UART interface circuit is connected to the MCU module circuit, and the power supply / UART interface circuit is used for device power supply, MCU working mode selection and external UART data communication. The entire device is powered by a +3V DC power supply, and the MODE signal is the MCU module circuit working mode configuration signal, wherein TX0 and RX0 are UART serial port communication signals. It is connected to the MCU module circuit and is mainly used to output the real-time differential signal decoding data or the FLASH decoding history data stored inside and outside to the display terminal through the serial port.

[0051] The above are only preferred embodiments of the present invention, and do not limit the patent scope of the present invention. All equivalent structural changes made by using the contents of the present invention specification and drawings under the utility model concept, or directly / indirectly used in other related technical fields are included in the patent protection scope of the present invention.

Claims

1. A dynamic non-return-to-zero differential signal side channel decoding device based on photoelectric isolation, characterized in that: include: MCU module circuit, IO drive buffer circuit, high-speed photoelectric isolation amplifier circuit, differential signal bypass acquisition interface, analog switch circuit, external FLASH storage circuit and power supply / UART; the output end of the analog switch circuit is electrically connected to the input end of the differential signal bypass acquisition interface, the output end of the differential signal bypass acquisition interface is connected to the input end of the high-speed photoelectric isolation amplifier circuit, the output end of the high-speed photoelectric isolation amplifier circuit is electrically connected to the input ends of the IO drive buffer circuit and the analog switch circuit respectively, the output end of the IO drive buffer circuit is connected to the input end of the MCU module circuit, and the output end of the MCU module circuit is electrically connected to the input end of the analog switch circuit; the external FLASH storage circuit and the power supply / UART are both electrically connected to the MCU module circuit.

2. The dynamic non-return-to-zero differential signal side channel decoding device based on photoelectric isolation according to claim 1, characterized in that: The analog switch circuit includes a differential signal S-end analog switch circuit; the differential signal S-end analog switch circuit is used to dynamically scan, select, monitor, analyze and formulate differential SI0-SI7 signal channels according to the driving instructions of the MCU module circuit.

3. The dynamic non-return-to-zero differential signal side channel decoding device based on photoelectric isolation according to claim 2, characterized in that: The analog switch circuit includes a differential signal COM end analog switch circuit; the input end of the differential signal COM end analog switch circuit is electrically connected to the output end of the differential signal S end analog switch circuit, and the output end of the differential signal COM end analog switch circuit is electrically connected to the input end of the differential signal bypass acquisition interface; the differential signal COM end analog switch circuit is used to dynamically scan, select, monitor and analyze the specified differential COM0-COM7 signal channels according to the driving instructions of the MCU module circuit.

4. A dynamic non-return-to-zero differential signal side channel decoding device based on photoelectric isolation according to any one of claims 1 to 3, characterized in that: The differential signal bypass acquisition interface is accessed in a side channel bypass manner.

5. The dynamic non-return-to-zero differential signal side channel decoding device based on photoelectric isolation according to claim 4, characterized in that: The differential signal bypass acquisition interface supports at least 8 channels of differential COM signals.

6. The dynamic non-return-to-zero differential signal side channel decoding device based on photoelectric isolation according to claim 4, characterized in that: The differential signal bypass acquisition interface supports at least 8 channels of differential SI signals.

7. A dynamic non-return-to-zero differential signal side channel decoding device based on photoelectric isolation according to any one of claims 1 to 3, characterized in that: The high-speed photoelectric isolation amplifier circuit adopts a Darlington structure.

8. The dynamic non-return-to-zero differential signal side channel decoding device based on photoelectric isolation according to claim 7, characterized in that: The high-speed optoelectronic isolation amplifier circuit is provided with at least four optocoupler isolation circuits; the optocoupler isolation circuit includes an optocoupler U6; pin 1 of the optocoupler U6 is connected to resistor R13, pin 3 of the optocoupler U6 is connected to resistor R14, and the other ends of the resistors R13 and R14 are connected to the differential signal bypass acquisition interface; pins 2 and 4 of the optocoupler U6 are both connected to the analog switch circuit; pins 5 and 7 of the optocoupler U6 are grounded; pin 6 of the optocoupler U6 is respectively connected to resistor R4 and the IO drive buffer circuit, and the other end of the resistor R4 is connected to the power supply end; pin 8 of the optocoupler U6 is respectively connected to resistor R3 and the IO drive buffer circuit, and the other end of the resistor R3 is connected to the power supply end.

9. A dynamic non-return-to-zero differential signal side channel decoding device based on photoelectric isolation according to any one of claims 1 to 3, characterized in that: The IO drive buffer circuit is provided with at least four buffer conversion circuits; the buffer conversion circuit includes a MOS tube Q3 and a MOS tube Q4; the gate of the MOS tube Q3 is connected to the high-speed photoelectric isolation amplifier circuit, the drain of the MOS tube Q3 is respectively connected to the resistor R19 and the MCU module circuit, and the other end of the resistor R19 is connected to the power supply terminal; the source of the MOS tube Q3 is grounded; the gate of the MOS tube Q4 is connected to the high-speed photoelectric isolation amplifier circuit, the drain of the MOS tube Q4 is respectively connected to the resistor R20 and the MCU module circuit, and the other end of the resistor R20 is connected to the power supply terminal.

10. A dynamic non-return-to-zero differential signal side channel decoding device based on photoelectric isolation according to any one of claims 1 to 3, characterized in that: The dynamic non-return-to-zero differential signal side channel decoding and analysis device based on photoelectric isolation also includes a power-on reset circuit; the output end of the power-on reset circuit is electrically connected to the input end of the MCU module circuit; the power-on reset circuit includes a resistor R2 and a capacitor C9; one end of the resistor R2 is connected to the power supply end, the other end of the resistor R2 is respectively connected to the capacitor C9 and the MCU module circuit, and the other end of the capacitor C9 is grounded.

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