Semiconductor element

Abstract

A semiconductor element includes a first transistor and a second transistor. A first transistor includes a first semiconductor channel layer, a first gate structure, and a first source / drain epitaxial structure. The first semiconductor channel layer has a first crystal orientation. The first gate structure surrounds the first semiconductor channel layer. The first source / drain epitaxial structures are located at two opposite ends of the first semiconductor channel layer. The second transistor is located above the first transistor and has a conductivity type different from that of the first transistor, and the second transistor comprises a second semiconductor channel layer, a second gate structure and a second source / drain epitaxial structure. The second semiconductor channel layer has a second crystal orientation different from the first crystal orientation. The second gate structure surrounds the second semiconductor channel layer. The second source / drain epitaxial structure is located at two opposite ends of the second semiconductor channel layer.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in integrated circuit materials and design have created generations of integrated circuits, each with smaller and more complex circuits than the previous one. Over the course of the evolution of integrated circuits, functional density (i.e., the number of interconnected components per chip) has continued to increase, while component size (i.e., the smallest component that can be manufactured by a process) has continued to decrease. Processes that shrink in size generally provide increased production efficiency and reduced associated waste. However, as feature sizes shrink, processes continue to become more difficult. Therefore, forming reliable semiconductor components is a challenge as dimensions get smaller. Utility Model Content

[0003] According to some embodiments of the present disclosure, a semiconductor element includes a first transistor and a second transistor. A first transistor includes a first semiconductor channel layer, a first gate structure, and a first source / drain epitaxial structure. The first semiconductor channel layer has a first crystal orientation. The first gate structure surrounds the first semiconductor channel layer. The first source / drain epitaxial structure is located at opposite ends of the first semiconductor channel layer. The second transistor is located above the first transistor and has a different conductivity type from the first transistor, wherein the second transistor includes a second semiconductor channel layer, a second gate structure, and a second source / drain epitaxial structure. The second semiconductor channel layer has a second crystal orientation different from the first crystal orientation. The second gate structure surrounds the second semiconductor channel layer. The second source / drain epitaxial structure is located at opposite ends of the second semiconductor channel layer.

[0004] According to some embodiments of the present disclosure, a semiconductor element includes a first transistor, a second transistor, a dielectric layer, and an isolation structure. The first transistor includes a first semiconductor channel layer, a first gate structure, and a first source / drain epitaxial structure. The first gate structure surrounds the first semiconductor channel layer. The first source / drain epitaxial structure is located at opposite ends of the first semiconductor channel layer. The second transistor is located above the first transistor, and includes a second semiconductor channel layer, a second gate structure, and a second source / drain epitaxial structure. The second semiconductor channel layer has a first crystal orientation. The second gate structure surrounds the second semiconductor channel layer. The second source / drain epitaxial structure is located at opposite ends of the second semiconductor channel layer. The dielectric layer is vertically located between the first gate structure and the second gate structure, wherein the dielectric layer has a second crystal orientation that is the same as the first crystal orientation. The isolation structure is located between one of the first source / drain epitaxial structures and one of the second source / drain epitaxial structures.

[0005] According to some embodiments of the present disclosure, a semiconductor element includes a first transistor and a second transistor. A first transistor includes a first semiconductor channel layer, a first gate structure, and a first source / drain epitaxial structure. The first semiconductor channel layer has a first crystal orientation. The first gate structure surrounds the first semiconductor channel layer. The first source / drain epitaxial structure is located at opposite ends of the first semiconductor channel layer. The second transistor is located above the first transistor and has a different conductivity type from the first transistor, wherein the second transistor includes a second semiconductor channel layer, a second gate structure, and a second source / drain epitaxial structure. The second semiconductor channel layer has a second crystal orientation different from the first crystal orientation. The second gate structure surrounds the second semiconductor channel layer. The second source / drain epitaxial structure is located at opposite ends of the second semiconductor channel layer. A dielectric layer is vertically located between the first transistor and the second transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. Note that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 A perspective view of a semiconductor device according to some embodiments of the present disclosure;

[0008] FIG. 2A to FIG. 17B Schematic diagrams of methods for forming semiconductor devices at different stages according to some embodiments of the present disclosure;

[0009] Fig.18A and Fig.18B Schematic diagram of a semiconductor device according to some embodiments of the present disclosure;

[0010] FIG. 19A to FIG. 35B Schematic diagrams of methods for forming semiconductor devices at different stages according to some embodiments of the present disclosure;

[0011] Figures 36 to 38B Schematic diagrams of methods for forming semiconductor devices at different stages according to some embodiments of the present disclosure.

[0012]

Explanation of symbols

[0013] 10: Complementary Field Effect Transistor / CFET

[0014] 100:Substrate

[0015] 100P:Semiconductor Strip

[0016] 102: Semiconductor channel layer / semiconductor layer

[0017] 104: Semiconductor layer

[0018] 105: Crystal direction switching layer

[0019] 106: Isolation Structure

[0020] 115: Spacer

[0021] 116:Internal spacer

[0022] 117: Isolation layer

[0023] 120: Fictitious Materials

[0024] 125: Lining

[0025] 130: dummy gate structure

[0026] 132: Dummy gate dielectric

[0027] 134: dummy gate electrode

[0028] 140: Source / drain epitaxial structure

[0029] 150: Isolation Structure

[0030] 152: Interlayer dielectric layer / ILD layer

[0031] 155: Contact Etch Stop Layer / CESL

[0032] 170:Metal gate structure

[0033] 172: Interface layer

[0034] 174: Gate dielectric layer

[0035] 176: Gate electrode

[0036] 200:Substrate

[0037] 202: Semiconductor channel layer / semiconductor layer

[0038] 204: Semiconductor layer

[0039] 215: Spacer

[0040] 216:Internal spacer

[0041] 230: dummy gate structure

[0042] 232:Dummy gate dielectric

[0043] 234: dummy gate electrode

[0044] 240: Source / drain epitaxial structure

[0045] 250: Isolation Structure

[0046] 252: Interlayer dielectric layer / ILD layer

[0047] 255: Contact Etch Stop Layer / CESL

[0048] 270:Metal gate structure

[0049] 272: Interface layer

[0050] 274: Gate dielectric layer

[0051] 276: Gate electrode

[0052] 302: Bonding layer

[0053] 304: Bonding layer

[0054] 300:Joint structure

[0055] 330,332,334,336: Hard mask

[0056] 400:Substrate

[0057] 405: Crystal direction switching layer

[0058] FN, FN1, FN2: Fin structure

[0059] G1: Clearance

[0060] GT1, GT2: Gate trench

[0061] HM1,HM2:Hard mask

[0062] MA1, MA2: Patterned mask

[0063] O1, O2: Open

[0064] R1: Depression

[0065] ST,ST1,ST2: stacking

[0066] TR1,TR2: Transistor

[0067] AA,BB:Line DETAILED DESCRIPTION

[0068] The following disclosure provides many different embodiments or examples for implementing the different features of the subject matter provided. Specific examples of components and configurations are described below to simplify the disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, the formation of a first feature above or on a second feature may include an embodiment in which the first and second features are formed in direct contact, and may also include an embodiment in which additional features may be formed between the first and second features so that the first and second features may not be in direct contact. In addition, in various examples, the disclosure may repeat reference numbers and / or letters. This repetition is for the purpose of simplicity and clarity, and does not itself define the relationship between the various embodiments and / or configurations discussed.

[0069] Additionally, for ease of description, spatially relative terms such as "beneath," "below," "lower," "above," and "upper," and the like, may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the figures. These spatially relative terms are intended to encompass different orientations of the elements in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein likewise interpreted accordingly.

[0070] A gate-all-around (GAA) transistor structure can be patterned by any suitable method. For example, the structure can be patterned using one or more photolithography processes, including double patterning or multiple patterning processes. Generally speaking, the double patterning or multiple patterning process combines photolithography and self-alignment processes, which allows the pattern to have a smaller pitch than can be obtained using a single direct photolithography process, for example. For example, in one embodiment, a sacrificial layer is formed above a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can be used to pattern the GAA structure.

[0071] Figure 11 is a perspective view of a semiconductor device of some embodiments of the present disclosure. In the present disclosure, a complementary field effect transistor (CFET) 10 is provided, and a manufacturing method thereof will be discussed in the following. In the CFET 10, a first transistor TR1 is disposed above a substrate (not shown), and a second transistor TR2 is vertically disposed above the first transistor TR1. In some embodiments, the first transistor TR1 and the second transistor TR2 may be field effect transistors (FETs), and both may include a gate all around (GAA) configuration, so the first transistor TR1 and the second transistor TR2 may also be referred to as GAA FETs. The first transistor TR1 includes vertically stacked first semiconductor channel layers 102, a first metal gate structure 170 surrounding each first semiconductor channel layer 102, and a first source / drain epitaxial structure 140 located at both ends of each first semiconductor channel layer 102. Similarly, the second transistor TR2 includes vertically stacked second semiconductor channel layers 202, a second metal gate structure 270 surrounding each second semiconductor channel layer 202, and a second source / drain epitaxial structure 240 located at both ends of each second semiconductor channel layer 202. The first metal gate structure 170 may include an interfacial layer 172 , a gate dielectric layer 174 , and a gate electrode 176 . Similarly, the second metal gate structure 270 may include an interfacial layer 272 , a gate dielectric layer 274 , and a gate electrode 276 .

[0072] In some embodiments, the first transistor TR1 has a first conductivity type and the second transistor TR2 has a second conductivity type different from the first conductivity type. For example, the first transistor TR1 may be an n-type transistor (e.g., N-FET) and the second transistor TR2 may be a p-type transistor (e.g., P-FET). However, in other embodiments, the first transistor TR1 may be a p-type transistor (e.g., P-FET) and the second transistor TR2 may be an n-type transistor (e.g., N-FET). For an n-type transistor, the source / drain epitaxial structure (e.g., the first source / drain epitaxial structure 140 and / or the second source / drain epitaxial structure 240) may include an n-type dopant, such as phosphorus (P), arsenic (As) or antimony (Sb), etc. For a p-type transistor, the source / drain epitaxial structure (e.g., the first source / drain epitaxial structure 140 and / or the second source / drain epitaxial structure 240) may include a p-type dopant, such as boron (B), gallium (Ga), indium (In), aluminum (Al), etc.

[0073] In some embodiments of the present disclosure, the first semiconductor channel layer 102 and the second semiconductor channel layer 202 may have different crystalline orientations. Experimental results show that the electron mobility of the silicon channel with a (100) crystalline orientation is 350 cm 2 / VS, which is higher than the electron mobility of (110) crystalline silicon channel (230cm 2 / VS) and the electron mobility of the (111) oriented silicon channel (e.g. 300 cm 2 / VS). On the other hand, the (110) crystalline silicon channel has a 180 cm 2 The hole mobility of / VS is higher than that of the (100) oriented silicon channel (e.g. 75 cm 2 / VS) and the hole mobility of the (111) oriented silicon channel (e.g. 120 cm 2 Therefore, the silicon channel with (100) crystal orientation is suitable for n-type devices, while the silicon channel with (110) crystal orientation is suitable for p-type devices.

[0074] Therefore, in an embodiment where the first transistor TR1 is an n-type transistor (e.g., N-FET) and the second transistor TR2 is a p-type transistor (e.g., P-FET), the first semiconductor channel layer 102 and the second semiconductor channel layer 202 may include a (100) crystal orientation and a (110) crystal orientation, respectively. On the other hand, in an embodiment where the first transistor TR1 is a p-type transistor (e.g., P-FET) and the second transistor TR2 is an n-type transistor (e.g., N-FET), the first semiconductor channel layer 102 and the second semiconductor channel layer 202 may include a (110) crystal orientation and a (100) crystal orientation, respectively. By selecting a suitable crystal orientation for the channel layer, the efficiency of the element can be improved.

[0075] FIG. 2A to FIG. 17B Schematic diagram of a method for forming a semiconductor device at different stages of some embodiments of the present disclosure. It should be noted that Figure 2A , Figure 3A , Figure 4A , Figure 5A , Fig. 6A , Fig. 7A , Fig. 8A , Fig. 9A , Fig. 10A , Fig.11A , Fig. 12A , Fig.13A , Fig.14A , Fig.15A , Fig.16A and Fig.17A The cross section and along Figure 1 The cross-section of line AA has the same cross-section, and Figure 2B , Figure 3B , Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B , Fig. 9B , Fig. 10B , Fig. 11B, Fig. 12B , Fig. 13B , Fig. 14B , Fig. 15B , Fig. 16B , Fig. 17B The cross-section diagram along Figure 1 The cross-sectional view of line BB has the same cross-sectional view. FIG. 2A to FIG. 17B A series of operations are described, but it should be understood that these operations are not restrictive, and the order of operations can be changed in other embodiments, and the disclosed method is also applicable to other structures. In other embodiments, some operations illustrated and / or described can be omitted in whole or in part. It is worth noting that FIG. 2A to FIG. 17B Some components can be similar to Figure 1 For the sake of brevity, the relevant details will not be repeated.

[0076] refer to Figure 2A and Figure 2B . A substrate 100 is shown. Generally speaking, the substrate 100 may include a bulk semiconductor substrate or a silicon-on-insulator (SOI) substrate. The SOI substrate includes an insulator layer below a thin semiconductor layer, wherein the thin semiconductor layer serves as an active layer of the SOI substrate. The active layer and the bulk semiconductor include a crystalline semiconductor material, silicon, but may also include one or more other semiconductor materials, such as germanium, a silicon-germanium alloy, a compound semiconductor (e.g., GaAs, AlAs, InAs, GaN, AlN, etc.), or alloys thereof (e.g., Ga x Al 1-x As、Ga x Al 1-x N、In x Ga 1-x As, etc.), oxide semiconductors (e.g., ZnO, SnO2, TiO2, Ga2O3, etc.) or combinations thereof. The semiconductor material may be doped or undoped. Other substrates that may be used include multilayer substrates, gradient substrates, or mixed crystal orientation substrates.

[0077] A stack ST is formed over the substrate 100. The stack ST includes a first stack ST1 of alternating semiconductor layers 102 and 104, a crystal orientation switching layer 105 disposed over the first stack ST1, and a second stack ST2 having alternating semiconductor layers 202 and 204 over the crystal orientation switching layer 105. In some embodiments, the semiconductor layers 102 and 202 may be made of pure silicon layers that do not contain germanium. In some embodiments, the semiconductor layers 102 and 202 may also be substantially pure silicon layers, for example, having a germanium percentage of less than about 1%. The semiconductor layers 104 and 204 may be made of silicon germanium. For example, the germanium percentage (atomic percentage concentration) of the semiconductor layers 104 and 204 may be in the range of about 20% and about 40%. In some embodiments, the semiconductor layers 102, 104, 202, and 204 may be deposited using a suitable deposition process, such as selective epitaxial growth (SEG), chemical vapor deposition (CVD), molecular beam epitaxy (MBE), or other suitable processes. In some embodiments, the semiconductor layers 104 and 204 may be removed during the gate replacement process, so the semiconductor layers 104 and 204 may also be referred to as sacrificial layers. In some embodiments, the crystal orientation switching layer 105 may be deposited using a suitable deposition process such as molecular beam epitaxy (MBE) or atomic layer chemical vapor deposition (ALCVD).

[0078] In some embodiments, the substrate 100 may include a first crystal orientation. For example, the first crystal orientation may be a (100) crystal orientation or a (110) crystal orientation. The semiconductor layers 102 and 104 are alternately deposited on the substrate 100. Due to the characteristics of epitaxial growth, the semiconductor layers 102 and 104 tend to have the same crystal orientation as the substrate 100. Therefore, the semiconductor layers 102 and 104 may also include a first crystal orientation.

[0079] The crystal orientation switching layer 105 is then deposited on the first stack ST1. For example, the crystal orientation switching layer 105 is deposited on the topmost semiconductor layer 102 of the first stack ST1. The crystal orientation switching layer 105 may include a second crystal orientation that is different from the first crystal orientation of the substrate 100 and the semiconductor layers 102 and 104. For example, if the first crystal orientation is a (100) crystal orientation, the second crystal orientation is a (110) crystal orientation. Similarly, if the first crystal orientation is a (110) crystal orientation, the second crystal orientation is a (100) crystal orientation.

[0080] The crystal orientation switching layer 105 may be made of a dielectric material, such as a metal oxide. In some embodiments, the metal oxide may include yttrium oxide (Y2O3), cerium oxide (CeO2), a composite oxide system (such as (La x Y 1-x)2O3(LaYO), or containing two or more metal elements), or the like. In some embodiments, because oxygen and silicon have similar lattice constants, silicon atoms can be bonded with oxygen atoms in the dielectric layer with a small lattice mismatch, so that the crystal orientation switching layer 105 can be epitaxially grown on the semiconductor layer (e.g., the topmost semiconductor layer 102) without a serious lattice mismatch problem.

[0081] In addition, the experimental results also show that during the deposition of the crystal orientation switching layer 105 on the semiconductor layer (e.g., the topmost semiconductor layer 102), the crystal orientation of the crystal orientation switching layer 105 is controllable. In detail, the crystal orientation of the crystal orientation switching layer 105 depends on the temperature during the deposition process. In other words, by controlling the deposition temperature of the crystal orientation switching layer 105, the crystal orientation switching layer 105 can obtain a desired crystal orientation.

[0082] For example, in an embodiment where the topmost semiconductor layer 102 is made of silicon and has a (100) crystal orientation, a deposition temperature of about 400° C. to 500° C. (e.g., 450° C. in this example) may produce a crystal orientation switching layer 105 having a (110) crystal orientation. If the deposition temperature is outside this range, the crystal orientation switching layer 105 may have an undesirable crystal orientation. For example, if the deposition temperature is about 60° C., the crystal orientation switching layer 105 may have a random crystal orientation (e.g., a polycrystalline structure). If the deposition temperature is about 270° C., the crystal orientation switching layer 105 has a (111) crystal orientation.

[0083] In some embodiments where the substrate 100 and the semiconductor layers 102 and 104 include a (100) orientation, the deposition temperature of the semiconductor layers 102 and 104 may be about 600° C. to about 700° C. That is, the deposition temperature of the semiconductor layers 102 and 104 may be higher than the deposition temperature of the orientation switching layer 105 .

[0084] Based on the above discussion, it can be seen that the crystal orientation of the crystal orientation switching layer 105 can be switched from the first crystal orientation of the substrate 100 and the semiconductor layers 102 and 104 to the second crystal orientation by selecting the material and deposition temperature of the crystal orientation switching layer 105. The switched crystal orientation is beneficial to make the subsequently grown semiconductor layers 202 and 204 have a different crystal orientation from the substrate 100 and the semiconductor layers 102 and 104.

[0085] The semiconductor layers 202 and 204 are alternately deposited on the crystal orientation switching layer 105. Due to the nature of epitaxial growth, the semiconductor layers 202 and 204 tend to have the same crystal orientation as the crystal orientation switching layer 105. Therefore, the semiconductor layers 202 and 204 may also include a second crystal orientation that is the same as the crystal orientation switching layer 105. That is, although the semiconductor layers 102 and 202 may be made of the same material (e.g., silicon), the semiconductor layers 102 and 202 may include different crystal orientations. Similarly, although the semiconductor layers 104 and 204 may be made of the same material (e.g., silicon germanium), the semiconductor layers 104 and 204 may include different crystal orientations.

[0086] refer to Figure 3A and Figure 3B The stack ST and the substrate 100 are subjected to a patterning process to form a fin structure FN. In some embodiments, the patterning process may include forming a patterned photoresist layer over the stack ST, and then performing an etching process to remove the stack ST and the unwanted portions of the substrate 100 exposed by the patterned photoresist layer. The fin structure FN may include the remaining portion of the stack ST and the semiconductor strip 100P protruding over the substrate 100. In some embodiments, the etching process may include wet etching, dry etching, etc.

[0087] After the fin structure FN is formed, an isolation structure 106 is formed above the substrate 100 and laterally around the fin structure FN. In some embodiments, the isolation structure 106 may be in contact with the sidewall of the semiconductor strip 100P of the substrate 100. The isolation structure 106 may be a shallow trench isolation (STI) structure, a suitable isolation structure, a combination thereof, etc. In some embodiments, the isolation structure 106 may be made of oxide (e.g., silicon oxide), nitride (e.g., silicon nitride), or a combination thereof.

[0088] refer to Figure 4A and Figure 4B The dummy gate structures 130 are formed over the substrate 100 and across the fin structures FN. In some embodiments, each dummy gate structure 130 includes a dummy gate dielectric 132 and a dummy gate electrode 134 over the dummy gate dielectric 132. The dummy gate dielectric 132 may be, for example, silicon oxide, silicon nitride, combinations thereof, etc., and may be deposited or thermally grown according to a suitable technique. The dummy gate electrode 134 may be a conductive or non-conductive material and may include amorphous silicon, polysilicon, polycrystalline silicon germanium (poly-SiGe), metal nitride, metal silicide, metal oxide, and metal.

[0089] The dummy gate electrode 134 and the dummy gate dielectric 132 can be formed by, for example, depositing a dummy gate dielectric layer and a dummy gate layer on the substrate 100, forming a patterned mask MA1 on the dummy gate layer, and then performing an etching process on the dummy dielectric layer and the dummy gate layer using the patterned mask MA1 as an etching mask. In some embodiments, the dummy gate electrode 134 can be deposited by physical vapor deposition (PVD), chemical vapor deposition (CVD), sputtering deposition, or other techniques for depositing a selected material. In some embodiments, the dummy gate dielectric 132 can be formed by thermal oxidation.

[0090] In some embodiments, each patterned mask MA1 includes a first hard mask 330 and a second hard mask 332 above the first hard mask 330. The first hard mask 330 and the second hard mask 332 may be made of different materials. In some embodiments, the first hard mask 330 may be formed of silicon nitride, and the second hard mask 332 may be formed of silicon oxide.

[0091] Spacers 115 are formed on opposite sidewalls of each dummy gate structure 130 (see Figure 4A ), and on the opposite sidewalls of the fin structure FN (see Figure 4B ). In some embodiments, the spacers 115 located on the opposite sidewalls of the dummy gate structure 130 may be referred to as gate spacers, and the spacers 115 located on the opposite sidewalls of the fin structure FN may be referred to as fin spacers. In some embodiments, the fin spacers fall on the isolation structure 106 and may be retained or removed in a subsequent process according to the embodiment. In some embodiments, the spacers 115 may be formed of silicon oxide, silicon nitride, silicon oxynitride, and combinations thereof. In some embodiments, the spacers 115 may be formed by, for example, blanket depositing a spacer layer on a substrate, and then performing an anisotropic etching process to remove a horizontal portion of the spacer layer, so that a vertical portion of the spacer layer remains on the sidewalls of the dummy gate structure 130 and the sidewalls of the fin structure FN. In some embodiments, the remaining vertical portion of the spacer layer may be referred to as a spacer 115. The spacer layer may be deposited using techniques such as CVD, ALD, and the like.

[0092] refer to Figure 5A and Figure 5B . Using the dummy gate structure 130 and the spacer 115 as an etching mask, an etching process is performed to remove a portion of the fin structure FN (or the stack ST) to form a source / drain opening O1 in the fin structure FN (or the stack ST). In some embodiments, the etching process may be wet etching, dry etching, or a combination thereof. In some embodiments, the bottom end of the source / drain opening O1 may be lower than the bottom semiconductor layer 104.

[0093] refer to Fig. 6A and Figure 6BAfter forming the source / drain openings O1, the semiconductor layer 104 and the semiconductor layer 204 are laterally etched to form a sidewall recess R1. In addition, the crystal orientation switching layer 105 is removed to form a gap G1, which is vertically located between the topmost semiconductor layer 102 and the bottommost semiconductor layer 202. In some embodiments, the gap G1 can spatially connect the source / drain openings O1 located on opposite sides of the dummy gate structure 130. In this embodiment, the crystal orientation switching layer 105 is removed and replaced by another dielectric material (e.g., Fig. 7A The isolation layer 117 in the embodiment is replaced to provide the desired electrical isolation purpose.

[0094] In some embodiments, the sidewalls of the semiconductor layers 104 and 204 may be etched using an isotropic etching process such as wet etching. In some embodiments where the semiconductor layers 104 and 204 include, for example, SiGe and the semiconductor layers 102 and 202 include, for example, Si, an etching process may be performed using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or the like for etching the sidewalls of the semiconductor layers 104 and 204. On the other hand, the crystal orientation switching layer 105 may be etched using a suitable etchant such as hydrofluoric acid (HF). In some embodiments, a first etching process is performed to etch the semiconductor layers 104 and 204, and a second etching process is performed to etch the crystal orientation switching layer 105. The first etching process may be performed before or after the second etching process.

[0095] refer to Fig. 7A and Figure 7B . An inner spacer 116 is formed in the sidewall recess R1 at both ends of the semiconductor layer 104 and the semiconductor layer 204, and an isolation layer 117 is formed in the gap G1. In some embodiments, the inner spacer 116 and the isolation layer 117 may include the same material. In some embodiments, the inner spacer 116 and the isolation layer 117 may be formed by the following method, for example, blanket depositing a dielectric layer on the substrate 100 and filling the sidewall recess R1 and the gap G1, and then performing anisotropic etching to remove a portion of the dielectric layer outside the sidewall recess R1 and the gap G1, leaving the remaining portion of the dielectric layer in the sidewall recess R1 and the gap G1 as the inner spacer 116 and the isolation layer 117. The inner spacer 116 and the isolation layer 117 may be deposited by a conformal deposition process such as CVD, ALD, etc. The dielectric layer may include materials such as SiN, SiOCN, SiCN, SIOC, but any suitable material may be used, such as a low dielectric constant (low-k) material having a k value of less than about 3.5. In some embodiments, voids may be formed in the isolation layer 117 due to the high aspect ratio.

[0096] refer to Fig. 8A and Figure 8B. The dummy material 120 is formed in the source / drain opening O1. In more detail, the dummy material 120 can be formed at the bottom of the source / drain opening O1 so that the top surface of the dummy material 120 is lower than the bottommost semiconductor layer 202. Therefore, after the dummy material 120 is formed, the semiconductor layer 202 can be exposed through the upper portion of the source / drain opening O1. In some embodiments, the dummy material 120 can be formed by the following methods, such as depositing a dielectric material to fill the source / drain opening O1, and then etching back the dielectric material to lower the top surface of the dielectric material to a desired position. In some embodiments, the dummy material 120 can be made of SiOCN or other suitable materials.

[0097] Afterwards, a liner 125 is formed to line the sidewalls of the upper portion of the source / drain opening O1 to cover the sidewall surfaces of the semiconductor layer 202 and the sidewall surfaces of the isolation layer 117. The liner 125 may also cover the sidewalls of the spacer 115. In some embodiments, the liner 125 may be formed by the following methods, such as blanket depositing the liner on the substrate, performing an anisotropic etching process to remove the horizontal portion of the liner, so that the vertical portion of the liner remains on the sidewalls of the semiconductor layer 202, the crystal orientation switching layer 105, and the spacer 115. In some embodiments, the remaining vertical portion of the liner may be referred to as the liner 125. In some embodiments, the liner 125 may be made of SiN, metal oxide, or other suitable materials.

[0098] refer to Fig. 9A and Fig. 9B The dummy material 120 is removed by a suitable etching process to expose the sidewall of the semiconductor layer 102 through the lower portion of the source / drain opening O1. In some embodiments, the liner 125 may have a higher etching resistance than the dummy material 120 to the etching process, so the liner 125 may remain after the dummy material 120 is removed.

[0099] refer to Fig. 10A and Fig. 10B. An epitaxial layer 142 is formed at the bottom of the source / drain opening O1, and then a first source / drain epitaxial structure 140 is formed on the epitaxial layer 142, respectively. In some embodiments, the formation of the epitaxial layer 142 may include multiple deposition cycles, wherein each deposition cycle may include a selective epitaxial growth (SEG) process and an etching process. In some embodiments, the SEG process may selectively grow semiconductor materials on exposed semiconductor surfaces, such as the exposed surfaces of the semiconductor strips 100P and the exposed surfaces of the semiconductor layer 102. However, since the exposed area of ​​the semiconductor strips 100P is larger than the exposed area of ​​each semiconductor layer 102, the semiconductor material has a higher growth rate on the exposed area of ​​the semiconductor strips 100P than on the exposed area of ​​each semiconductor layer 102. That is, more semiconductor material will grow on the exposed area of ​​the semiconductor strips 100P than on the exposed area of ​​each semiconductor layer 102. Therefore, the etching process in each deposition cycle of the epitaxial layer 142 can remove the semiconductor material formed on the exposed area of ​​each semiconductor layer 102, and the semiconductor material can remain above the semiconductor strip 100P after the etching process. Therefore, performing several deposition cycles can allow the epitaxial layer 142 to be deposited in a bottom-up manner. That is, the epitaxial layer 142 can be formed from the bottom of the source / drain opening O1 in a bottom-up manner.

[0100] The first source / drain epitaxial structure 140 may be formed by a suitable deposition process, such as a selective epitaxial growth (SEG) process. In some embodiments, the SEG process may selectively grow semiconductor materials on exposed semiconductor surfaces, such as the exposed surface of the epitaxial layer 142 and the exposed surface of the semiconductor layer 102. In some embodiments, an implantation process may be performed on the first source / drain epitaxial structure 140. For example, when the semiconductor layer 102 has a (100) crystal orientation, the first source / drain epitaxial structure 140 may be doped with an n-type dopant, such as phosphorus (P), arsenic (As), or antimony (Sb), etc. Alternatively, when the semiconductor layer 102 has a (110) crystal orientation, the first source / drain epitaxial structure 140 may be doped with a p-type dopant, such as boron (B), gallium (Ga), indium (In), aluminum (Al), or the like. In some embodiments, each first source / drain epitaxial structure 140 may include different layers (e.g., L1, L2, etc.), wherein the layers may include different doping concentrations. In some embodiments, the epitaxial layer 142 may be formed without performing an implantation process, and thus the epitaxial layer 142 is undoped.

[0101] refer to Fig.11A and Fig. 11B After forming the first source / drain epitaxial structure 140, the liner 125 is removed by a suitable etching process. After removing the liner 125, the sidewall of the semiconductor layer 202 is exposed.

[0102] refer to Fig. 12A and Fig. 12B A contact etch stop layer (CESL) 155 is formed covering the first source / drain epitaxial structure 140. Next, an interlayer dielectric (ILD) layer 152 is formed over the CESL 155. Then, an etch-back process is performed to lower the top surfaces of the CESL 155 and the ILD layer 152 so that the sidewalls of the semiconductor layer 202 are exposed through the source / drain openings O1. In some embodiments, the CESL 155 and the ILD layer 152 may be combined to be referred to as an isolation structure 150. In some embodiments, the topmost semiconductor layer 102, the isolation layer 117, and the bottommost semiconductor layer 202 are in contact with the CESL 155 of the isolation structure 150.

[0103] In some embodiments, CESL 155 may be a dielectric layer including silicon nitride, silicon oxynitride, or other suitable materials. In some embodiments, ILD layer 152 may include silicon oxide, silicon nitride, silicon oxynitride, tetraethoxysilane (TEOS), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), low-k dielectric materials, and / or other suitable dielectric materials. Examples of low-k dielectric materials include, but are not limited to, fluorinated quartz glass (FSG), carbon-doped silicon oxide, amorphous fluorinated carbon, polyparaxylene, bisbenzocyclobutene (BCB), or polyimide. CESL 155 and ILD layer 152 may be formed using, for example, CVD, ALD, or other suitable techniques.

[0104] refer to Fig.13A and Fig. 13B. The second source / drain epitaxial structure 240 is formed on opposite sides of each semiconductor layer 202. In some embodiments, the second source / drain epitaxial structure 240 can be formed by a selective epitaxial growth (SEG) process. The SEG process can selectively grow semiconductor materials on exposed semiconductor surfaces, such as the exposed surface of the semiconductor layer 202. In some embodiments, the second source / drain epitaxial structure 240 can be implanted. For example, when the semiconductor layer 202 has a (100) crystal orientation, the second source / drain epitaxial structure 240 can be doped with an n-type dopant, such as phosphorus (P), arsenic (As), or antimony (Sb). Alternatively, when the semiconductor layer 202 has a (110) crystal orientation, the second source / drain epitaxial structure 240 can be doped with a p-type dopant, such as boron (B), gallium (Ga), indium (In), aluminum (Al), or the like. In some embodiments, each second source / drain epitaxial structure 240 may include different layers (e.g., L1, L2, etc.), wherein these layers may include different doping concentrations. In some embodiments, the first source / drain epitaxial structure 140 and the second source / drain epitaxial structure 240 may include dopants of opposite conductivity types. For example, if the first source / drain epitaxial structure 140 is doped with n-type dopants, the second source / drain epitaxial structure 240 is doped with p-type dopants. Similarly, if the first source / drain epitaxial structure 140 is doped with p-type dopants, the second source / drain epitaxial structure 240 is doped with n-type dopants. Fig. 13B , the second source / drain epitaxial structure 240 may include a different width than the first source / drain epitaxial structure 140. In some embodiments, the topmost semiconductor layer 102, the isolation layer 117, and the bottommost semiconductor layer 202 are in contact with the isolation structure 150. However, in other embodiments, the isolation layer 117 and the bottommost semiconductor layer 202 are in contact with the isolation structure 150, while the topmost semiconductor layer 102 may be in contact with the first source / drain epitaxial structure 140, so that one first source / drain epitaxial structure 140 may be in contact with three semiconductor layers 102 and one second source / drain epitaxial structure 240 may be in contact with two semiconductor layers 202. In some other embodiments, the topmost semiconductor layer 102 and the isolation layer 117 are in contact with the isolation structure 150, and the bottommost semiconductor layer 202 can be in contact with the second source / drain epitaxial structure 240, so that a first source / drain epitaxial structure 140 can contact two semiconductor layers 102, and a second source / drain epitaxial structure 240 can contact three semiconductor layers 202.

[0105] refer to Fig.14A and Fig. 14B. A contact etch stop layer (CESL) 255 is formed covering the second source / drain epitaxial structure 240. Thereafter, an interlayer dielectric (ILD) layer 252 is formed over the CESL 255. Then, a planarization process, such as CMP, is performed to remove excess material of the CESL 255 and the ILD layer 252 until the dummy gate structure 130 is exposed. In some embodiments, the patterned mask MA1 is removed during the planarization process. In some embodiments, the CESL 255 and the ILD layer 252 may be combined and referred to as an isolation structure 250. The materials of the CESL 255 and the ILD layer 252 may be similar to those of the CESL 155 and the ILD layer 152, and for the sake of brevity, the relevant details will not be repeated. In some embodiments, the isolation structures 150 and 250 may together form a composite isolation structure.

[0106] refer to Fig.15A and Fig. 15B The dummy gate structure 130 is removed to form a gate trench GT1 between each pair of spacers 115 . Then, an etching process is performed to remove the semiconductor layers 104 and 204 through the gate trench GT1 , so that the semiconductor layer 102 and the semiconductor layer 202 are suspended above the substrate 100 .

[0107] refer to Fig.16A and Fig. 16B The interface layers 172 and 272 are formed on the exposed surfaces of the semiconductor layers 102 and 202, respectively. Then, the gate dielectric layers 174 and 274 are formed on the interface layers 172 and 272, respectively. In some embodiments, the interface layers 172 and 272 can be formed using the same deposition process, and the gate dielectric layers 174 and 274 can be formed using the same deposition process.

[0108] After forming the interface layers 172 and 272 and the gate dielectric layers 174 and 274, a gate electrode 176 is formed in the gate trench GT1 and above the gate dielectric layer 174. The gate electrode 176 is then etched back so that the remaining gate electrode 176 is located at the lower portion of the gate trench GT1. Thus, a first metal gate structure 170 is formed. In more detail, the first metal gate structure 170 is formed at the bottom of the gate trench GT1 so that the first metal gate structure 170 can surround the corresponding semiconductor layer 102. In some embodiments, each first metal gate structure 170 may include an interface layer 172, a gate dielectric layer 174 above the interface layer 172, and a gate electrode 176 above the gate dielectric layer 174.

[0109] In some embodiments, the interface layers 172 and 272 may be made of oxides, such as aluminum oxide (Al2O3), silicon oxide (SiO2), etc. In some embodiments, the gate dielectric layers 174 and 274 may include high-k dielectrics. Examples of high-k dielectric materials include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-aluminum oxide (HfO2-Al2O3) alloys, other suitable high-k dielectric materials, and / or combinations thereof.

[0110] The gate electrode 176 may include a work function metal layer and a fill metal. The work function metal layer may be an n-type or p-type work function layer. Exemplary p-type work function metals include TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, WN, other suitable p-type work function materials, or combinations thereof. Exemplary n-type work function metals include Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, other suitable n-type work function materials, or combinations thereof. The work function layer may include multiple layers. The fill metal may include tungsten (W), aluminum (Al), copper (Cu), or another suitable conductive material.

[0111] refer to Fig.17A and Fig. 17B . The gate electrode 276 is formed in the gate trench GT1 and above the first metal gate structure 170. Therefore, the second metal gate structure 270 is formed. In more detail, the second metal gate structure 270 is formed in the upper portion of the gate trench GT1 and above the first metal gate structure 170, so that the second metal gate structure 270 can surround the corresponding semiconductor layer 202. In some embodiments, each second metal gate structure 270 may include an interface layer 272, a gate dielectric layer 274 located above the interface layer 272, and a gate electrode 276 located above the gate dielectric layer 274. The material of the gate electrode 276 is similar to the material described for the upper gate electrode 176, and the relevant details will not be repeated for the sake of brevity.

[0112] The second metal gate structure 270 is then etched back so that the top surface of the second metal gate structure 270 is lower than the top surface of the gate spacer 115. Thereafter, a hard mask HM1 is formed over the corresponding second metal gate structure 270. In some embodiments, the hard mask HM1 may include one or more layers of dielectric material, such as a silicon nitride-based material including SiN, SiCN, and SiOCN. The hard mask HM1 may be formed by the following method, for example, depositing a dielectric layer over the etched back second metal gate structure 270, and then performing a planarization process such as CMP on the dielectric layer until the isolation structure 250 is exposed.

[0113] The first metal gate structure 170, the first source / drain epitaxial structure 140 located on both sides of the first metal gate structure 170, and the semiconductor layer 102 in contact with the first source / drain epitaxial structure 140 can serve as Figure 1 In this case, the semiconductor layer 102 in contact with the first source / drain epitaxial structure 140 can also be referred to as the channel layer of the first transistor TR1. Similarly, the second metal gate structure 270, the second source / drain epitaxial structure 240 located on both sides of the second metal gate structure 270, and the semiconductor layer 202 in contact with the second source / drain epitaxial structure 240 can be collectively referred to as the channel layer of the first transistor TR1. Figure 1 In this case, the semiconductor layer 202 in contact with the second source / drain epitaxial structure 240 may be referred to as a channel layer of the second transistor TR2. Fig.17A In the embodiment, both ends of the topmost semiconductor layer 102 are in contact with the isolation structure 150, but not in contact with the first source / drain epitaxial structure 140. Therefore, the topmost semiconductor layer 102 does not serve as the channel layer of the first transistor TR1. Similarly, both ends of the bottommost semiconductor layer 202 are in contact with the isolation structure 150, but not in contact with the second source / drain epitaxial structure 240. Therefore, the bottommost semiconductor layer 202 does not serve as the channel layer of the second transistor TR2.

[0114] Fig.18A and Fig.18B Schematic diagram of a semiconductor device of some embodiments of the present disclosure. It should be noted that Fig.18A The cross-section diagram and FIG. 2A to FIG. 17A The cross-section diagrams of have the same cross-section, Fig.18B The cross-section diagram and Figures 2B to 17B The cross-section diagram of has the same cross-section. It is worth noting that Fig.18A and Fig.18B Some components can be similar to FIG. 2A to FIG. 17B As described above, these components have the same component numbers and the related details will not be repeated.

[0115] Fig.18A and Fig.18B Examples and FIG. 2A to FIG. 17B The difference between the embodiments is that in Fig. 6A and Figure 6B The crystal orientation switching layer 105 is not removed during the process discussed. Therefore, the crystal orientation switching layer 105 can remain in the final structure. This is because the crystal orientation switching layer 105 is made of a dielectric layer, such as a metal oxide, which is different from the semiconductor material of the semiconductor layers 102, 104, 202 and 205. Therefore, the crystal orientation switching layer 105 can provide sufficient etching selectivity to the semiconductor material of the semiconductor layers 102, 104, 202 and 205.

[0116] like Fig.18A As shown, the sidewall of the crystal orientation switching layer 105 may be in contact with the isolation structure 150. In some embodiments, the crystal orientation switching layer 105 may be in contact with the CESL 255, and may be separated from the ILD layer 252 by the CESL 255. In addition, the topmost semiconductor layer 102 may be in contact with the bottom surface of the crystal orientation switching layer 105, and the bottommost semiconductor layer 202 may be in contact with the top surface of the crystal orientation switching layer 105.

[0117] FIG. 19A to FIG. 35B Schematic diagram of a method for forming a semiconductor device at different stages of some embodiments of the present disclosure. It should be noted that Fig.19A , Fig. 20A , Fig.21A , Fig.22A , Fig.23A , Fig.24A , Fig.25A , Fig.26 , Fig.27A , Fig.28A , Fig.29A , Fig. 30A , Fig.31A , Fig.32A , Fig.33A , Fig.34A and Fig.35A The cross-section diagram has FIG. 2A to FIG. 17A The cross-section diagram of the same cross-section, while Fig.19B , Fig. 20B , Fig. 21B , Fig. 22B , Fig. 23B , Fig. 24B , Fig.25B , Fig.27B , Fig.28B , Fig.29B , Fig. 30B , Fig.31B , Fig.32B , Fig.33B , Fig.34B and Fig.35B The cross-section diagram has Figures 2B to 17B The cross-section diagram of the tube is the same as the cross-section diagram of the tube. FIG. 19A to FIG. 35B A series of operations are described, but it should be understood that these operations are not restrictive, and the order of operations can be changed in other embodiments, and the disclosed method is also applicable to other structures. In other embodiments, some operations illustrated and / or described can be omitted in whole or in part. It is worth noting that FIG. 19A to FIG. 35B Some components can be similar to Figure 1 and FIG. 2A to FIG. 17B For the sake of brevity, the relevant details will not be repeated.

[0118] refer to Fig.19A and Fig.19B. A substrate 100 is shown. Then, a first stack ST1 having alternating semiconductor layers 102 and semiconductor layers 104 is formed over the substrate 100. In some embodiments, the substrate 100 may include a first crystal orientation. For example, the first crystal orientation may be a (100) crystal orientation or a (110) crystal orientation. The semiconductor layers 102 and 104 are alternately deposited on the substrate 100. Due to the nature of epitaxial growth, the semiconductor layers 102 and 104 tend to have the same crystal orientation as the substrate 100. Therefore, the semiconductor layers 102 and 104 may also include a first crystal orientation.

[0119] refer to Fig. 20A and Fig. 20B The first stack ST1 and the substrate 100 are patterned to form a fin structure FN1. The fin structure FN1 may include a remaining portion of the first stack ST1 and a semiconductor strip 100P protruding above the substrate 100. After the fin structure FN1 is formed, an isolation structure 106 is formed above the substrate 100 and laterally surrounds the fin structure FN1.

[0120] refer to Fig.21A and Fig. 21B A dummy gate structure 130 is formed above the substrate 100 and across the fin structure FN1. In some embodiments, the patterned mask MA1 is used to form the dummy gate structure 130 as described above. Spacers 115 are formed on opposite sidewalls of each dummy gate structure 130 (see FIG. 1 ). Fig.21A ), and on the opposite sidewalls of the fin structure FN1 (see Fig. 21B In some embodiments, the spacers 115 located on opposite sidewalls of each dummy gate structure 130 may be referred to as gate spacers, and the spacers 115 located on opposite sidewalls of the fin structure FN1 may be referred to as fin spacers.

[0121] refer to Fig.22A and Fig. 22B . Using the dummy gate structure 130 and the spacer 115 as an etching mask, an etching process is performed to remove a portion of the fin structure FN1 (or the stack ST1) to form a source / drain opening. Then, the semiconductor layer 104 is laterally etched to form a sidewall recess, and an inner spacer 116 is formed in the sidewall recess at opposite ends of each semiconductor layer 104. Thereafter, an epitaxial layer 142 is formed at the bottom of the source / drain opening, and then a first source / drain epitaxial structure 140 is formed above the epitaxial layer 142, respectively. The materials and formation methods of the inner spacer 116, the epitaxial layer 142, and the first source / drain epitaxial structure 140 have been described above, and the relevant details are not repeated here.

[0122] In some embodiments, an implantation process may be performed on the first source / drain epitaxial structure 140. For example, when the crystal orientation of the semiconductor layer 102 is (100), the first source / drain epitaxial structure 140 may be doped with n-type dopants, such as phosphorus (P), arsenic (As), or antimony (Sb). Alternatively, when the semiconductor layer 102 has a (110) crystal orientation, the first source / drain epitaxial structure 140 may be doped with p-type dopants, such as boron (B), gallium (Ga), indium (In), aluminum (Al), or the like.

[0123] refer to Fig.23A and Fig. 23B A contact etch stop layer (CESL) 155 is formed covering the first source / drain epitaxial structure 140. Then, an interlayer dielectric (ILD) layer 152 is formed over the CESL 155. Then, a planarization process such as CMP is performed on the ILD layer 152 and the CESL 155 until the dummy gate structure 130 is exposed. In some embodiments, the CESL 155 and the ILD layer 152 may be combined into an isolation structure 150.

[0124] refer to Fig.24A and Fig. 24B The dummy gate structure 130 is removed to form a gate trench GT1 between each pair of spacers 115 . Then, an etching process is performed to remove the semiconductor layer 104 through the gate trench GT1 , so that the semiconductor layer 102 is suspended on the substrate 100 .

[0125] refer to Fig.25A and Fig.25B The interface layers 172 are respectively formed on the exposed surfaces of the semiconductor layer 102. Then, a gate dielectric layer 174 is formed on the interface layer 172, and a gate electrode 176 is formed on the gate dielectric layer 174. Thus, the first metal gate structures 170 are formed, wherein each of the first metal gate structures 170 includes the interface layer 172, the gate dielectric layer 174, and the gate electrode 176. A planarization process, such as CMP, is performed to remove excess gate dielectric layer 174 and gate electrode 176 until the isolation structure 150 is exposed.

[0126] The first metal gate structure 170 is then etched back so that the top surface of the first metal gate structure 170 is lower than the top surface of the spacer 115. Thereafter, a hard mask HM1 is formed over the corresponding first metal gate structure 170. The hard mask HM1 can be formed by, for example, depositing a dielectric layer over the etched back first metal gate structure 170 and then performing a planarization process such as CMP on the dielectric layer until the isolation structure 150 is exposed.

[0127] refer to Fig.26 .exist Fig.25A and Fig.25BThe bonding layer 302 is formed on the structure shown. In more detail, the bonding layer 302 may be in contact with the hard mask HM1, the spacer 115, and the isolation structure 150. In some embodiments, the bonding layer 302 may be deposited on the hard mask HM1 using a suitable deposition process, such as CVD, PVD, ALD, etc. Fig.25A and Fig.25B above the structure shown.

[0128] On the other hand, a substrate 200 is provided. The substrate 200 may include a material similar to the substrate 100. For example, the substrate 200 may be made of silicon. A second stack ST2 having alternating semiconductor layers 202 and semiconductor layers 204 is formed over the substrate 200.

[0129] In some embodiments, the substrate 200 may include a second crystal orientation different from the first crystal orientation of the substrate 100. For example, if the first crystal orientation is the (100) crystal orientation, the second crystal orientation is the (110) crystal orientation. Similarly, if the first crystal orientation is the (110) crystal orientation, the second crystal orientation is the (100) crystal orientation. The semiconductor layers 202 and 204 are alternately deposited on the substrate 200. Due to the nature of epitaxial growth, the semiconductor layers 202 and 204 tend to have the same crystal orientation as the substrate 200. Therefore, the semiconductor layers 202 and 204 may also include a second crystal orientation.

[0130] A bonding layer 304 is formed above the second stack ST2. In some embodiments, the bonding layer 304 contacts the topmost semiconductor layer 204. The bonding layers 302 and 304 may include dielectric materials, such as silicon oxide (SiOx), silicon dioxide (SiO2), or other suitable materials. In some embodiments, the bonding layers 302 and 304 may include the same bonding material. In other embodiments, the bonding layers 302 and 304 may include different bonding materials.

[0131] The substrate 100 will be Fig.26 The arrows shown in FIG. 3 are bonded to the substrate 200. In more detail, the substrate 100 is bonded to the substrate 200 by bonding layers 302 and 304, which will be discussed later.

[0132] refer to Fig.27A and Fig.27B . The substrate 100 is bonded to the substrate 200. For example, Fig.27A and Fig.27B In the embodiment, the substrate 200 is flipped 180 degrees so that the bonding layer 304 on the substrate 200 faces the bonding layer 302 on the substrate 100 .

[0133] Then, the bonding layers 302 and 304 are bonded to each other using a suitable technique. In some embodiments, the bonding process may include surface treatment of the surfaces of the bonding layers 302 and 304, respectively. The surface treatment may include plasma treatment. The plasma treatment may be performed in a vacuum environment. After the plasma treatment, the bonding layers 302 and 304 may also be subjected to surface removal, such as a cleaning process (e.g., rinsing with deionized water, etc.). The bonding layers 302 and 304 are pressed against each other to start the pre-bonding of the substrates 100 and 200. The pre-bonding may be performed at room temperature (between about 21 degrees and about 25 degrees). After the pre-bonding, an annealing process may be performed on the bonding layers 302 and 304 that have been pressed against each other. The annealing process increases the bonding force between the bonding layers 302 and 304, so that even if the bonding layers 302 and 304 are no longer subjected to pressure, they will not separate or peel from each other. In some embodiments, the bonding layers 302 and 304 may be combined and referred to as the bonding structure 300. In some embodiments, the bonding layers 302 and 304 may each be referred to as a dielectric layer or an isolation layer, and the bonding structure 300 may be referred to as a dielectric structure or an isolation structure.

[0134] refer to Fig.28A and Fig.28B A grinding process is performed on the back side of the substrate 200 (see Fig.27A and Fig.27B ) to remove the substrate 200 until the topmost semiconductor layer 202 is exposed.

[0135] refer to Fig.29A and Fig.29B A patterning process is performed on the second stack ST2 to form a fin structure FN2. In some embodiments, the patterning process may include forming a patterned photoresist layer over the second stack ST2, and then performing an etching process to remove an unnecessary portion of the second stack ST2 exposed by the patterned photoresist layer. The fin structure FN2 may include a remaining portion of the second stack ST2.

[0136] refer to Fig. 30A and Fig. 30B A dummy gate structure 230 is formed across the fin structure FN2. In some embodiments, each dummy gate structure 230 includes a dummy gate dielectric 232 and a dummy gate electrode 234 over the dummy gate dielectric 232. The materials of the dummy gate dielectric 232 and the dummy gate electrode 234 may be similar to the materials of the dummy gate dielectric 132 and the dummy gate electrode 134, and thus the related details will not be repeated.

[0137] The dummy gate electrode 234 and the dummy gate dielectric 232 can be formed by, for example, depositing a dummy gate dielectric layer and a dummy gate layer on the fin structure FN2, forming a patterned mask MA2 on the dummy gate layer, and then performing an etching process on the dummy dielectric layer and the dummy gate layer using the patterned mask MA2 as an etching mask. In some embodiments, each patterned mask MA2 includes a first hard mask 334 and a second hard mask 336 located above the first hard mask 334. In some embodiments, the first hard mask 334 can be formed of silicon nitride, and the second hard mask 336 can be formed of silicon oxide.

[0138] Spacers 215 are formed on opposite sidewalls of each dummy gate structure 230. The materials and formation methods of the spacers 215 may be similar to those described with respect to the spacers 115, and thus the relevant details will not be repeated.

[0139] refer to Fig.31A and Fig.31B The dummy gate structure 230 and the spacer 215 are used as etching masks to perform an etching process to remove a portion of the fin structure FN2 (or the second stack ST2), thereby forming a source / drain opening O2. Then, the semiconductor layer 204 is laterally etched to form sidewall recesses, and inner spacers 216 are formed in the sidewall recesses at opposite ends of each semiconductor layer 204.

[0140] refer to Fig.32A and Fig.32B . A second source / drain epitaxial structure 240 is formed on opposite sides of each semiconductor layer 202. In some embodiments, an implantation process may be performed on the second source / drain epitaxial structure 240. For example, when the semiconductor layer 202 has a (100) crystal orientation, the second source / drain epitaxial structure 240 may be doped with an n-type dopant, such as phosphorus (P), arsenic (As), or antimony (Sb). Alternatively, when the semiconductor layer 202 has a (110) crystal orientation, the second source / drain epitaxial structure 240 may be doped with a p-type dopant, such as boron (B), gallium (Ga), indium (In), aluminum (Al), or the like. In some embodiments, the first source / drain epitaxial structure 140 and the second source / drain epitaxial structure 240 may include dopants of opposite conductivity types. For example, if the first source / drain epitaxial structure 140 is doped with an n-type dopant, the second source / drain epitaxial structure 240 is doped with a p-type dopant. Similarly, if the first source / drain epitaxial structure 140 is doped with a p-type dopant, the second source / drain epitaxial structure 240 is doped with an n-type dopant. Fig.32B In the cross-sectional view of , the second source / drain epitaxial structure 240 may include a different width than the first source / drain epitaxial structure 140 .

[0141] refer to Fig.33A and Fig.33B. A contact etch stop layer (CESL) 255 is formed covering the second source / drain epitaxial structure 240. Thereafter, an interlayer dielectric (ILD) layer 252 is formed over the CESL 255. Then, a planarization process, such as CMP, is performed to remove excess material of the CESL 255 and the ILD layer 252 until the dummy gate structure 230 is exposed. In some embodiments, the patterned mask MA2 is removed during the planarization process. In some embodiments, the CESL 255 and the ILD layer 252 may be combined to be referred to as an isolation structure 250.

[0142] refer to Fig.34A and Fig.34B The dummy gate structure 230 is removed to form a gate trench GT2 between each pair of spacers 215 . Then, an etching process is performed to remove the semiconductor layer 204 through the gate trench GT2 , so that the semiconductor layer 202 is suspended on the bonding structure 300 .

[0143] refer to Fig.35A and Fig.35B The interface layers 272 are respectively formed on the exposed surfaces of the semiconductor layer 202. Thereafter, a gate dielectric layer 274 is formed on the interface layer 272, and a gate electrode 276 is formed on the gate dielectric layer 274. Thus, the second metal gate structures 270 are formed, wherein each second metal gate structure 270 includes the interface layer 272, the gate dielectric layer 274, and the gate electrode 276. A planarization process, such as CMP, is performed to remove excess interface layer 272, excess gate dielectric layer 274, and excess gate electrode 276 until the isolation structure 250 is exposed.

[0144] Next, the second metal gate structure 270 is etched back so that the top surface of the second metal gate structure 270 is lower than the top surface of the spacer 215. Thereafter, a hard mask HM2 is formed over the corresponding second metal gate structure 270. The hard mask HM2 can be formed by, for example, depositing a dielectric layer over the etched back second metal gate structure 270 and then performing a planarization process such as CMP on the dielectric layer until the isolation structure 250 is exposed.

[0145] The first metal gate structure 170, the first source / drain epitaxial structure 140 located on both sides of the first metal gate structure 170, and the semiconductor layer 102 in contact with the first source / drain epitaxial structure 140 can serve as Figure 1In this case, the semiconductor layer 102 in contact with the first source / drain epitaxial structure 140 can also be referred to as the channel layer of the first transistor TR1. Similarly, the second metal gate structure 270, the second source / drain epitaxial structure 240 located on both sides of the second metal gate structure 270, and the semiconductor layer 202 in contact with the second source / drain epitaxial structure 240 can be collectively referred to as the channel layer of the first transistor TR1. Figure 1 The second transistor TR2 is shown. In this case, the semiconductor layer 202 in contact with the second source / drain epitaxial structure 240 may be referred to as a channel layer of the second transistor TR2.

[0146] like Fig.35A As shown, the bonding structure 300 is disposed between the first transistor TR1 and the second transistor TR2. The bottom surface of the bonding structure 300 may contact the spacer 115, the isolation structure 150, and the hard mask HM1. The top surface of the bonding structure 300 may contact the metal gate structure 270, the inner spacer 216, and the second source / drain epitaxial structure 240.

[0147] Figures 36 to 38B Schematic diagram of a method for forming a semiconductor device at different stages of some embodiments of the present disclosure. It should be noted that Fig.36 , Fig.37A and Fig.38A The cross-section diagram has FIG. 19A to FIG. 35A The cross-section diagram of the same cross-section, while Fig.37B and Fig.38B The cross-section diagram has FIG. 19B to FIG. 35B The cross-section diagram of the same cross-section. Figures 36 to 38B A series of operations are described, but it should be understood that these operations are not restrictive, and the order of operations can be changed in other embodiments, and the disclosed method is also applicable to other structures. In other embodiments, some operations illustrated and / or described can be omitted in whole or in part. It is worth noting that Figures 36 to 38B Some components can be similar to Figure 1 and FIG. 19A to FIG. 35B For the sake of brevity, the relevant details will not be repeated.

[0148] refer to Fig.36 . Fig.36 Similar to Fig.26 ,and Fig.36 and Fig.26 The difference between Fig.26 The substrate 200 discussed is omitted. Instead, Fig.36 In the present invention, a substrate 400 is provided. Next, a crystal orientation switching layer 405 is formed on the substrate 400. Then, a second stack ST2 having alternating semiconductor layers 202 and semiconductor layers 204 is formed on the crystal orientation switching layer 405. A bonding layer 304 is formed on the second stack ST2.

[0149] In some embodiments, the substrate 400 may include a material similar to that of the substrate 100. For example, the substrate 400 may be made of silicon. The substrate 400 may include a first crystal orientation that is the same as that of the substrate 100. For example, the first crystal orientation may be a (100) crystal orientation or a (110) crystal orientation.

[0150] The crystal orientation switching layer 405 may include a second crystal orientation different from the first crystal orientation of the substrate 400. For example, if the first crystal orientation is the (100) crystal orientation, the second crystal orientation is the (110) crystal orientation. Similarly, if the first crystal orientation is the (110) crystal orientation, the second crystal orientation is the (100) crystal orientation.

[0151] The crystal orientation switching layer 405 may be made of a dielectric material, such as a metal oxide. In some embodiments, the metal oxide may include yttrium oxide (Y2O3), cerium oxide (CeO2), a composite oxide system (such as (La x Y 1-x )2O3(LaYO), or containing two or more metal elements), or the like. In some embodiments, because oxygen and silicon have similar lattice constants, silicon atoms can be bonded with oxygen atoms in the dielectric layer with a small lattice mismatch, so that the crystal orientation switching layer 405 can be epitaxially grown on the semiconductor layer (e.g., substrate 400) without a serious lattice mismatch problem.

[0152] In addition, the experimental results also show that during the deposition of the crystal orientation switching layer 405 on the semiconductor layer (e.g., substrate 400), the crystal orientation of the crystal orientation switching layer 405 is controllable. In detail, the crystal orientation of the crystal orientation switching layer 405 depends on the temperature during the deposition process. That is, by controlling the deposition temperature of the crystal orientation switching layer 405, the crystal orientation switching layer 405 can obtain a desired crystal orientation.

[0153] For example, in an embodiment where the substrate 400 is made of silicon and has a (100) crystal orientation, a deposition temperature of about 400° C. to 500° C. (e.g., 450° C. in this example) may produce a crystal orientation switching layer 405 having a (110) crystal orientation. If the deposition temperature is outside this range, the crystal orientation switching layer 405 may have an undesirable crystal orientation. For example, if the deposition temperature is about 60° C., the crystal orientation switching layer 405 may have a random crystal orientation (e.g., a polycrystalline structure). If the deposition temperature is about 270° C., the crystal orientation switching layer 405 has a (111) crystal orientation.

[0154] Based on the above discussion, it can be seen that the crystal orientation of the crystal orientation switching layer 405 can be switched from the first crystal orientation of the substrate 400 to the second crystal orientation by selecting the material and deposition temperature of the crystal orientation switching layer 405. The switched crystal orientation is beneficial to make the subsequently grown semiconductor layers 202 and 204 have a different crystal orientation from the substrate 400.

[0155] Semiconductor layers 202 and 204 are alternately deposited on the orientation switching layer 405. Due to the nature of epitaxial growth, semiconductor layers 202 and 204 tend to have the same orientation as the orientation switching layer 405. Therefore, semiconductor layers 202 and 204 may also include the same second orientation as the orientation switching layer 405.

[0156] refer to Fig.37A and Fig.37B . The substrate 100 is bonded to the substrate 400. For example, Fig.37A and Fig.37B In the embodiment, the substrate 400 is flipped 180 degrees so that the bonding layer 304 on the substrate 400 faces the bonding layer 302 on the substrate 100. Then, the bonding layers 302 and 304 are bonded using the appropriate method discussed above, and the bonded bonding layers 302 and 304 can be combined and referred to as a bonding structure 300.

[0157] refer to Fig.38A and Fig.38B The back side of the substrate 400 is ground (see Fig.37A and Fig.37B ) to remove the substrate 400 and the crystal orientation switching layer 405 until the uppermost semiconductor layer 202 is exposed. Then, Fig.38A and Fig.38B The structure can undergo FIG. 29A to FIG. 25B The process discussed, the resulting structure and Fig.35A and Fig.35B same.

[0158] According to the above embodiments, it can be seen that the present disclosure provides advantages in manufacturing integrated circuits. However, it should be understood that other embodiments may provide additional advantages, and not all advantages must be disclosed herein, and all embodiments do not require specific advantages. The present disclosure provides a CFET, comprising a first transistor and a second transistor located above the first transistor. The channel layer of the first transistor and the channel layer of the second transistor may include different crystal orientations. For example, a channel layer with a (100) crystal orientation is applied to an n-type transistor, while a channel layer with a (110) crystal orientation is applied to a p-type transistor. By selecting a suitable channel layer crystal orientation for the conductivity type of the transistor, the device performance can be improved. In addition, a crystal orientation switching layer is added to the manufacturing method of the CFET, and the crystal orientation switching layer allows the channel layer of the upper second transistor to have a different crystal orientation from the channel layer of the lower first transistor. The embodiments of the present disclosure improve the device performance by increasing the carrier mobility of the N-type channel and the P-type channel. In addition, the crystal orientation switching layer with a smaller lattice mismatch also increases the critical thickness, which will also improve the quality of the channel layer of the second transistor and make the structure more flexible. The crystal orientation switching layer also allows epitaxial growth on the dielectric layer. The crystal orientation switching layer also provides sufficient etching selectivity for semiconductor materials.

[0159] According to some embodiments of the present disclosure, a semiconductor element includes a first transistor and a second transistor. A first transistor includes a first semiconductor channel layer, a first gate structure, and a first source / drain epitaxial structure. The first semiconductor channel layer has a first crystal orientation. The first gate structure surrounds the first semiconductor channel layer. The first source / drain epitaxial structure is located at opposite ends of the first semiconductor channel layer. The second transistor is located above the first transistor and has a different conductivity type from the first transistor, wherein the second transistor includes a second semiconductor channel layer, a second gate structure, and a second source / drain epitaxial structure. The second semiconductor channel layer has a second crystal orientation different from the first crystal orientation. The second gate structure surrounds the second semiconductor channel layer. The second source / drain epitaxial structure is located at opposite ends of the second semiconductor channel layer.

[0160] In some embodiments, the first crystal orientation is a (100) crystal orientation and the first transistor is an N-type transistor, while the second crystal orientation is a (110) crystal orientation and the first transistor is a P-type transistor.

[0161] In some embodiments, the first crystal orientation is a (110) crystal orientation and the first transistor is a P-type transistor, while the second crystal orientation is a (100) crystal orientation and the first transistor is an N-type transistor.

[0162] In some embodiments, the first transistor is vertically located between a substrate and the second transistor, wherein the substrate has a third crystal orientation that is the same as the first crystal orientation.

[0163] In some embodiments, the semiconductor device further includes a dielectric layer vertically disposed between the first transistor and the second transistor.

[0164] In some embodiments, the semiconductor device further includes an isolation structure, a first semiconductor layer, and a second semiconductor layer. The isolation structure is located between one of the first source / drain epitaxial structures and one of the second source / drain epitaxial structures. The first semiconductor layer is located above the first gate structure of the first transistor and contacts a side wall of the isolation structure, wherein the first semiconductor layer has a third crystal orientation that is the same as the first crystal orientation. The second semiconductor layer is located below the second gate structure of the second transistor and contacts a side wall of the isolation structure, wherein the second semiconductor layer has a fourth crystal orientation that is the same as the second crystal orientation.

[0165] In some embodiments, the semiconductor device further includes an isolation layer located between the first semiconductor layer and the second semiconductor layer and contacting the sidewall of the isolation structure.

[0166] In some embodiments, the semiconductor device further includes a metal oxide layer vertically located between the first transistor and the second transistor, wherein the metal oxide layer has a third crystal orientation that is the same as the second crystal orientation.

[0167] According to some embodiments of the present disclosure, a semiconductor element includes a first transistor, a second transistor, a dielectric layer, and an isolation structure. The first transistor includes a first semiconductor channel layer, a first gate structure, and a first source / drain epitaxial structure. The first gate structure surrounds the first semiconductor channel layer. The first source / drain epitaxial structure is located at opposite ends of the first semiconductor channel layer. The second transistor is located above the first transistor, and includes a second semiconductor channel layer, a second gate structure, and a second source / drain epitaxial structure. The second semiconductor channel layer has a first crystal orientation. The second gate structure surrounds the second semiconductor channel layer. The second source / drain epitaxial structure is located at opposite ends of the second semiconductor channel layer. The dielectric layer is vertically located between the first gate structure and the second gate structure, wherein the dielectric layer has a second crystal orientation that is the same as the first crystal orientation. The isolation structure is located between one of the first source / drain epitaxial structures and one of the second source / drain epitaxial structures.

[0168] In some embodiments, the dielectric layer is composed of metal oxide.

[0169] In some embodiments, the metal oxide includes yttrium oxide or cerium oxide.

[0170] In some embodiments, the first semiconductor channel layer has a third crystal orientation different from the first crystal orientation.

[0171] In some embodiments, the semiconductor device further includes a first semiconductor layer and a second semiconductor layer, wherein the first semiconductor layer contacts the bottom surface of the dielectric layer, and the second semiconductor layer contacts the top surface of the dielectric layer, wherein the first semiconductor layer and the second semiconductor layer have different crystal orientations.

[0172] In some embodiments, the dielectric layer contacts the isolation structure.

[0173] According to some embodiments of the present disclosure, a method includes forming a first stack having alternating first semiconductor channel layers and first sacrificial layers on a first substrate, wherein the first semiconductor channel layers have a first crystal orientation; forming a second stack having alternating second semiconductor channel layers and second sacrificial layers above the first stack, wherein the second semiconductor channel layers have a second crystal orientation different from the first crystal orientation; forming a first source / drain epitaxial structure at opposite ends of each of the first semiconductor channel layers; forming a second source / drain epitaxial structure at opposite ends of each of the second semiconductor channel layers; replacing the first sacrificial layer with a first gate structure, the first gate structure wrapping around each of the first semiconductor channel layers; and replacing the second sacrificial layer with a second gate structure, the second gate structure wrapping around each of the second semiconductor channel layers.

[0174] In some embodiments, the method further includes forming an orientation switching layer above the first stack, wherein the second stack is formed above the orientation switching layer, and wherein the orientation switching layer has a third orientation that is different from the first orientation and the same as the second orientation.

[0175] In some embodiments, the method further includes replacing the crystal orientation switching layer with an isolation layer before forming the first source / drain epitaxial structure.

[0176] In some embodiments, the crystal orientation switching layer is composed of metal oxide.

[0177] In some embodiments, the first crystal orientation is a (100) crystal orientation, and wherein a crystal orientation switching layer is formed on a topmost layer of the first semiconductor channel layer, and the crystal orientation switching layer is deposited at a temperature ranging from about 400° C. to about 500° C., so that the third crystal orientation is a (110) crystal orientation.

[0178] In some embodiments, forming a second stack having alternating second semiconductor channel layers and second sacrificial layers above a first stack includes forming a second stack having alternating second semiconductor channel layers and second sacrificial layers above a second substrate, wherein the second substrate has a third crystal orientation that is the same as the second crystal orientation; forming a first bonding layer above the first stack having alternating first semiconductor channel layers and first sacrificial layers; forming a second bonding layer above the second stack having alternating second semiconductor channel layers and second sacrificial layers; bonding the first bonding layer and the second bonding layer; and removing the second substrate.

[0179] According to some embodiments of the present disclosure, a semiconductor element includes a first transistor and a second transistor. A first transistor includes a first semiconductor channel layer, a first gate structure, and a first source / drain epitaxial structure. The first semiconductor channel layer has a first crystal orientation. The first gate structure surrounds the first semiconductor channel layer. The first source / drain epitaxial structure is located at opposite ends of the first semiconductor channel layer. The second transistor is located above the first transistor and has a different conductivity type from the first transistor, wherein the second transistor includes a second semiconductor channel layer, a second gate structure, and a second source / drain epitaxial structure. The second semiconductor channel layer has a second crystal orientation different from the first crystal orientation. The second gate structure surrounds the second semiconductor channel layer. The second source / drain epitaxial structure is located at opposite ends of the second semiconductor channel layer. A dielectric layer is vertically located between the first transistor and the second transistor.

[0180] The foregoing summarizes the features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art will appreciate that they may readily use the present disclosure as a basis for designing or modifying other processing procedures and structures for carrying out the same purposes and / or achieving the same advantages of the embodiments described herein. Those skilled in the art will also appreciate that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may be variously modified, substituted, and altered without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor element, characterized in that: Include: A first transistor comprising: a first semiconductor channel layer, wherein the first semiconductor channel layer has a first crystal orientation; a first gate structure surrounding the first semiconductor channel layer; and A first source / drain epitaxial structure is located at two opposite ends of the first semiconductor channel layer; and a second transistor is located above the first transistor and has a conductivity type different from that of the first transistor, wherein the second transistor comprises: a second semiconductor channel layer, wherein the second semiconductor channel layer has a second crystal orientation different from the first crystal orientation; a second gate structure surrounding the second semiconductor channel layer; and The second source / drain epitaxial structure is located at two opposite ends of the second semiconductor channel layer.

2. The semiconductor device according to claim 1, wherein: The first crystal orientation is 100 crystal orientation and the first transistor is an N-type transistor, while the second crystal orientation is 110 crystal orientation and the first transistor is a P-type transistor.

3. The semiconductor device according to claim 1, wherein: The first crystal orientation is 110 and the first transistor is a P-type transistor, while the second crystal orientation is 100 and the first transistor is an N-type transistor.

4. The semiconductor device according to claim 1, wherein: The first transistor is vertically located between a substrate and the second transistor, wherein the substrate has a third crystal orientation that is the same as the first crystal orientation.

5. The semiconductor device according to claim 1, wherein: A dielectric layer is also included and is vertically located between the first transistor and the second transistor.

6. The semiconductor device according to claim 1, wherein: Also includes: an isolation structure located between one of the first source / drain epitaxial structures and one of the second source / drain epitaxial structures; a first semiconductor layer, located above the first gate structure of the first transistor and contacting a sidewall of the isolation structure, wherein the first semiconductor layer has a third crystal orientation that is the same as the first crystal orientation; as well as A second semiconductor layer is located below the second gate structure of the second transistor and contacts the sidewall of the isolation structure, wherein the second semiconductor layer has a fourth crystal orientation that is the same as the second crystal orientation.

7. The semiconductor device according to claim 6, wherein: The invention also comprises an isolation layer, which is located between the first semiconductor layer and the second semiconductor layer and contacts the side wall of the isolation structure.

8. The semiconductor device according to claim 1, wherein: The invention also comprises a metal oxide layer vertically located between the first transistor and the second transistor, wherein the metal oxide layer has a third crystal orientation which is the same as the second crystal orientation.

9. A semiconductor element, characterized in that: Include: A first transistor comprising: a first semiconductor channel layer; a first gate structure surrounding the first semiconductor channel layer; and A first source / drain epitaxial structure is located at two opposite ends of the first semiconductor channel layer; a second transistor, located above the first transistor, comprising: a second semiconductor channel layer, wherein the second semiconductor channel layer has a first crystal orientation; a second gate structure surrounding the second semiconductor channel layer; and A second source / drain epitaxial structure is located at two opposite ends of the second semiconductor channel layer; a dielectric layer vertically disposed between the first gate structure and the second gate structure, wherein the dielectric layer has a second crystal orientation that is the same as the first crystal orientation; and An isolation structure is located between one of the first source / drain epitaxial structures and one of the second source / drain epitaxial structures.

10. A semiconductor element, characterized in that: Include: A first transistor comprising: a first semiconductor channel layer, wherein the first semiconductor channel layer has a first crystal orientation; a first gate structure surrounding the first semiconductor channel layer; and A first source / drain epitaxial structure is located at two opposite ends of the first semiconductor channel layer; a second transistor, located above the first transistor and having a conductivity type different from that of the first transistor, wherein the second transistor comprises: a second semiconductor channel layer, wherein the second semiconductor channel layer has a second crystal orientation different from the first crystal orientation; a second gate structure surrounding the second semiconductor channel layer; as well as A second source / drain epitaxial structure is located at two opposite ends of the second semiconductor channel layer; and a dielectric layer is vertically located between the first transistor and the second transistor.

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