Memory read-write DMA controller based on FIFO interface
By designing a memory read and write DMA controller based on the FIFO interface in FPGA, the problems of application complexity and development difficulty of DDR memory controller in the prior art are solved, and more efficient memory read and write operations and development efficiency are achieved.
Patent Information
- Application Number
- CN202323664173.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-29
- Publication Date
- 2025-01-10
- Estimated Expiration
- 2033-12-29
AI Technical Summary
The existing DDR memory controller based on FPGA is relatively complex, and developers need to be familiar with the standard bus interface, which makes it difficult to quickly master and adapt to the FIFO interface to improve memory read and write efficiency.
A memory read and write DMA controller based on FIFO interface is designed, including FPGA devices, data cache FIFO IP core, DMA controller and DDR memory controller IP core, and user data write and write and write user data through LocalBus bus to AXI4 bus module. Reading reduces dependence on standard bus interfaces and provides FIFO write and read interfaces to simplify user operations.
It reduces the development difficulty of FPGA developers, improves development efficiency, and makes memory read and write operations more flexible and efficient, suitable for rapid porting of different application scenarios.
Smart Images
Figure CN222337616U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of DMA control, in particular to a memory read-write DMA controller based on a FIFO interface. Background Art
[0002] In the existing physical memory application solutions based on programmable logic devices FPGA, FPGA devices based on Xilinx or Altera and memory controller IP cores integrated by the manufacturers are generally used for development. The external user interface of such IP cores is a standard AXI4 bus, Native bus or standard Avalon MM bus interface. The application of this type of interface is relatively complex, and FPGA developers need to be familiar with the specifications of this type of bus before they can apply it. Therefore, it is relatively difficult for FPGA developers and has low application flexibility.
[0003] It can be seen that how to quickly master the application of DDR memory controller IP core and convert the above standard bus interface to adapt to the FIFO read and write user interface, so as to reduce the development difficulty, improve the development efficiency, and meet the memory read and write efficiency requirements is an urgent problem to be solved. Utility Model Content
[0004] In order to solve the above technical problems, the utility model provides a memory read-write DMA controller based on a FIFO interface, comprising:
[0005] An FPGA device, the FPGA device comprising an application layer, a data cache FIFO IP core, a DMA controller and a DDR memory controller IP core, wherein the DMA controller comprises a LocalBus bus to AXI4 bus module, the LocalBus bus to AXI4 bus module is communicatively connected with the DDR memory controller IP core, and the data cache FIFO IP core is used through an interface of the application layer to complete write and read operations of user data; and
[0006] DDR memory particles, wherein the DDR memory particles are externally mounted on external pins of the FPGA device.
[0007] Furthermore, the application layer includes a FIFO write interface and a FIFO read interface, the data cache FIFO IP core includes a write operation cache FIFO IP core and a read operation cache FIFO IP core, the FIFO write interface is connected to the input end of the write operation cache FIFO IP core, and the FIFO read interface is connected to the input end of the read operation cache FIFO IP core.
[0008] Furthermore, the DMA controller includes a DMA write control module of the DDR memory and a DMA read control module of the DDR memory.
[0009] Furthermore, the write operation cache FIFO IP core is connected to a read "write operation cache" FIFO control module at a later stage, and the read operation cache FIFO IP core is connected to a write "read operation cache" IP control module at a later stage.
[0010] Furthermore, the user writes data into the write operation cache FIFO IP core through the FIFO write interface, the read "write operation cache" FIFO control module reads data from the write operation cache FIFO IP core and passes it to the DMA controller, and the DMA controller writes the data into the DDR memory particles through the DDR memory controller IP core.
[0011] Furthermore, the write "read operation cache" IP control module is connected to the interface of the application layer, and the user obtains the data amount information in the read operation cache FIFO IP core through the FIFO read interface, and the DMA controller reads the data in the read operation cache FIFO IP core.
[0012] Furthermore, the amount of data transmitted by the DMA controller at one time is less than or equal to 4096 bytes.
[0013] Compared with the prior art, the utility model has the following beneficial effects:
[0014] The memory application DMA controller based on the FIFO read and write interface of the utility model is convenient for FPGA developers to use, reduces the development difficulty, and is also easy to apply and transplant, thus greatly improving the development efficiency of the project. BRIEF DESCRIPTION OF THE DRAWINGS
[0015] Figure 1 It is the principle diagram of the utility model;
[0016] Figure 2 It is the principle diagram of the utility model.
[0017] In the figure: 100, FPGA device; 110, application layer; 120, write operation cache FIFO IP core; 121, read operation cache FIFO IP core; 130, read "write operation cache" FIFO control module; 131, write "read operation cache" IP control module; 140, DMA controller; 150, DDR memory controller IP core; 200, DDR memory particles. DETAILED DESCRIPTION
[0018] In order to make the technical scheme and technical effect of the utility model clearer, the technical scheme in the embodiment of the utility model will be clearly and completely described below in conjunction with the drawings in the embodiment. Obviously, the described embodiment is only a part of the embodiment of the utility model, not all of the embodiments.
[0019] like Figure 1 , 2 As shown (It should be noted that: in order to facilitate the clear display of the figure, the original whole figure is cut into Figure 1 and Figure 2 ), the utility model aims to provide a memory read-write DMA controller based on FIFO interface, mainly including FPGA device 100 and DDR memory particle 200, and DDR memory particle is externally mounted on the external pin of FPGA device 100. Among them, FPGA device 100 includes application layer 110, data cache FIFO IP core, DMA controller 140 and DDR memory controller IP core 150.
[0020] The data cache FIFO IP core includes a write cache FIFO IP core 120 and a read cache FIFO IP core 121. The write cache FIFO IP core 120 is connected to a read "write cache" FIFO control module 130, and the read cache FIFO IP core 121 is connected to a write "read cache" IP control module 131.
[0021] The application layer 110 includes a FIFO write interface and a FIFO read interface. The FIFO write interface is connected to the input end of the write operation cache FIFO IP core 120, and the FIFO read interface is connected to the input end of the read operation cache FIFO IP core 121.
[0022] The DMA controller 140 includes a DMA write control module of the DDR memory, a DMA read control module of the DDR memory, and a LocalBus bus to AXI4 bus module. The LocalBus bus to AXI4 bus module is communicatively connected to the DDR memory controller IP core 150 .
[0023] The read operation cache FIFO IP core 121 and the DDR memory controller IP core 150 are Xilinx official IP cores.
[0024] FPGA developers use the write operation cache FIFO IP core 120 and the read operation cache FIFO IP core 121 through the interface of the application layer 110 to complete the user data write DDR memory and read DDR memory operations, reducing the user's difficulty in using the DDR memory controller IP core 150, thereby improving development efficiency. The main technical measures of this process include user DMA write to DDR memory, DMA read of DDR memory, and AXI4 address boundary processing. The specific process is as follows:
[0025] 1. The DMA write process of DDR memory, the specific steps are as follows:
[0026] First, the user sets the DMA write data length and DMA write DDR memory address information before initiating a write request;
[0027] The user writes data into the write operation cache FIFO IP core 120 through the FIFO write interface;
[0028] The read "write operation cache" FIFO control module 130 determines whether the "read FIFO threshold" is reached according to the data amount information rd_data_count written by the previous write operation cache FIFO IP core 120. If yes, a DMA write DDR memory request is initiated, otherwise, continue to wait;
[0029] Determine whether DMA can perform write operation, if yes, initiate DMA write request, at this time, read "write operation cache" FIFO control module 130 reads data from write operation cache FIFO IP core 120 and passes it to DMA controller 140;
[0030] The DMA controller 140 writes the required data into the external DDR memory particle 200 through the DDR memory controller IP core 150 .
[0031] 2. The DMA reading process of DDR memory, the specific steps are as follows:
[0032] First, the user sets the DMA read data length and DMA write DDR memory address information;
[0033] After the setting is completed, the user initiates a read request to write the "read operation cache" IP control module 131;
[0034] The DMA controller 140 informs whether a DMA operation is possible, and if so, performs a DMA read operation, otherwise waits;
[0035] The user obtains the data volume information wr_data_count in the read operation cache FIFO IP core 121 through the FIFO read interface, and determines that the data volume in the FIFO reaches the readable threshold;
[0036] The user starts to read the data in the read operation buffer FIFO IP core 121 .
[0037] 3. AXI4 bus address crosses 4KB boundary
[0038] The AXI4 bus standard requires that the bus cannot cross the 4096-byte address boundary during the read and write process, otherwise it will cause read and write failures; to solve this problem, the user layer needs to perform batch operations based on the data length information of each DMA write or read operation, thereby avoiding the AXI address boundary problem. The implementation instructions are as follows:
[0039] Before initiating a DMA read or write operation, the user sets the data length information of this DMA operation to determine the data length of the DMA operation; if the data length of the DMA operation is greater than 4096 bytes, multiple DMA operations are required, otherwise only one DMA operation is required.
[0040] In multiple DMA operations, the amount of data transferred each time is no more than 4096 bytes, and it will not end until all DMA operations are completed.
[0041] The utility model reduces the development difficulty and is convenient for FPGA developers to use; the memory DMA controller based on the FIFO interface is also easy to apply and transplant, and can be quickly and simply transplanted to application occasions with different requirements, greatly improving project development efficiency.
[0042] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the appended claims and their equivalents.
Claims
1. A memory read / write DMA controller based on a FIFO interface, characterized in that: include: An FPGA device (100), the FPGA device (100) comprising an application layer (110), a data cache FIFO IP core, a DMA controller (140) and a DDR memory controller IP core (150), wherein the DMA controller (140) comprises a LocalBus bus to AXI4 bus module, the LocalBus bus to AXI4 bus module is communicatively connected to the DDR memory controller IP core (150), and the data cache FIFO IP core is used to complete user data write and read operations through an interface of the application layer (110); and A DDR memory particle (200) is mounted on an external pin of the FPGA device (100).
2. The memory read-write DMA controller based on FIFO interface according to claim 1, characterized in that: The application layer (110) comprises a FIFO write interface and a FIFO read interface, the data cache FIFO IP core comprises a write operation cache FIFO IP core (120) and a read operation cache FIFO IP core (121), the FIFO write interface is connected to an input end of the write operation cache FIFO IP core (120), and the FIFO read interface is connected to an input end of the read operation cache FIFO IP core (121).
3. The memory read-write DMA controller based on FIFO interface according to claim 1, characterized in that: The DMA controller (140) comprises a DMA write control module of the DDR memory and a DMA read control module of the DDR memory.
4. The memory read-write DMA controller based on FIFO interface according to claim 2, characterized in that: The write operation cache FIFO IP core (120) is connected to a read "write operation cache" FIFO control module (130) at a later stage, and the read operation cache FIFO IP core (121) is connected to a write "read operation cache" IP control module (131) at a later stage.
5. The memory read-write DMA controller based on FIFO interface according to claim 4, characterized in that: The user writes data into the write operation cache FIFO IP core (120) through the FIFO write interface, the read "write operation cache" FIFO control module (130) reads the data from the write operation cache FIFO IP core (120) and transmits the data to the DMA controller (140), and the DMA controller (140) writes the data into the DDR memory particle (200) through the DDR memory controller IP core (150).
6. The memory read-write DMA controller based on FIFO interface according to claim 4, characterized in that: The write "read operation cache" IP control module (131) is connected to the application layer (110), and the user obtains data amount information in the read operation cache FIFO IP core (121) through the FIFO read interface, and the DMA controller (140) reads data in the read operation cache FIFO IP core (121).
7. The memory read-write DMA controller based on FIFO interface according to claim 4, characterized in that: The amount of data transmitted by the DMA controller (140) at one time is less than or equal to 4096 bytes.