SiC-based split gate groove type IGBT semiconductor device structure

Abstract

The utility model relates to an improvement of a groove type IGBT semiconductor device structure, in particular to a SiC-based split gate groove type IGBT semiconductor device structure, which can be used for manufacturing a SiC-based IGBT semiconductor device with higher current density on the premise of not increasing the difficulty of the existing process and the manufacturing cost. Comprising a first conductive type substrate (1); the second-type conductive buffer layer (2) is arranged at the upper part of the first-type conductive substrate (1); a second conductivity type drift layer (3) disposed above the second conductivity type buffer layer (2); the first-type conductive doped region (4) is arranged on the upper surface of the second-type conductive drift layer (3); the second-type conductive doped region (5) is arranged on the local upper surface of the first-type conductive doped region (4); and the groove (6) is arranged on the upper surface of the second conductive type drift layer (3) and penetrates through the first conductive type doped region (4) and the second conductive type doped region (5), and the groove (6) extends into the second conductive type drift layer (3).

Description

Technical Field

[0001] The utility model relates to a design improvement of a trench-type IGBT semiconductor device structure, in particular to a SiC-based split-gate trench-type IGBT semiconductor device structure. Background Art

[0002] Conventional Si-based semiconductor devices have inherent disadvantages compared to devices made from wide-bandgap semiconductors (SiC). Wide-bandgap semiconductors offer higher electron mobility and higher bandgap energy. SiC devices offer advantages over Si devices primarily in three areas: reduced energy loss during power conversion, easier miniaturization, and improved high-temperature and pressure resistance. Furthermore, SiC-based split-gate trench IGBT semiconductor devices offer lower on-state voltage drop and greater current capability than conventional planar-gate and trench-type devices.

[0003] The insulated gate bipolar transistor (IGBT) is a fully controlled, voltage-driven, composite power semiconductor device composed of a bipolar junction transistor (BJT) and an insulated gate field-effect transistor (MOS). Its switching speed is higher than that of a BJT, and as a voltage-controlled device, it offers excellent stability. It combines the advantages of a MOSFET's high input impedance with a BJT's low on-state voltage drop. Due to its low switching losses, simple gate control, and excellent switching controllability, the IGBT has become a new generation mainstream product in the power electronics field, finding widespread application in household appliance frequency conversion control, industrial control, locomotive transmission, power electronics, and renewable energy grid access.

[0004] With the rapid development of power electronics technology, the demand for high-power semiconductor devices is becoming increasingly significant. However, due to material limitations, the performance of traditional silicon devices has reached its theoretical limits. Silicon carbide, a wide-bandgap semiconductor material that has rapidly developed over the past decade, offers advantages such as a wide bandgap, high thermal conductivity, high carrier saturation mobility, and high power density, making it suitable for high-power, high-temperature, and radiation-resistant applications. The processing of silicon carbide crystals and epitaxial materials has made significant progress in recent years. In the field of power electronics, silicon carbide IGBTs are widely used in high-voltage applications due to their conductivity modulation effect and low on-resistance.

[0005] Silicon carbide IGBTs (SiC IGBTs) boast low on-state voltage drop, fast switching speeds, and high-temperature resistance, offering significant advantages in high-voltage frequency conversion, new energy vehicles, and rail transit. Because SiC is the only wide-bandgap semiconductor material that can be directly thermally oxidized to form SiO2, this advantage simplifies the manufacturing process for SiC IGBTs, attracting significant attention.

[0006] To improve the performance of SiC IGBT devices, a common approach is to shorten the channel length and reduce the area of ​​individual cells in SiC IGBT devices, thereby increasing the number of cells per unit area and improving current density. Currently, common SiC IGBT devices all use either planar gate or trench gate structures. However, because planar gates occupy the cell area, there are limitations to reducing the area of ​​individual cells. Furthermore, trench gates use epitaxial materials with higher resistivity, resulting in a significant increase in on-state voltage drop as voltage increases.

[0007] Based on the above reasons, the structural design of a SiC-based IGBT semiconductor device that can surpass the performance of existing silicon carbide IGBTs and have a higher current density is a technical problem that needs to be solved. Utility Model Content

[0008] In response to the problems mentioned in the background technology, the purpose of the present invention is to provide a SiC-based split-gate trench IGBT semiconductor device structure, which can complete the manufacture of SiC-based IGBT semiconductor devices with higher current density without increasing the difficulty and manufacturing cost of existing processes.

[0009] The above technical objectives of the present invention are achieved through the following technical solutions: A SiC-based split-gate trench IGBT semiconductor device structure, comprising:

[0010] The first conductive substrate;

[0011] A second conductive type buffer layer disposed on the first conductive type substrate;

[0012] a second conductive type drift layer disposed above the second conductive type buffer layer;

[0013] A first conductivity type doped region disposed on the upper surface of the second conductivity type drift layer;

[0014] A second conductivity type doped region disposed on a local upper surface of the first conductivity type doped region;

[0015] a trench provided on the upper surface of the second conductivity type drift layer and penetrating the first conductivity type doped region and the second conductivity type doped region, the trench extending into the interior of the second conductivity type drift layer, wherein the depth of the trench is greater than the thickness of the first conductivity type doped region;

[0016] A first oxide layer is provided on an inner wall of the trench and contacts the first conductivity type doped region. A second oxide layer is further provided inside the trench. The first oxide layer and the second oxide layer jointly surround the first gate. The second oxide layer is located above and adjacent to the first gate. The upper surface of the first gate is lower than the second conductivity type doped region, and the lower surface of the first gate is lower than the lower surface of the first conductivity type doped region.

[0017] A second gate is further provided inside the trench, and the second gate is located above and adjacent to the second oxide layer; two sides of the second gate are adjacent to the first oxide layer;

[0018] A third oxide layer is provided on the upper portion of the trench; the third oxide layer is in contact with both the first oxide layer and the second gate;

[0019] A source metal covering the first conductivity type doping region and the second conductivity type doping region is provided on the third oxide layer;

[0020] A drain metal is provided at the bottom of the first conductive type substrate.

[0021] Preferably, the second conductivity type doping region is surrounded on three sides by the first conductivity type doping region, and the upper surface of the first conductivity type doping region is flush with the upper surface of the second conductivity type doping region.

[0022] Preferably, the materials of the first conductivity type substrate, the second conductivity type buffer layer, the second conductivity type drift layer, the first conductivity type doping region and the second conductivity type doping region are all silicon carbide.

[0023] Preferably, the conductivity types of the first conductivity type and the second conductivity type materials are P type or N type, and the doping types of the first conductivity type and the second conductivity type are opposite.

[0024] In summary, the present invention has the following beneficial effects: The groove structure of the second gate of the epitaxial layer of the SiC-based split-gate trench IGBT semiconductor device structure of the present invention increases the surface area of ​​oxidation and improves the output of free carbon elements, thereby more effectively filling the Z1 / 2 defect, improving the conductive properties of the material, and improving the conduction performance of the silicon carbide IGBT. In addition, by utilizing the two-dimensional charge coupling effect, the concentration of the second conductive drift layer in the first gate region is further increased compared to traditional silicon carbide IGBT devices, and the device structure has a lower on-resistance characteristic. Finally, the first gate connected to the emitter separates the second gate and the collector, thereby greatly reducing the capacitance between the gate and the collector, making the switching speed faster and the on-resistance lower, thereby further improving the power density and power efficiency of the device.

[0025] Another object of the present invention is to propose a method for manufacturing a SiC-based split-gate trench IGBT semiconductor device structure, which utilizes the known existence of free carbon elements at the interface of silicon carbide and its oxide, and the property that free carbon elements can diffuse into silicon carbide materials at high temperatures, to solve the problem of poor conductivity of silicon carbide IGBTs in the prior art, and improve the yield of free carbon atoms and the conduction performance of silicon carbide IGBTs. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 A structural schematic diagram of the preparation process of step S2.

[0027] Figure 2 This is a structural diagram after step S2 is completed.

[0028] Figure 3 This is a structural diagram after step S3 is completed.

[0029] Figure 4 This is a structural diagram after step S4 is completed.

[0030] Figure 5 This is a structural diagram after step S5 is completed.

[0031] Figure 6 This is a structural diagram after step S6 is completed.

[0032] Figure 7 This is a structural diagram after step S7 is completed.

[0033] Figure 8 This is a structural diagram after step S8 is completed.

[0034] Figure 9 This is a structural diagram after step S10 is completed.

[0035] Figure 10 A structural schematic diagram of the preparation process of step A2.

[0036] Figure 11 This is a structural diagram after step A3 is completed.

[0037] Figure 12 This is a structural diagram after step A4 is completed.

[0038] Figure 13 This is a structural diagram after step A5 is completed.

[0039] Figure 14 This is a structural diagram after step A7 is completed.

[0040] Figure 15 This is a structural diagram after step A8 is completed.

[0041] Figure 16 This is a structural diagram after step A9 is completed.

[0042] Figure 17 This is a structural diagram after step A11 is completed.

[0043] Figure numerals: 1. First conductive type substrate; 2. Second conductive type buffer layer; 3. Second conductive type drift layer; 4. First conductive type doped region; 5. Second conductive type doped region; 6. Trench; 7. First oxide layer; 8. First gate; 9. Second oxide layer; 10. Second gate; 11. Third oxide layer; 12. Source metal; 13. Drain metal. DETAILED DESCRIPTION

[0044] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0045] To improve the performance of SiC-based IGBT devices, a common approach is to shorten the channel length and reduce the area of ​​individual cells in SiC-based IGBT devices, thereby increasing the number of cells per unit area and improving current density. Currently, common SiC-based IGBT devices use either planar gate or trench gate structures. However, because planar gates occupy the cell area, reducing the area of ​​individual cells is limited. Furthermore, trench gates use epitaxial materials with higher resistivity, resulting in a significant increase in on-state voltage drop as voltage increases.

[0046] Based on the above reasons, a SiC-based IGBT semiconductor device structure that can break through the performance of existing SiC-based IGBTs and have a higher current density is very necessary; at the same time, a manufacturing method of SiC-based IGBT semiconductor devices is also needed to complete the manufacturing of SiC-based IGBT semiconductor devices with higher current density without increasing the difficulty and manufacturing cost of existing processes.

[0047] The purpose of the utility model is to propose a SiC-based split-gate trench IGBT semiconductor device structure. The recessed structure of the epitaxial layer's second gate increases the oxidized surface area and improves the yield of free carbon, thereby more effectively filling the Z1 / 2 defect, improving the material's conductivity and enhancing the on-state performance of the silicon carbide IGBT. Furthermore, by utilizing the two-dimensional charge coupling effect, the concentration of the second-type conductive drift layer in the first gate region is further increased compared to conventional silicon carbide IGBT devices, resulting in a device structure with lower on-resistance. Finally, the first gate connected to the emitter separates the second gate from the collector, significantly reducing the capacitance between the gate and collector, resulting in faster switching speeds and lower on-state resistance. This further improves both the device's power density and power efficiency.

[0048] The specific SiC-based split-gate trench IGBT semiconductor device structure includes:

[0049] A first conductive substrate 1;

[0050] A second conductive type buffer layer 2 provided on the first conductive type substrate 1;

[0051] A second conductive type drift layer 3 is provided above the second conductive type buffer layer 2;

[0052] A first conductivity type doped region 4 provided on the upper surface of the second conductivity type drift layer 3;

[0053] A second conductivity type doping region 5 provided on a partial upper surface of the first conductivity type doping region 4;

[0054] a trench 6 provided on the upper surface of the second conductivity type drift layer 3 and penetrating the first conductivity type doped region 4 and the second conductivity type doped region 5, the trench 6 extending into the interior of the second conductivity type drift layer 3, wherein the depth of the trench 6 is greater than the thickness of the first conductivity type doped region 4;

[0055] A first oxide layer 7 is provided on the inner wall of the trench 6 and the first oxide layer 7 is in contact with the first conductivity type doped region 4. A second oxide layer 9 is further provided inside the trench 6. The first oxide layer 7 and the second oxide layer 9 together surround a first gate 8. The second oxide layer 9 is located above and adjacent to the first gate 8. The upper surface of the first gate 8 is lower than the second conductivity type doped region 5, and the lower surface of the first gate 8 is lower than the lower surface of the first conductivity type doped region 4.

[0056] A second gate 10 is further provided inside the trench 6 , and the second gate 10 is located above and adjacent to the second oxide layer 9 ; both sides of the second gate 10 are adjacent to the first oxide layer 7 ;

[0057] A third oxide layer 11 is provided on the upper portion of the trench 6; the third oxide layer 11 is in contact with both the first oxide layer 7 and the second gate 10;

[0058] A source metal 12 is provided on the third oxide layer 11, covering the first conductivity type doping region 4 and the second conductivity type doping region 5;

[0059] A drain metal 13 is provided at the bottom of the first conductive type substrate 1 .

[0060] There may also be another structural form, that is, the second conductivity type doping region 5 is surrounded by the first conductivity type doping region 4 on three sides, and the upper surface of the first conductivity type doping region 4 is flush with the upper surface of the second conductivity type doping region 5 .

[0061] The materials of the first conductive type substrate 1 , the second conductive type buffer layer 2 , the second conductive type drift layer 3 , the first conductive type doping region 4 and the second conductive type doping region 5 are all silicon carbide.

[0062] The conductivity types of the first conductivity type and the second conductivity type materials are P type or N type, and the doping types of the first conductivity type and the second conductivity type are opposite.

[0063] Another object of the present invention is to propose a method for manufacturing a SiC-based split-gate trench IGBT semiconductor device, which utilizes the known existence of free carbon elements at the interface of silicon carbide and its oxide, and the property that free carbon elements can diffuse into the silicon carbide material at high temperatures, to solve the problem of poor conductivity of silicon carbide IGBT in the prior art, and improve the yield of free carbon atoms and the conduction performance of silicon carbide IGBT.

[0064] The specific steps are as follows:

[0065] Step S1: epitaxially growing a second conductivity type buffer layer 2 on a first conductivity type substrate 1, and then epitaxially growing a second conductivity type drift layer 3;

[0066] Step S2: forming a first conductivity type doped region 4 on the upper surface of the second conductivity type drift layer 3 by epitaxial growth or ion implantation, and then forming a second conductivity type doped region 5 in the first conductivity type doped region 4 by ion implantation again;

[0067] Step S3: etching to form a trench 6 on the upper surface of the second conductivity type drift layer 3, wherein the trench 6 passes through the first conductivity type doped region 4 and the second conductivity type doped region 5;

[0068] Step S4: high-temperature oxidation of the trench 6 sidewalls, the upper surface of the first conductivity type doped region 4 and the upper surface of the second conductivity type doped region 5 to form a first oxide layer, and annealing at a high temperature of 1000-1600° C.;

[0069] Step S5: depositing a first gate material in the trench 6 and patterning it;

[0070] Step S6: oxidizing the first gate 8 at a high temperature to form a second oxide layer 9, and annealing at a high temperature of 1000-1600° C.;

[0071] Step S7: continue depositing the second gate material in the trench 6 and patterning it;

[0072] Step S8: forming a third oxide layer 11 on the second gate 10 and patterning it to expose the upper surface of the first conductivity type doped region 4 and a partial upper surface of the second conductivity type doped region 5;

[0073] Step S9: forming a source metal 12 on the third oxide layer 11 to cover the upper surface of the first conductivity type doping region 4 and the upper surface of the second conductivity type doping region 5;

[0074] Step S10: forming a drain metal 13 at the bottom of the first conductive type substrate 1 .

[0075] Furthermore, in step S3 , the trench 6 is etched by dry etching or laser etching.

[0076] Furthermore, the oxidation treatment in steps S4 and S6 adopts dry oxygen oxidation or wet oxygen oxidation, and the annealing time is 0.1-10 hours.

[0077] Using the preparation method of the present invention, the groove structure of the second gate electrode 10 of the epitaxial layer increases the surface area of ​​oxidation and improves the output of free carbon elements, thereby more effectively filling the Z1 / 2 defect, improving the conductive properties of the material, and improving the conduction performance of the SiC-based IGBT. In addition, by utilizing the two-dimensional charge coupling effect, the concentration of the second conductive drift layer in the first gate region is further increased compared to traditional SiC-based IGBT devices, and the device structure has lower on-resistance characteristics. The first gate electrode 8 connected to the emitter separates the second gate electrode 10 from the collector, thereby greatly reducing the capacitance between the gate and the collector, faster switching speed, and lower on-resistance, thereby further improving both the power density and power efficiency of the device.

[0078] The trench 6 in step S3 is etched by dry etching or laser etching.

[0079] The oxidation treatment in step S4 adopts dry oxygen oxidation or wet oxygen oxidation, and a silicon dioxide layer of 20-1000 nm is formed on the surface after oxidation. The annealing time is 0.1-10 hours.

[0080] The gate material in step S5 can be polysilicon, metal, or an alloy of these two materials or a stacked structure.

[0081] The source metal 12 in step S9 and the drain metal 13 in steps S10 and A10 can be Ti, Ni, Al, Pb, Pt, Ta, Co or alloys TiC, SiNi, Si2Ni, SiNi2, or a stacked structure thereof.

[0082] The preparation method of steps S2 to S8 can also adopt the following steps:

[0083] Step A2: forming a first conductivity type doped region 4 on the upper surface of the second conductivity type drift layer 3 by epitaxial growth or ion implantation, and then forming a second conductivity type doped region 5 on the upper surface of the first conductivity type doped region 4 by ion implantation again;

[0084] Step A3: forming a trench 6 on the upper surface of the second conductivity type drift layer 3 by etching, and the trench 6 penetrates the first conductivity type doped region 4 and the second conductivity type doped region 5;

[0085] Step A4: oxidizing the sidewalls of the trench 6 and the upper surface of the second conductivity type doped region 5 at high temperature to form a first oxide layer, and annealing at a high temperature of 1000-1600° C.;

[0086] Step A5: depositing a first gate material in the trench 6 and patterning it;

[0087] Step A6: oxidizing the first gate 8 and part of the trench sidewall at high temperature to form a second oxide layer, and annealing at a high temperature of 1000-1600° C.;

[0088] Step A7: Continue depositing and patterning the second gate material in the trench;

[0089] Step A8: forming a third oxide layer 11 on the second gate 10 and patterning it to expose the upper surface of the first conductivity type doped region 4 and a partial upper surface of the second conductivity type doped region 5;

[0090] Step A9: forming a source metal 12 on the third oxide layer 11 to cover the upper surface of the first conductivity type doped region 4 and the upper surface of the second conductivity type doped region 5;

[0091] Step A10: forming a drain metal 13 at the bottom of the first conductive type substrate 1 .

[0092] Although the embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and variations may be made to these embodiments without departing from the principles and spirit of the present invention, and the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A SiC-based split-gate trench IGBT semiconductor device structure, characterized in that: include: A first conductive substrate (1); A second conductive type buffer layer (2) disposed on the upper portion of the first conductive type substrate (1); A second conductive type drift layer (3) disposed above the second conductive type buffer layer (2); A first conductivity type doped region (4) disposed on the upper surface of the second conductivity type drift layer (3); A second conductive type doping region (5) disposed on a local upper surface of the first conductive type doping region (4); A groove (6) is provided on the upper surface of the second conductive type drift layer (3) and penetrates the first conductive type doping region (4) and the second conductive type doping region (5), the groove (6) extending to the interior of the second conductive type drift layer (3), wherein the depth of the groove (6) is greater than the thickness of the first conductive type doping region (4); A first oxide layer (7) is provided on the inner wall of the groove (6), and the first oxide layer (7) is in contact with the first conductive type doping region (4). A second oxide layer (9) is also provided inside the groove (6). The first oxide layer (7) and the second oxide layer (9) jointly surround the first gate (8), and the second oxide layer (9) is located above and adjacent to the first gate (8). The upper surface of the first gate (8) is lower than the second conductive type doping region (5), and the lower surface of the first gate (8) is lower than the lower surface of the first conductive type doping region (4). A second gate (10) is also provided inside the groove (6), and the second gate (10) is located above and adjacent to the second oxide layer (9); two sides of the second gate (10) are adjacent to the first oxide layer (7); A third oxide layer (11) is provided on the upper portion of the trench (6); the third oxide layer (11) is in contact with both the first oxide layer (7) and the second gate (10); A source metal (12) is provided on the upper part of the third oxide layer (11) and covers the first conductive type doping region (4) and the second conductive type doping region (5); A drain metal (13) is provided at the bottom of the first conductive type substrate (1).

2. The SiC-based split-gate trench IGBT semiconductor device structure according to claim 1, characterized in that: The second conductive type doping region (5) is surrounded on three sides by the first conductive type doping region (4), and the upper surface of the first conductive type doping region (4) is flush with the upper surface of the second conductive type doping region (5).

3. The SiC-based split-gate trench IGBT semiconductor device structure according to any one of claims 1 to 2, characterized in that: The materials of the first conductive type substrate (1), the second conductive type buffer layer (2), the second conductive type drift layer (3), the first conductive type doping region (4) and the second conductive type doping region (5) are all silicon carbide.

4. The SiC-based split-gate trench IGBT semiconductor device structure according to any one of claims 1 to 2, characterized in that: The conductivity types of the first conductivity type and the second conductivity type materials are P type or N type, and the doping types of the first conductivity type and the second conductivity type are opposite.

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