Thin film transistor and array substrate

Abstract

The embodiment of the utility model discloses a thin film transistor and an array substrate. The thin film transistor comprises a substrate, and a gate layer, an insulating layer, a semiconductor layer, a source electrode and a drain electrode which are arranged on one side of the substrate, the outer peripheral side of the semiconductor layer includes a first side surface parallel to the length direction of the channel portion. The gate layer at least comprises a first ring gate part, and the orthographic projection of the first ring gate part on the first side surface covers the orthographic projection of the channel part on the first side surface; the semiconductor layer further comprises an extension part, and the extension part is located on the side, away from the first ring gate part, of the channel part and connected with the channel part. According to the thin film transistor, the extension part is arranged on one side, far away from the first ring gate part, of the channel part, and when the thin film transistor is in a cut-off state, repulsive electrons move to the extension part from the channel part to be stored; when the thin film transistor is in a conducting state, the stored electrons move from the extension part to the channel part, so that the stability of the thin film transistor is improved.

Description

Technical Field

[0001] The utility model relates to the field of display technology, in particular to a thin film transistor and an array substrate. Background Art

[0002] Amorphous silicon (a-Si) thin film transistor (TFT) devices have the advantages of mature technology and low cost, and are widely used in panels. With the development of the times, products such as high brightness, narrow borders, and high penetration have put forward higher requirements for thin film transistor devices. However, the current amorphous silicon thin film transistor devices are basically single-gate structure devices with poor device stability. Utility Model Content

[0003] The embodiments of the utility model provide a thin film transistor and an array substrate, which can solve the technical problem of poor device stability of the existing amorphous silicon thin film transistor.

[0004] The present invention provides a thin film transistor, comprising a substrate, and a gate layer, an insulating layer, a semiconductor layer, a source electrode and a drain electrode arranged on one side of the substrate, wherein the insulating layer is located between the gate layer and the semiconductor layer, and the source electrode and the drain electrode are located on the same side or different sides of the semiconductor layer;

[0005] The semiconductor layer includes a channel portion corresponding to a gap region between the source electrode and the drain electrode, and an outer peripheral side of the semiconductor layer includes a first side surface parallel to a length direction of the channel portion;

[0006] The gate layer at least includes a ring gate layer disposed on the outer peripheral side of the semiconductor layer, the ring gate layer at least includes a first ring gate portion located on a side of the first side away from the channel portion, and an orthographic projection of the first ring gate portion on the first side covers an orthographic projection of the channel portion on the first side;

[0007] Wherein, the semiconductor layer further includes an extension portion, and the extension portion is located on a side of the channel portion away from the first ring gate portion and connected to the channel portion.

[0008] According to the thin film transistor provided by the embodiment of the utility model, the orthographic projection of the extension portion on the first side surface at least covers the orthographic projection of the channel portion on the first side surface.

[0009] According to the thin film transistor provided by the embodiment of the present invention, the size of the extension portion along the width direction of the channel portion is greater than or equal to 1 micron and less than or equal to 3 microns; wherein the width direction of the channel portion is perpendicular to the length direction of the channel portion.

[0010] According to the thin film transistor provided by the embodiment of the utility model, the orthographic projection of the first ring gate portion on the first side surface at least partially overlaps with the orthographic projection of the source electrode on the first side surface, and the orthographic projection of the first ring gate portion on the first side surface at least partially overlaps with the orthographic projection of the drain electrode on the first side surface.

[0011] According to the thin film transistor provided by the embodiment of the utility model, the source electrode and the drain electrode are both located on a side of the semiconductor layer away from the substrate and are arranged in the same layer;

[0012] The gate layer further comprises a bottom gate layer and a top gate layer, wherein the bottom gate layer is located on a side of the semiconductor layer close to the substrate, and the top gate layer is located on a side of the source and the drain away from the substrate;

[0013] The thin film transistor further includes a via hole penetrating the insulating layer, the first ring gate portion is located in the via hole, and the top gate layer is connected to the bottom gate layer through the first ring gate portion.

[0014] According to the thin film transistor provided by the embodiment of the utility model, the orthographic projection of the bottom gate layer on the substrate covers the orthographic projections of the channel portion and the extension portion on the substrate, and the orthographic projection of the top gate layer on the substrate covers the orthographic projection of the channel portion on the substrate.

[0015] According to the thin film transistor provided by the embodiment of the utility model, the source is located on the side of the semiconductor layer close to the substrate, and the drain is located on the side of the semiconductor layer away from the substrate; wherein the extension portion is located on the side of the source away from the first ring gate portion and covers the surface of the substrate on one side close to the semiconductor layer.

[0016] According to the thin film transistor provided by the embodiment of the utility model, the semiconductor layer further comprises a second side surface and a third side surface which are arranged opposite to and respectively connected to the first side surface;

[0017] The ring gate layer also includes a second ring gate portion and a third ring gate portion which are arranged opposite to each other and connected to the first ring gate portion. The second ring gate portion is located on a side of the second side away from the third side, and the third ring gate portion is located on a side of the third side away from the second side.

[0018] According to the thin film transistor provided by the embodiment of the utility model, the orthographic projection of the second ring gate portion on the second side surface does not overlap with the orthographic projection of the extension portion on the third side surface, and the orthographic projection of the third ring gate portion on the third side surface does not overlap with the orthographic projection of the extension portion on the third side surface.

[0019] An embodiment of the utility model provides an array substrate, and the array substrate includes the above-mentioned thin film transistor.

[0020] Beneficial effects: In the thin film transistor and array substrate provided by the embodiment of the utility model, the thin film transistor includes a substrate, a gate layer, an insulating layer, a semiconductor layer, a source and a drain, the outer peripheral side of the semiconductor layer includes a first side parallel to the length direction of the channel part; the gate layer at least includes a ring gate layer arranged on the outer peripheral side of the semiconductor layer, the ring gate layer at least includes a first ring gate part located on the side of the first side away from the channel part, and the positive projection of the first ring gate part on the first side covers the positive projection of the channel part on the first side; the semiconductor layer also includes an extension part, the extension part is located on the side of the channel part away from the first ring gate part and is connected to the channel part. The utility model arranges the extension part on the side of the channel part away from the first ring gate part, when the thin film transistor is in the off state, the first ring gate part has a certain repulsive force on the electrons, and the electrons are repelled from the channel part to the position of the extension part for storage; when the thin film transistor is in the on state, the first ring gate part has a certain attraction for the electrons, and the stored electrons move from the extension part to the channel part, which is conducive to improving the stability of the thin film transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0022] Figure 1 A schematic diagram of a first planar structure of a thin film transistor provided by an embodiment of the utility model;

[0023] Figure 2 for Figure 1 A schematic cross-sectional structure diagram of a thin film transistor along a section line AA;

[0024] Figure 3 for Figure 1 A schematic cross-sectional structure diagram of the thin film transistor along the section line BB;

[0025] Figure 4 for Figure 1 A schematic diagram of a planar structure of a semiconductor layer of a thin film transistor;

[0026] Figure 5 A schematic diagram of a second planar structure of a thin film transistor provided by an embodiment of the utility model;

[0027] Figure 6 for Figure 5 A schematic cross-sectional structure diagram of the thin film transistor along the section line CC;

[0028] Figure 7 for Figure 5 Schematic diagram of the planar structure of the semiconductor layer of the thin film transistor.

[0029] Description of reference numerals:

[0030] 100, thin film transistor; 10, substrate; 11, gate layer; 111, ring gate layer; 1111, first ring gate portion; 1112, second ring gate portion; 1113, third ring gate portion; 112, bottom gate layer; 113, top gate layer; 12, insulating layer; 121, gate insulating layer; 122, passivation layer; 13, semiconductor layer; 131, channel portion; 132, extension portion; 133, first contact portion; 134, second contact portion; 13a, first side surface; 13b, second side surface; 13c, third side surface; 14, source electrode; 15, drain electrode; 16, pixel electrode. DETAILED DESCRIPTION

[0031] The following will be combined with the drawings in the embodiments of the utility model to clearly and completely describe the technical solutions in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments in the utility model, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the utility model.

[0032] In the description of the present invention, it should be understood that the terms "length", "width", "thickness", "upper", "lower" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific position, be constructed and operated in a specific position, and therefore cannot be understood as a limitation on the present invention. In the description of the present invention, "multiple" means two or more, unless otherwise clearly and specifically defined.

[0033] In the present invention, unless otherwise clearly stipulated and limited, the first feature being "on" or "below" the second feature may include the first and second features being in direct contact, or may include the first and second features not being in direct contact but being in contact through another feature between them.

[0034] The embodiment of the utility model provides a thin film transistor and an array substrate. The thin film transistor includes a substrate, and a gate layer, an insulating layer, a semiconductor layer, a source electrode and a drain electrode arranged on one side of the substrate, the insulating layer is located between the gate layer and the semiconductor layer, and the source electrode and the drain electrode are located on the same side or different sides of the semiconductor layer; the semiconductor layer includes a channel portion corresponding to the gap area between the source electrode and the drain electrode, and the outer peripheral side of the semiconductor layer includes a first side surface parallel to the length direction of the channel portion; the gate layer at least includes a ring gate layer arranged on the outer peripheral side of the semiconductor layer, the ring gate layer at least includes a first ring gate portion located on a side of the first side away from the channel portion, and the orthographic projection of the first ring gate portion on the first side surface covers the orthographic projection of the channel portion on the first side surface; wherein the semiconductor layer also includes an extension portion, and the extension portion is located on a side of the channel portion away from the first ring gate portion and is connected to the channel portion. By setting the extension part, when the thin film transistor is in the off state, the first ring gate part has a certain repulsive force on electrons, repelling the electrons from the channel part to move to the extension part for storage; when the thin film transistor is in the on state, the first ring gate part has a certain attraction force on electrons, and the stored electrons move from the extension part to the channel part, which is beneficial to improving the stability of the thin film transistor.

[0035] The thin film transistor and the array substrate provided by the embodiments of the present utility model will be described in detail below. It should be noted that the description order of the following embodiments is not intended to limit the preferred order of the embodiments.

[0036] See also Figure 1-Figure 7 The embodiment of the utility model provides a thin film transistor 100, which includes a substrate 10 and a gate layer 11, an insulating layer 12, a semiconductor layer 13, a source electrode 14 and a drain electrode 15 arranged on one side of the substrate 10. The insulating layer 12 is located between the gate layer 11 and the semiconductor layer 13, and the source electrode 14 and the drain electrode 15 are located on the same side or different sides of the semiconductor layer 13.

[0037] The semiconductor layer 13 includes a channel portion 131 corresponding to the gap area between the source 14 and the drain 15, and the outer peripheral side of the semiconductor layer 13 includes a first side surface 13a parallel to the length direction of the channel portion 131. Specifically, the length direction of the channel portion 131 actually refers to the direction in which the source 14 points to the drain 15. Depending on the channel type of the thin film transistor 100, the relative positional relationship between the length direction of the channel portion 131 and the plane where the substrate 10 is located is also different. For example, when the thin film transistor 100 adopts a horizontal channel, the length direction of the channel portion 131 is parallel to the plane where the substrate 10 is located. Conversely, when the thin film transistor 100 adopts a vertical channel, the length direction of the channel portion 131 is perpendicular to the plane where the substrate 10 is located.

[0038] In an embodiment of the utility model, the thin film transistor 100 is a ring-gate thin film transistor 100. As the name implies, the ring-gate thin film transistor 100 refers to a thin film transistor 100 in which at least a portion of the gate layer 11 is arranged around the semiconductor layer 13 and overlaps with the channel portion 131 to increase the coverage area of ​​the gate layer 11 on the channel portion 131, which is beneficial to increasing the control area of ​​the gate layer 11 on the semiconductor layer 13 and improving the stability of the thin film transistor 100.

[0039] Specifically, the gate layer 11 at least includes a ring gate layer 111 arranged on the peripheral side of the semiconductor layer 13, and the ring gate layer 111 at least includes a first ring gate portion 1111 located on the side of the first side 13a away from the channel portion 131, and the orthographic projection of the first ring gate portion 1111 on the first side 13a covers the orthographic projection of the channel portion 131 on the first side 13a, that is, the first ring gate portion 1111 is arranged corresponding to the channel portion 131, and the first ring gate portion 1111 can shield the influence of external light and other factors on the channel portion 131, and can also enhance the control of the gate layer 11 over the semiconductor layer 13.

[0040] In the embodiment of the utility model, the semiconductor layer 13 further includes an extension portion 132, and the extension portion 132 is located on a side of the channel portion 131 away from the first ring-gate portion 1111 and connected to the channel portion 131. Specifically, the extension portion 132 is formed by extending the semiconductor layer 13 in a direction away from the first ring-gate portion 1111, and the material of the extension portion 132 is the same as that of the semiconductor layer 13.

[0041] It can be understood that, in the present invention, by arranging the extension part 132 on the side of the channel part 131 away from the first ring gate part 1111, when the thin film transistor 100 is in the off state, the first ring gate part 1111 has a certain repulsive force on electrons, repelling electrons from the channel part 131 to the position of the extension part 132 for storage; when the thin film transistor 100 is in the on state, the first ring gate part 1111 has a certain attraction for electrons, and the stored electrons move from the extension part 132 to the channel part 131, which is conducive to improving the stability of the thin film transistor 100. In other words, the extension part 132 plays the role of providing a storage space for repelling electrons.

[0042] Specifically, the substrate 10 may be a flexible substrate or a rigid substrate, and the flexible substrate may be a laminated structure of a double-layer polyimide (PI) substrate or a single-layer PI substrate. In this embodiment, a double-layer PI substrate is preferred, wherein an inorganic layer is provided between the double-layer PI substrates. Therefore, the laminated structure of the double-layer PI substrate can effectively block water and oxygen while improving the flexible bending ability of the display product, which is beneficial to improving the life of the display product.

[0043] Specifically, the material of the gate electrode may include a low-resistance material such as Al, Ti, Mo, Cu, Ni, or an alloy thereof, or a multilayer or single-layer structure of a material with high corrosion resistance, which is not specifically limited in the present invention. The material of the insulating layer 12 may include a combination of one or more of silicon oxide, silicon nitride, and silicon oxynitride. The material of the source electrode 14 and the drain electrode 15 may be a multilayer or single-layer structure formed of a low-resistance material such as Al, Ti, Mo, Cu, Ni, or an alloy thereof, or a material with high corrosion resistance. Exemplarily, the material of the source electrode 14 and the drain electrode 15 may be a triple layer of Ti / Cu / Ti, Ti / Ag / Ti, Ti / Al / Ti or Mo / Al / Mo and others.

[0044] Specifically, the material of the semiconductor layer 13 includes amorphous silicon.

[0045] Specifically, the semiconductor layer 13 further includes a first contact portion 133 and a second contact portion 134 located at opposite sides of the channel portion 131, the source 14 is connected to the first contact portion 133, and the drain 15 is connected to the second contact portion 134. The first contact portion 133 and the second contact portion 134 are conductor regions of the semiconductor layer 13.

[0046] In the embodiment of the present invention, the orthographic projection of the extension portion 132 on the substrate 10 does not overlap with the orthographic projections of the source electrode 14 and the drain electrode 15 on the substrate 10 .

[0047] In the embodiment of the utility model, the orthographic projection of the extension portion 132 on the first side surface 13a at least covers the orthographic projection of the channel portion 131 on the first side surface 13a, so that when the thin film transistor 100 is in the cut-off state, the extension portion 132 has enough space to store the electrons in the channel that are repelled by the first ring gate portion 1111.

[0048] Furthermore, the orthographic projection of the extension portion 132 on the first side surface 13a overlaps with the orthographic projections of the source 14 and the drain 15 on the first side surface 13a. Still further, the orthographic projection of the extension portion 132 on the first side surface 13a covers the orthographic projections of the source 14 and the drain 15 on the first side surface 13a, so as to increase the area of ​​the extension portion 132, thereby increasing the storage space for repelling electrons.

[0049] In the embodiment of the utility model, along the width direction of the channel portion 131, the size of the extension portion 132 is greater than or equal to 1 micron and less than or equal to 3 microns; wherein the width direction of the channel portion 131 is perpendicular to the length direction of the channel portion 131. Specifically, along the width direction of the channel portion 131, the size of the extension portion 132 is greater than or equal to 1.5 microns and less than or equal to 2 microns. Optionally, along the width direction of the channel portion 131, the size of the extension portion 132 can be one of 1.5 microns, 1.6 microns, 1.7 microns, 1.8 microns, 1.9 microns and 2 microns.

[0050] In the embodiment of the utility model, the orthographic projection of the first ring gate portion 1111 on the first side surface 13a at least partially overlaps with the orthographic projection of the source 14 on the first side surface 13a, and the orthographic projection of the first ring gate portion 1111 on the first side surface 13a at least partially overlaps with the orthographic projection of the drain 15 on the first side surface 13a. Since the channel portion 131 is located between the source 14 and the drain 15, it can be ensured that the first ring gate portion 1111 can completely cover the first side surface 13a, which is beneficial to enhance the control of the gate layer 11 over the semiconductor layer 13.

[0051] In the embodiment of the present invention, the structure of the channel portion 131 of the thin film transistor 100 can be a horizontal channel or a vertical channel. The following will introduce these two types of thin film transistor 100 structures in detail one by one.

[0052] In one embodiment, see Figure 1-Figure 4, the channel portion 131 of the thin film transistor 100 is a horizontal structure. Specifically, the source 14 and the drain 15 are both located on the same side of the semiconductor layer 13, that is, the source 14 and the drain 15 are both located on the side of the semiconductor layer 13 away from the substrate 10 and are arranged in the same layer. The gate layer 11 also includes a bottom gate layer 112 and a top gate layer 113, the bottom gate layer 112 is located on the side of the semiconductor layer 13 close to the substrate 10, and the top gate layer 113 is located on the side of the source 14 and the drain 15 away from the substrate 10. Among them, the thin film transistor 100 also includes a via hole penetrating the insulating layer 12, the first ring gate portion 1111 is located in the via hole, and the top gate layer 113 is connected to the bottom gate layer 112 through the first ring gate portion 1111.

[0053] It can be understood that, in this embodiment, the bottom gate layer 112 , the top gate layer 113 and the first ring gate portion 1111 together constitute the gate layer 11 .

[0054] Specifically, the orthographic projection of the bottom gate layer 112 on the substrate 10 covers the orthographic projection of the channel portion 131 and the extension portion 132 on the substrate 10 to shield the lower side of the channel portion 131 and the extension portion 132; the orthographic projection of the top gate layer 113 on the substrate 10 covers the orthographic projection of the channel portion 131 on the substrate 10 to shield the upper side of the channel portion 131.

[0055] Specifically, in this embodiment, the insulating layer 12 includes a gate insulating layer 121 and a passivation layer 122, the gate insulating layer 121 covers the side of the bottom gate layer 112 away from the substrate 10, the semiconductor layer 13 is located on the side of the gate insulating layer 121 away from the substrate 10, the source 14 and the drain 15 are located on the side of the semiconductor layer 13 away from the substrate 10, the passivation layer 122 covers the side of the source 14 and the drain 15 away from the substrate 10, and the top gate layer 113 is located on the side of the passivation layer 122 away from the substrate 10.

[0056] Optionally, the material of the gate insulating layer 121 may include one or more combinations of silicon oxide, silicon nitride and silicon oxynitride. The material of the passivation layer 122 may be the same as that of the gate insulating layer 121, or may include one or more combinations of silicon oxide, silicon nitride and silicon oxynitride.

[0057] In one embodiment, see Figure 5 and Figure 7, the channel portion 131 of the thin film transistor 100 is a vertical structure. Specifically, the source electrode 14 and the drain electrode 15 are located on different sides of the semiconductor layer 13 away from the substrate 10. In this embodiment, the source electrode 14 and the drain electrode 15 are located on opposite sides of the semiconductor layer 13 away from the substrate 10. Specifically, the source electrode 14 is located on the side of the semiconductor layer 13 close to the substrate 10, and the drain electrode 15 is located on the side of the semiconductor layer 13 away from the substrate 10; wherein the extension portion 132 is located on the side of the source electrode 14 away from the first ring gate portion 1111 and covers the surface of the substrate 10 on one side close to the semiconductor layer 13.

[0058] Specifically, in this embodiment, the insulating layer 12 includes a gate insulating layer 121 and a passivation layer 122, the gate insulating layer 121 covers the side of the raised structure formed by the source 14, the semiconductor layer 13 and the drain 15 away from the substrate 10, the ring gate layer 111 is located on the side of the gate insulating layer 121 away from the substrate 10, and the passivation layer 122 covers the side of the ring gate layer 111 away from the substrate 10.

[0059] In this embodiment, the semiconductor layer 13 further includes a second side surface 13b and a third side surface 13c which are arranged opposite to and respectively connected to the first side surface 13a; the ring-gate layer 111 further includes a second ring-gate portion 1112 and a third ring-gate portion 1113 which are arranged opposite to and connected to the first ring-gate portion 1111, the second ring-gate portion 1112 is located on a side of the second side surface 13b away from the third side surface 13c, and the third ring-gate portion 1113 is located on a side of the third side surface 13c away from the second side surface 13b. That is to say, in this embodiment, the ring-gate layer 111 is a semi-circular structure composed of the first ring-gate portion 1111, the second ring-gate portion 1112 and the third ring-gate portion 1113, the ring-gate layer 111 includes an opening, and the extension portion 132 is arranged at the opening.

[0060] It should be noted that the second ring gate portion 1112 is arranged corresponding to the second side surface 13b, and the third ring gate portion 1113 is arranged corresponding to the third side surface 13c, thereby further increasing the shielding area of ​​the gate layer 11 on the channel portion 131, which is beneficial to further shield the influence of external light and other factors on the channel portion 131, and further enhance the control of the gate layer 11 on the semiconductor layer 13.

[0061] In this embodiment, the orthographic projection of the second ring gate portion 1112 on the second side surface 13b does not overlap with the orthographic projection of the extension portion 132 on the third side surface 13c, and the orthographic projection of the third ring gate portion 1113 on the third side surface 13c does not overlap with the orthographic projection of the extension portion 132 on the third side surface 13c, so as to avoid the second ring gate portion 1112, the third ring gate portion 1113 and the extension portion 132 being too close to each other and affecting the movement and storage of the repelled electrons.

[0062] See also Figure 3 and Figure 6 The thin film transistor 100 further includes a pixel electrode 16, which is disposed on a side of the source electrode 14 and the drain electrode 15 away from the substrate 10 and is electrically connected to the drain electrode 15. Figure 3 In the embodiment, the pixel electrode 16 (not shown in the figure) is electrically connected to the drain electrode 15 through a via hole penetrating the passivation layer 122. Figure 6 In the embodiment, the pixel electrode 16 is electrically connected to the drain electrode 15 through a via hole penetrating the gate insulating layer 121 and the passivation layer 122 .

[0063] The embodiment of the utility model also provides an array substrate 10, the array substrate 10 includes the thin film transistor 100 in the above embodiment, and the array substrate 10 also includes a plurality of metal wirings such as a scan line, a data line, and a power signal line. Among them, the scan line is electrically connected to the gate electrode in the thin film transistor 100, and the data line is electrically connected to the source electrode 14 in the thin film transistor 100, and is respectively used to transmit a scan signal and a data signal to the thin film transistor 100. The power signal line includes a high-level power signal line and a low-level power signal line, which are used to transmit a power signal. Of course, the array substrate 10 also includes other structures, which are not described in detail here because they are prior art.

[0064] Beneficial effects: In the thin film transistor and array substrate provided by the embodiment of the utility model, the thin film transistor includes a substrate, a gate layer, an insulating layer, a semiconductor layer, a source and a drain, the outer peripheral side of the semiconductor layer includes a first side parallel to the length direction of the channel part; the gate layer at least includes a ring gate layer arranged on the outer peripheral side of the semiconductor layer, the ring gate layer at least includes a first ring gate part located on the side of the first side away from the channel part, and the positive projection of the first ring gate part on the first side covers the positive projection of the channel part on the first side; the semiconductor layer also includes an extension part, the extension part is located on the side of the channel part away from the first ring gate part and is connected to the channel part. The utility model arranges the extension part on the side of the channel part away from the first ring gate part, when the thin film transistor is in the off state, the first ring gate part has a certain repulsive force on the electrons, and the electrons are repelled from the channel part to the position of the extension part for storage; when the thin film transistor is in the on state, the first ring gate part has a certain attraction for the electrons, and the stored electrons move from the extension part to the channel part, which is conducive to improving the stability of the thin film transistor.

[0065] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0066] The above is a detailed introduction to a thin film transistor and an array substrate provided in an embodiment of the present invention. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the technical solution and core idea of ​​the present invention. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A thin film transistor, characterized in that: It comprises a substrate, and a gate layer, an insulating layer, a semiconductor layer, a source electrode and a drain electrode arranged on one side of the substrate, wherein the insulating layer is located between the gate layer and the semiconductor layer, and the source electrode and the drain electrode are located on the same side or different sides of the semiconductor layer; The semiconductor layer includes a channel portion corresponding to a gap region between the source electrode and the drain electrode, and an outer peripheral side of the semiconductor layer includes a first side surface parallel to a length direction of the channel portion; The gate layer at least includes a ring gate layer disposed on the outer peripheral side of the semiconductor layer, the ring gate layer at least includes a first ring gate portion located on a side of the first side away from the channel portion, and an orthographic projection of the first ring gate portion on the first side covers an orthographic projection of the channel portion on the first side; Wherein, the semiconductor layer further includes an extension portion, and the extension portion is located on a side of the channel portion away from the first ring gate portion and connected to the channel portion.

2. The thin film transistor according to claim 1, characterized in that: An orthographic projection of the extension portion on the first side surface at least covers an orthographic projection of the channel portion on the first side surface.

3. The thin film transistor according to claim 2, characterized in that: Along the width direction of the channel portion, the size of the extension portion is greater than or equal to 1 micrometer and less than or equal to 3 micrometers; wherein the width direction of the channel portion is perpendicular to the length direction of the channel portion.

4. The thin film transistor according to claim 1, characterized in that: The orthographic projection of the first ring gate portion on the first side surface at least partially overlaps with the orthographic projection of the source on the first side surface, and the orthographic projection of the first ring gate portion on the first side surface at least partially overlaps with the orthographic projection of the drain on the first side surface.

5. The thin film transistor according to any one of claims 1 to 4, characterized in that: The source electrode and the drain electrode are both located on a side of the semiconductor layer away from the substrate and are arranged in the same layer; The gate layer further comprises a bottom gate layer and a top gate layer, wherein the bottom gate layer is located on a side of the semiconductor layer close to the substrate, and the top gate layer is located on a side of the source and the drain away from the substrate; The thin film transistor further includes a via hole penetrating the insulating layer, the first ring gate portion is located in the via hole, and the top gate layer is connected to the bottom gate layer through the first ring gate portion.

6. The thin film transistor according to claim 5, characterized in that: The orthographic projection of the bottom gate layer on the substrate covers the orthographic projections of the channel portion and the extension portion on the substrate, and the orthographic projection of the top gate layer on the substrate covers the orthographic projection of the channel portion on the substrate.

7. The thin film transistor according to any one of claims 1 to 4, characterized in that: The source is located on a side of the semiconductor layer close to the substrate, and the drain is located on a side of the semiconductor layer away from the substrate; wherein the extension portion is located on a side of the source away from the first ring gate portion and covers a surface of a side of the substrate close to the semiconductor layer.

8. The thin film transistor according to claim 7, characterized in that: The semiconductor layer further includes a second side surface and a third side surface which are arranged opposite to each other and are respectively connected to the first side surface; The ring gate layer also includes a second ring gate portion and a third ring gate portion which are arranged opposite to each other and connected to the first ring gate portion. The second ring gate portion is located on a side of the second side away from the third side, and the third ring gate portion is located on a side of the third side away from the second side.

9. The thin film transistor according to claim 8, characterized in that: The orthographic projection of the second ring gate portion on the second side surface does not overlap with the orthographic projection of the extension portion on the third side surface, and the orthographic projection of the third ring gate portion on the third side surface does not overlap with the orthographic projection of the extension portion on the third side surface.

10. An array substrate, characterized in that: The array substrate comprises the thin film transistor according to any one of claims 1 to 9.

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