Integrated circuit device

Abstract

The embodiment of the utility model provides an integrated circuit device. The integrated circuit device comprises a semiconductor substrate; a transistor including a channel in the semiconductor substrate, a gate over the channel, a gate dielectric between the gate and the channel, source and drain regions on opposite sides of the gate, where the source and drain regions have a first doping type and the channel has an opposite second doping type; a drift region provided by the semiconductor substrate, the drift region having a first doping type, contacting the drain region and the channel, having a doping concentration lower than that of the drain region, and extending below the gate; the first deep trap is arranged below the drain electrode region, the first deep trap has a first doping type, and the doping concentration of the first deep trap is higher than that of the drift region; and a second deep well under the drain region and the first deep well, the second deep well having a second doping type, having a doping concentration higher than that of the drift region, and being in contact with the first deep well to form a diode.

Description

Technical Field

[0001] An embodiment of the utility model relates to an integrated circuit device, and more particularly to an integrated circuit device including a clamping diode. Background Art

[0002] High voltage integrated circuits (HVICs) are widely used in switching power supplies, motor drives, and other power control systems. For example, an HVIC may include a low voltage device, a high voltage device, and a level shifter on a common semiconductor chip. It has long been recognized that these devices need to be made smaller and more robust. Utility Model Content

[0003] An embodiment of the utility model provides an integrated circuit device including: a semiconductor substrate; a transistor, including a channel in the semiconductor substrate, a gate above the channel, a gate dielectric between the gate and the channel, a source region and a drain region on opposite sides of the gate, wherein the source region and the drain region have a first doping type, and the channel has a second doping type opposite to the first doping type; a drift region provided by the semiconductor substrate, wherein the drift region has the first doping type, contacts the drain region and the channel, has a lower doping concentration than the drain region, and extends below the gate; a first deep well below the drain region, wherein the first deep well has the first doping type and a higher doping concentration than the drift region; and a second deep well below the drain region and the first deep well, wherein the second deep well has the second doping type, a higher doping concentration than the drift region, and contacts the first deep well to form a diode.

[0004] An embodiment of the utility model provides an integrated circuit device including: a semiconductor substrate; a transistor including a gate, a drain region, a drift region and a channel region, wherein the drift region, the drain region and the channel region are provided by the semiconductor substrate, the drift region and the drain region have N-type doping and the channel region has P-type doping; a first vertical PN junction below the gate, wherein the first vertical PN junction is formed by the drift region and a P-type doping region of the semiconductor substrate below the drift region; and a second vertical PN junction below the drain region, wherein the second vertical PN junction is formed by an N-well above the P-well; wherein the N-well has a higher doping concentration than the drift region; and the P-well has a higher doping concentration than the P-type doping region.

[0005] Based on the above, the problem of voltage overshoot causing impact ionization and performance degradation can be reduced or avoided by embedding the diode directly under the drain of the integrated circuit device. The embedded diode has a heavier doping than the drift region of the integrated circuit device, which reduces the breakdown voltage of the integrated circuit device.

[0006] In order to make the above features and advantages of the embodiments of the present invention more obvious and easy to understand, embodiments are specifically cited below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1A A cross-sectional side view of an integrated circuit (IC) device is shown in accordance with some embodiments.

[0008] Figure 1B Shows Figure 1A A plan view of an IC device.

[0009] Figure 2-Figure 9 A cross-sectional side view of an IC device according to various other embodiments is shown.

[0010] Figure 10-15 is an example of forming a Figure 1A A series of cross-sectional views of a method of IC device.

[0011] Fig.16 A flow chart illustrating a method of forming an IC device according to some embodiments is provided.

[0012] Description of Reference Numerals

[0013] 100A, 100B, 100C, 100D, 100E, 100F, 100H, 100I: IC device; 101: source contact plug; 103: source region; 105: gate contact; 107: gate; 109: gate dielectric; 110, 110A, 110B, 110C, 110D, 110E, 110F, 110H, 110I: transistor; 1 11: spacer; 113: drain contact; 115: drain region; 117: interlayer dielectric; 119: semiconductor substrate; 121: deep N well; 123: deep P well; 124: embedded diode; 125: embedded PN junction; 126: vertical PN diode; 127: vertical PN junction; 129: drift region; 130: junction; 131: P-type doped region; 133: channel region; 135: bulk region; 141: isolation structure; 401, 403: sidewall; 405: plane; 407: vertical surface; 701: body contact region; 703: field oxide structure; 705: buried n layer; 709: P well; 801: body contact plug; 803: shallow trench isolation (STI) structure; 901: supplementary oxide; 1000, 1100, 1200, 1300, 1 400, 1500: cross-sectional view; 1101: gate dielectric layer; 1103: gate electrode layer; 1105: gate stack; 1201, 1401: mask; 1600: process; 1601, 1603, 1605, 1606, 1607, 1609, 1610, 1611, 1613, 1615, 1617, 1619: action; D1: distance; θ: angle. DETAILED DESCRIPTION

[0014] The following disclosure provides many different embodiments or examples for implementing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the scope of the present invention. For example, in the following description, a first feature is formed "above" or "on" a second feature, which may include an embodiment in which the first feature and the second feature are formed to be in direct contact, or an embodiment in which an additional feature is formed between the first feature and the second feature so that the first feature and the second feature are not in direct contact. In addition, the present invention may reuse component numbers and / or letters in each example. Such repetition is for the purpose of simplifying and clearly describing the present invention, rather than for limiting the relationship between various embodiments and / or configurations.

[0015] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one component or feature to another (other) component or feature as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be in other orientations (rotated 90 degrees or at other orientations) and the spatially relative descriptors used therein may be interpreted in a similar manner.

[0016] Parasitic inductance may cause voltage overshoot in power switch circuits running at high switching speeds. Voltage overshoot may cause impact ionization and cause device performance degradation, which is manifested as a reduction in drain current. The utility model provides a device and method in which this type of performance degradation is reduced or avoided by embedding a diode directly under the drain of the device. The embedded diode has a heavier doping than the drift region of the device and reduces the breakdown voltage of the device.

[0017] Some aspects of the utility model relate to an integrated circuit device including a transistor, the transistor including a channel provided by a semiconductor substrate, a gate located above the channel, a gate dielectric between the gate and the channel, a source region and a drain region. A drift region located directly below the gate extends from the channel to the drain. An embedded diode is provided by a first deep well located directly below the drain and a second deep well of opposite doping type located directly below the first deep well. The first deep well has the same doping type as the drift region, but a higher doping concentration. The source / drain region may represent a source or a drain individually or collectively, depending on the context.

[0018] In some embodiments, the semiconductor substrate has opposite doping types in the regions directly below the drift region and directly below the gate, thereby forming a vertical PN diode directly below the gate electrode. The vertical PN diode has lighter doping than the embedded diode. Both the P-type and N-type regions of the embedded diode have heavier doping than the P-type and N-type regions of the vertical PN diode. In some embodiments, the doping concentration in the vertical PN diode is at least about an order of magnitude lower.

[0019] In some embodiments, the transistor is a high voltage device. In some embodiments, the transistor has a threshold voltage ranging from about 5 volts to about 35 volts. In some embodiments, the transistor is a laterally diffused metal oxide semiconductor (LDMOS) device. In some embodiments, the transistor is an n-channel device. In some embodiments, the transistor has a variable gate oxide thickness so that the gate oxide is thicker on the drain side. The embedded diode can be used as a clamping diode for the transistor.

[0020] In some embodiments, the deep P-well and deep N-well forming the embedded diode are doped in the same arrangement as the drain. For example, the drain can be doped to align with the spacer on the gate side, and the deep P-well and deep N-well can also be doped to align with the spacer. In some embodiments, the drain is aligned with the isolation structure. The isolation structure can be a field oxide structure (LOCOS) produced by local oxidation of silicon, a shallow trench isolation (STI) structure, etc. In some embodiments, the isolation structure extends under the gate electrode. Placing the embedded diode directly under the drain but not directly under the gate reduces the possibility of gate oxide damage when junction collapse occurs.

[0021] In some embodiments, the first deep well of the embedded diode is deep enough so that the drift region extends between the drain and the embedded diode. Advantages of placing the embedded diode deeper in the semiconductor substrate may include preventing the first deep well from lowering the threshold voltage of the transistor. In some embodiments, the doping of the deep P-well and deep N-well that form the embedded diode eliminates the drift region directly below the drain. The latter configuration can improve the protection provided by the embedded diode.

[0022] In some embodiments, the PN junction of the embedded diode is as shallow as or shallower than the bottom of the drift region. It may be easier to form an embedded diode at a relatively shallow location. In some embodiments, the PN junction of the embedded diode is deeper in the semiconductor substrate than the bottom of the drift region. Placing the PN junction of the embedded diode at a deeper position in the semiconductor substrate can help protect the gate dielectric when junction collapse occurs.

[0023] In some embodiments, the transistor is part of a multi-finger device. The number and / or length of the fingers may be selected to provide a desired current rating for the multi-finger device. In some embodiments, the drain and embedded diode are disposed between two adjacent fingers of the multi-finger device. The multi-finger device may be surrounded by an isolation structure such as a guard ring. The multi-finger device may be further isolated by a buried layer directly below the multi-finger device.

[0024] In some embodiments, a body contact region is formed in the semiconductor substrate adjacent to the source region. In some embodiments, the source of the transistor is connected to the body contact region. In some embodiments, the source is connected to both the source region and the body contact region. A terminal in the embedded diode can be coupled to the body contact region through the semiconductor substrate.

[0025] Figure 1A A cross-sectional view of an integrated circuit (IC) device 100A including a transistor 110A according to some embodiments is shown. The transistor 110A has a source region 103, a channel region 133, a drift region 129, and a drain region 115 formed in a semiconductor substrate 119. The channel region 133 is provided by a p-type doped region 131 of the semiconductor substrate 119. The drift region 129, the source region 103, and the drain region 115 have n-type doping. The transistor 110A also includes a gate 107 and a gate dielectric 109 separating the gate 107 from the semiconductor substrate 119. The gate 107 is disposed directly above a junction 130 between the channel region 133 and the drift region 129. The source region 103 and the drain region 115 may be aligned with spacers 111 disposed on both sides of the gate 107.

[0026] The embedded diode 124 is disposed directly below the drain region 115. The embedded diode 124 is provided by the deep N well 121 and the deep P well 123. The deep N well 121 and the deep P well 123 have a boundary location of the type formed by implanting dopants aligned with the spacers 111. In the example shown, the sidewalls are substantially vertical and horizontally aligned with the spacers 111.

[0027] In some embodiments, the deep N well 121 has a density ranging from about 1×10 17 Atoms (atoms / cm 3 ) to about 1x10 19 atoms / cm 3The doping concentration of the deep N well 121 is higher than that of the drift region 129. In some embodiments, the doping concentration of the deep N well 121 is about ten times or more the doping concentration of the drift region 129. The doping concentration of the drain region 115 is higher than that of the deep N well 121. In some embodiments, the doping concentration of the drain region 115 is about ten times or more the doping concentration of the deep N well 121. In some embodiments, the doping concentration of the semiconductor substrate 119 is minimum between the drain region 115 and the deep N well 121. In some embodiments, the drift region 129 extends between the drain region 115 and the deep N well 121.

[0028] In some embodiments, the deep P well 123 has a range from about 1×10 17 atoms / cm 3 To about 1x10 19 atoms / cm 3 In some embodiments, the deep P-well 123 has a doping concentration of the same order of magnitude as the deep N-well 121. In some embodiments, the deep P-well 123 has a higher doping concentration than the drift region 129. In some embodiments, the doping concentration of the deep P-well 123 is about ten times or more the doping concentration of the drift region 129. The semiconductor substrate 119 has a bulk region 135 having a p-type doping and located directly below the drift region 129 and the gate 107. In some embodiments, the doping concentration of the deep P-well 123 is about ten times or more the doping concentration of the P-type doping region 131.

[0029] Drift region 129 and bulk region 135 form vertical PN diode 126 with vertical PN junction 127 directly under gate 107. Deep N-well 121 and deep P-well 123 form embedded diode 124 with embedded PN junction 125 directly under drain region 115. In some embodiments, vertical PN junction 127 does not extend directly under drain region 115 because deep N-well 121 and deep P-well 123 occupy space lateral to vertical PN junction 127 and directly under drain region 115. In some embodiments, embedded PN junction 125 does not extend directly under gate 107 because deep N-well 121 and deep P-well 123 do not extend that far laterally. In transistor 110A, embedded PN junction 125 is lower than vertical PN junction 127.

[0030] In some embodiments, deep N well 121 is laterally displaced from gate 107 so that deep N well 121 does not extend directly under gate 107. In some embodiments, deep P well 123 is laterally displaced from gate 107 so that deep P well 123 does not extend directly under gate 107.

[0031] Figure 1B FIG. 1 is a plan view showing a portion of the IC device 100A. Figure 1BAs shown, gate 107 may be elongated to form strips. A plurality of these strips may be arranged and connected in parallel to form a device having multiple fingers. Drain region 115 is disposed between adjacent pairs of gates 107. Providing IC device 100A with multiple fingers may increase the current carrying capacity of IC device 100A while retaining the channel length and preventing the device from being overly elongated. Transistor 110A may be surrounded by isolation structure 141. In some embodiments, isolation structure 141 comprises a shallow trench isolation structure. In some embodiments, isolation structure 141 comprises a guard ring.

[0032] Figure 2 FIG. 1 shows a cross-sectional view of an IC device 100B including a transistor 110B according to some other embodiments. The transistor 110B is similar to Figure 1A In the transistor 110A, except that in the transistor 110B, the drift region 129 does not extend between the deep N well 121 and the drain region 115. Instead, the deep N well 121 abuts the drain region 115.

[0033] Figure 3 FIG. 4 shows a cross-sectional view of an IC device 100C including a transistor 110C according to some other embodiments. The transistor 110C is similar to Figure 2 In some embodiments, the embedded PN junction 125 is above the vertical PN junction 127, except that in the transistor 110B, the embedded PN junction 125 is at or above the vertical PN junction 127. In some embodiments, the embedded PN junction 125 is above the vertical PN junction 127.

[0034] Figure 4 FIG. 1 shows a cross-sectional view of an IC device 100D including a transistor 110D according to some other embodiments. The transistor 110D is similar to Figure 1A 10A, except that in transistor 110D, the sidewalls 401 of the deep N well 121 form an angle θ with a vertical plane 407 that is horizontally aligned with the spacer 111. The sidewalls 403 of the deep P well 123 may also form an angle θ with the vertical plane 407. The sidewalls 401 are located in a plane 405 that intersects the edge of the spacer 111. These are geometric features of the deep N well 121 formed by implanting dopant ions aligned with the spacer 111. The drain region 115 may also have a geometry created by dopants aligned with the spacer 111, but may have a different sidewall angle. The angle θ depends on the conditions used during the ion implantation process.

[0035] Figure 5 FIG. 4 shows a cross-sectional view of an IC device 100E including a transistor 110E according to some other embodiments. The transistor 110E is similar to Figure 1A10A, except that in transistor 110E, drain region 115 is laterally displaced from spacer 111. Drain region 115 may be laterally offset from gate 107 by distance D1. Distance D1 is greater than the width of spacer 111. In some embodiments, distance D1 is in a range of about 100 nanometers to about 2 μm. In some embodiments of transistor 110E, deep N-well 121, deep P-well 123 are aligned with drain region 115. This alignment may be achieved by doping drain region 115 with a mask that is also used to dope deep N-well 121 and deep P-well 123.

[0036] Figure 6 FIG. 1 shows a cross-sectional view of an IC device 100F including a transistor 110F according to some other embodiments. The transistor 110F is similar to Figure 5 The transistor 110E is shown in FIG. 1 , except that in the transistor 110F, the deep N-well 121 and the deep P-well 123 are aligned with the spacer 111 instead of the drain region 115 .

[0037] Figure 7 FIG. 1 shows a cross-sectional view of an IC device 100G including a transistor 110G according to some other embodiments. The transistor 110G is similar in many respects to FIG. Figure 1A 10A, but in transistor 110G, the drain region 115, the deep N-well 121, and the deep P-well 123 are aligned with the field oxide structure 703 below one side of the gate 107. The field oxide structure 703 may be provided to increase the threshold voltage of the transistor 110G. The IC device 100G shows optional additional structures of other embodiments. One option is that the semiconductor substrate 119 includes a buried n-layer 705, and the portion of the semiconductor substrate 119 above the buried n-layer 705 is formed by epitaxial growth. Another option is to include a P-well 709 directly below the drift region 129 in the area directly below the gate 107. The P-well 709 is doped more heavily than the bulk region 135, and like the drift region 129, the doping concentration ranges from about 10 16 / cm 3 To about 10 18 / cm 3 Another option is to include a body contact region 701 that interfaces with the source region 103. The body contact region 701 has a p-type doping. The source contact plug 101 can be coupled to the body contact region 701 instead of directly coupling to the source region 103. The p-terminal of the embedded diode 124 is coupled to the body contact region 701 through the p-type doped region 131 and the bulk region 135.

[0038] Figure 8 FIG. 1 shows a cross-sectional view of an IC device 100H including a transistor 110H according to some other embodiments. The transistor 110H is similar in many respects to FIG. Figure 710G, but in the transistor 110H, the drain region 115, the deep N-well 121, and the deep P-well 123 are aligned with the shallow trench isolation (STI) structure 803 under one side of the gate 107. Another difference is that in the transistor 110H, the source contact plug 101 is directly coupled to the source region 103. The body contact plug 801 is connected to the body contact region 701. The source contact plug 101 and the body contact plug 801 can be connected to the same source or to different voltage sources.

[0039] Fig. 9 FIG. 1 shows a cross-sectional view of an IC device 100I including a transistor 110I according to some other embodiments. The transistor 110I is similar in many respects to the Figure 7 10G, but in transistor 110I, drain region 115, deep N-well 121, and deep P-well 123 are aligned with spacers 111. In transistor 110I, the supplementary oxide 901 deposited on the drain side thickens the gate dielectric 109 on the drain side. The spacers 111 on the drain side may abut the supplementary oxide 901. In transistor 110I, the source contact plug 101 is in direct contact with the body contact region 701 and the source region 103.

[0040] According to the utility model, Figures 1A to 9 Various features of the IC devices 100A-I may be combined with one another to form additional embodiments. All of these examples illustrate n-channel devices. It should be understood that the doping types in these examples may be reversed to form p-channel devices according to the present invention.

[0041] Figures 10 to 15 2 is a cross-sectional view illustrating a method of forming an IC device according to the present invention. Figure 10 to Figure 15 Various embodiments are described with reference to methods, but it should be understood that Figure 10 to Figure 15 The structure shown in is not limited to the method but can be independent of the method. Figure 10 to Figure 15 Described as a series of actions. The order of these actions may be changed in other embodiments. Figures 10 to 15 A particular set of actions is illustrated and described, but some may be omitted in other embodiments. In addition, actions that are not shown and / or described may be included in other embodiments. Figures 10 to 15 Explained Figure 1A However, it should be understood that the method may be varied to form an IC device according to other embodiments of the present invention.

[0042] like Fig.10As shown in the cross-sectional view 1000 of , the method may start with providing a semiconductor substrate 119 and doping to provide a drift region 129 and a P-type doped region 131 as required. The semiconductor substrate 119 may be, for example, a bulk substrate (e.g., a bulk silicon substrate), a silicon-on-insulator (SOI) substrate, etc. The semiconductor may be silicon (Si), a Group III V or some other binary semiconductor, a ternary semiconductor (e.g., AlGaAs), a high-order semiconductor, etc. The upper portion of the semiconductor substrate 119 including the bulk region 135 may be a single crystal structure, an epitaxial growth structure, etc. In some embodiments, the bulk region 135 is the main body of the semiconductor substrate 119. In some embodiments, the bulk region 135 has a thickness of about 10 12 / cm 3 to about 10 15 / cm 3 range of doping concentration.

[0043] In some embodiments, the P-type doping region 131 has a P-type doping concentration of about 10 16 / cm 3 to about 10 18 / cm 3 In some embodiments, the P-type doping region 131 has a P-type doping concentration of about 10 17 / cm 3 , for example, ranging from about 5x10 16 / cm 3 About 4x10 17 / cm 3 In some embodiments, the P-type doped region 131 is provided by masking and then implanting P-type dopant ions. In some embodiments, the P-type doped region 131 is provided by and integrated with the bulk region 135, in which case the bulk region 135 is more heavily doped to provide a suitable doping concentration for the channel region 133 (see Figure 1A In some embodiments, the P-type doping region 131 is formed by performing a lateral diffusion process after forming the gate 107 (see Figure 1A The lateral diffusion process includes implanting P-type dopants on the source side of the gate 107 and then performing a heat treatment to cause the dopants to diffuse.

[0044] In some embodiments, the drift region 129 has an N-type doping, wherein the doping concentration is about 10 16 / cm 3 to about 10 18 / cm 3 In some embodiments, the drift region 129 has an N-type doping concentration of about 10 17 / cm 3, for example, ranging from about 5x10 16 / cm 3 About 4x10 17 / cm 3 In some embodiments, the drift region 129 is provided by masking and then implanting P-type dopant ions. In some embodiments, the drift region 129 is formed by performing a lateral diffusion process after forming the gate 107 (see Figure 1A The lateral diffusion process includes implanting N-type dopants on the drain side of the gate 107 and then performing a heat treatment to cause the dopants to diffuse.

[0045] like Fig.11 As shown in the cross-sectional view 1100 of , the process may continue to form a gate stack 1105 on the semiconductor substrate 119. The gate stack 1105 includes a gate dielectric layer 1101 and a gate electrode layer 1103. In some embodiments, the formation of the gate dielectric layer 1101 includes oxidizing the upper surface of the semiconductor substrate 119. In some embodiments, the formation of the gate dielectric layer 1101 includes depositing one or more dielectric layers. The deposition process may be physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), etc., or some other suitable process. The gate dielectric layer may include one or more layers of a dielectric material. The dielectric material may be or include silicon dioxide (SiO2), a high dielectric constant dielectric, etc., or some other suitable dielectric. In some embodiments, the gate dielectric layer 1101 is or includes silicon dioxide (SiO2), etc. The gate electrode layer 1103 may be deposited by PVD, CVD, ALD or some other suitable process, etc. The gate electrode layer 1103 may be or include a conductive material, such as metal, polysilicon, graphene, etc. In some embodiments, the gate electrode layer 1103 is polysilicon, etc.

[0046] According to various embodiments of the present invention, additional processing may be performed during or before forming the gate stack 1105 to produce a device. For example, masking and oxidation processes may be performed to produce Figure 7 The field oxide structure 703 may be formed by performing masking, etching, deposition and planarization processes. Figure 8 The STI structure 803 may be formed by performing deposition and etching processes. Fig. 9 Supplementary oxide 901.

[0047] like Fig.12As shown in the cross-sectional view 1200 of FIG. 1 , the process may continue to form a mask 1201 and etch from the gate stack 1105 to pattern the transistor 110. The mask 1201 may be patterned by photolithography or the like. The patterning process may include plasma etching or the like. The patterning produces a gate dielectric 109 from the gate dielectric layer 1101 and a gate 107 from the gate electrode layer 1103.

[0048] like Fig.13 As shown in the cross-sectional view 1300 of FIG. 1 , a spacer 111 may be formed on the sidewalls of the transistor 110. Forming the spacer 111 may include depositing a spacer material and then performing anisotropic plasma etching to leave thicker material only on the sidewalls. The deposition process may be PVD, CVD, ALD, etc. or any other suitable process. The spacer material may include one or more layers of a dielectric oxide, a nitride, a carbide, a combination thereof, etc. In some embodiments, the spacer material includes silicon nitride (SiN), etc.

[0049] like Fig.14 As shown in the cross-sectional view 1400 of FIG. 1 , a mask 1401 may be formed and an ion implantation process may be performed to sequentially form a deep P well 123 and a deep N well 121. When the ion implantation occurs, the mask 1401 covers the semiconductor substrate 119 on the source side of the transistor 110. According to some embodiments, one or both ion implantation processes are self-aligned with the spacer 111 on the drain side of the transistor 110. In some embodiments, one or both doping processes to form the deep P well 123 and the deep N well 121 are self-aligned with the gate 107 on the drain side of the transistor 110. In some embodiments, one or both doping processes are self-aligned with the field oxide structure 703 on the drain side of the transistor 110 (see FIG. 1 ). Figure 7 In some embodiments, one or both doping processes are self-aligned with the STI structure 803 on the drain side of the transistor 110 (see Figure 8 In some embodiments, mask 1401 extends to the drain side of transistor 110, so that one or both of deep P-well 123 and deep N-well 121 are laterally offset from transistor 110 (see FIG. Figure 5 ).

[0050] In some embodiments, the dopant for forming the deep P well 123 and the dopant for forming the deep N well 121 are respectively implanted by an ion implantation process at a depth of about 10 13 / cm 2 to about 10 17 / cm 2 In some embodiments, the dose is about 10 13 / cm 2 to about 10 16 / cm 2The energy level of the implantation process can be adjusted to obtain a desired doping depth. In some embodiments, the dopant of the deep N well 121 deposits more energy than the dopant forming the drift region 129. In some embodiments, the dopant of the deep P well 123 deposits more energy than the dopant forming the drift region 129. In some embodiments, the dopant of the deep P well 123 deposits more energy than the dopant of the deep N well 121. The degree of anisotropy of the dopant implantation process can be controlled to change the angle θ (see FIG. 1 ) at which the deep P well 123 and the deep N well 121 are aligned with the spacer 111. Figure 4 ).

[0051] like Fig.15 As shown in the cross-sectional view 1500 of FIG. 1 , another ion implantation process may be performed to form the source region 103 and the drain region 115. The ion implantation process may provide N-type doping and may have lower energy than the ion implantation used to form the deep P well 123 and the deep N well 121, making the source region 103 and the drain region 115 shallower. In some embodiments, the dopant is deposited to about 10 19 / cm 3 to about 10 21 / cm 3 In some embodiments, drain region 115 is self-aligned to the same structure that is self-aligned with deep P well 123 and deep N well 121, such as self-aligned to spacer 111. Masking and p-type dopant implantation can also be performed at this processing stage to form a p-type doped contact region, such as body contact region 701 (see Figure 7 ).

[0052] Further processing provides interlayer dielectric 117, source contact plug 101, gate contact 105 and drain contact 113, such as Figure 1A As shown. The interlayer dielectric 117 can be any other suitable dielectric such as silicon oxide (SiO), a low dielectric constant dielectric, etc. The interlayer dielectric 117 can be formed by CVD, PVD, etc. or any other suitable process. A mask can be formed and used to etch holes through the interlayer dielectric 117. Metal can be deposited to fill the holes to form the source contact plug 101, the gate contact 105 and the drain contact 113. Excess metal can be removed by a planarization process such as chemical mechanical polishing (CMP). The metal can be, for example, aluminum, copper, titanium, tantalum, titanium nitride, tantalum nitride, ruthenium, tungsten, another conductive material, etc., or any combination of the foregoing. Figure 10 to Figure 15 The examples described above describe the formation of n-channel devices. The doping types in these examples can be reversed to form p-channel devices.

[0053] Fig.16A flow chart of a process 1600 that can be used to form an IC device according to the present invention is presented. Fig.16 The process 1600 is shown and described herein as a series of acts or events, but it should be understood that the order in which the acts or events are shown should not be construed in a limiting sense. For example, some acts may occur in a different order and / or concurrently with other acts or events than illustrated and / or described herein. In addition, not all of the acts shown are required to implement one or more aspects or embodiments described herein, and one or more of the acts described herein may be implemented in one or more separate acts and / or stages. The process 1600 includes forming Figure 1A Variations of the process 1600 may be used to form other integrated circuit devices of the present invention.

[0054] The process 1600 may begin with act 1601 , providing a semiconductor substrate, act 1603 , forming a well of a first doping type to provide a drift region, and act 1605 , forming a well of a second doping type to provide a channel. Fig.10 An example is provided by the cross-sectional view 1000 of In some embodiments, the semiconductor substrate includes a buried layer of a first doping type. Figure 7 The buried n-layer 705 of FIG. 1 provides an example of such a layer. An epitaxial layer of a second doping type may be grown on the buried layer. Optionally, action 1603 and / or action 1605 are omitted and a well of the first doping type is formed and / or a well of the second doping type is formed provided by action 1610, which is a lateral diffusion process that does not occur until after action 1609 (patterning the gate stack).

[0055] Process 1600 may continue with act 1606 to form a barrier structure for the gate. The barrier structure provides a barrier to conduction between the drain and the channel, thereby increasing the threshold voltage. Possible examples of barrier structures include Figure 7 Field oxide structure 703, Figure 8 The STI structure 803 and Fig. 9 Supplementary oxide 901.

[0056] The process may continue with act 1607 to form a gate stack. Fig.11 An example is provided in the cross-sectional view 1100 of FIG. The gate stack includes at least a dielectric layer and an electrode layer. Action 1609 is patterning the gate stack to form a gate. Fig.12 An example is provided in cross-sectional view 1200 .

[0057] Action 1610 is a selective step of forming a well of a first doping type by lateral diffusion from the drain side of the gate and / or forming a region of a second doping type by lateral diffusion from the source side of the gate. Action 1610 may be used in place of action 1603 and / or action 1605. The lateral diffusion process includes implanting dopants and then performing a heat treatment to induce diffusion of the dopants to form drift and / or channel regions.

[0058] Action 1611 is to form sidewall spacers (sidewall spacers). Fig.13 An example is provided in cross-sectional view 1300 .

[0059] Action 1613 is doping to form a deep P-well on the drain side of the gate. Action 1615 is doping to form a deep N-well over the deep P-well. During these doping processes, the source side may be shielded. Fig.14 An example is provided in cross-sectional view 1400 of . These doping processes form an embedded diode that is disposed below the drain region of the transistor.

[0060] Action 1617 is to perform doping to form source and drain regions adjacent to the gate. Fig.15 An example is provided in the cross-sectional view 1500 of FIG. 1. A self-aligned silicide process may be performed on the source region and the drain region to form a silicide contact layer. Action 1619 is a back end of line (BEOL) process. The BEOL process forms source, drain, gate and body contact plugs and metal interconnect structures (not shown) on the semiconductor substrate.

[0061] Some aspects of the utility model relate to an integrated circuit device, which includes a transistor with a channel provided by a semiconductor substrate, a gate directly above the channel, a gate dielectric between the gate and the channel, and a source region and a drain region on opposite sides of the gate electrode. The source region and the drain region have a first doping type, and the channel has a second doping type opposite to the first doping type. The drift region provided by the semiconductor substrate has a first doping type and contacts the drain region and the channel. The doping concentration of the drift region is lower than that of the drain region and extends directly below the gate electrode. There is a first deep well of the first doping type directly below the drain region. The doping concentration of the first deep well is higher than that of the drift region. There is a second deep well directly below the drain region and the first deep well. The second deep well has a second doping type and has a higher doping concentration than the drift region, and contacts the first deep well to form a diode.

[0062] In some embodiments, the drift region separates the drain region from the first deep well. In some embodiments, the diode is used as a clamping diode for a transistor. In some embodiments, the first deep well is doped to align with the drain region. In some embodiments, the second deep well is doped to align with the drain region. In some embodiments, the first deep well extends deeper into the semiconductor substrate than the drift region. In some embodiments, the diode is deeper in the semiconductor substrate than the bottom in the drift region. In some, wherein the gate is one of a plurality of fingers. In some embodiments, the first deep well is laterally displaced from the gate electrode. In some embodiments, a buried layer is directly below the second deep well and the gate, wherein the buried layer has a first doping type. In some embodiments, a third deep well is directly below the gate and the drift region and directly above the buried layer, wherein the third deep well has a second doping type and a lower doping concentration than the second deep well. In some embodiments, the second deep well extends deeper into the semiconductor substrate than the third deep well.

[0063] Some aspects of the utility model relate to an integrated circuit device including a transistor having a gate, a drain region, a drift region and a channel region provided by a semiconductor substrate. The drift region and the drain region have N-type doping. The channel region has P-type doping. The drift region of the semiconductor substrate and the P-type doping region directly below the drift region form a first vertical PN junction directly below the gate electrode. The N-well directly above the P-well directly below the drain region provides a second vertical PN junction. The doping concentration of the N-well is higher than that of the drift region. The doping concentration of the P-well is higher than that of the P-type doping region.

[0064] In some embodiments, the second vertical PN junction is deeper than the first vertical PN junction. In some embodiments, the semiconductor substrate includes an epitaxial layer with P-type doping directly above a buried layer with N-type doping, wherein the buried layer with N-type doping is directly below the transistor. In some embodiments, the transistor is part of a power switch circuit. In some embodiments, the second vertical PN junction reduces the breakdown voltage of the transistor. In some embodiments, the P-well is coupled to the body contact region with P-type doping through a portion of the semiconductor substrate with P-type doping.

[0065] Some aspects of the utility model relate to a method for forming an integrated circuit device. The method includes doping a semiconductor substrate to form a drift region and a channel region, which has a junction adjacent to a surface of the semiconductor substrate, forming a gate stack on the semiconductor substrate, patterning the gate stack to form a gate directly above the junction, forming a spacer abutting the gate, implanting a deep P well, implanting a deep N well directly above the deep P well, and implanting dopants to form a drain region directly above the deep P well and the deep N well. The doping concentration of the deep P well and the deep N well is higher than that of the drift region. In some embodiments, the deep P well and the deep N well are aligned with the spacer.

[0066] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the embodiments of the utility model, rather than to limit them. Although the embodiments of the utility model are described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. However, these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the utility model.

Claims

1. An integrated circuit device, characterized in that: include: Semiconductor substrate; a transistor comprising a channel in the semiconductor substrate, a gate over the channel, a gate dielectric between the gate and the channel, a source region and a drain region on opposite sides of the gate, wherein the source region and the drain region have a first doping type and the channel has a second doping type opposite to the first doping type; a drift region provided by the semiconductor substrate, wherein the drift region has the first doping type, contacts the drain region and the channel, has a lower doping concentration than the drain region, and extends below the gate; a first deep well below the drain region, wherein the first deep well has the first doping type and a higher doping concentration than the drift region; as well as A second deep well is below the drain region and the first deep well, wherein the second deep well has the second doping type, a higher doping concentration than the drift region, and contacts the first deep well to form a diode.

2. The integrated circuit device according to claim 1, wherein: The drift region separates the drain region from the first deep well.

3. The integrated circuit device according to claim 1, wherein: The first deep well is doped to be aligned with the drain region.

4. The integrated circuit device according to claim 1, wherein: The first deep well extends deeper into the semiconductor substrate than the drift region.

5. The integrated circuit device according to claim 1, wherein: The diode is deeper in the semiconductor substrate than a bottom of the drift region.

6. The integrated circuit device according to claim 1, wherein: The first deep well and the gate are laterally shifted.

7. An integrated circuit device, characterized in that: include: Semiconductor substrate; A transistor, comprising a gate, a drain region, a drift region and a channel region, wherein the drift region, the drain region and the channel region are provided by the semiconductor substrate, the drift region and the drain region have N-type doping and the channel region has P-type doping; a first vertical PN junction below the gate, wherein the first vertical PN junction is formed by the drift region and a P-type doped region of the semiconductor substrate below the drift region; as well as a second vertical PN junction below the drain region, wherein the second vertical PN junction is formed by an N well above the P well; wherein the N-well has a higher doping concentration than the drift region; as well as The P-well has a higher doping concentration than the P-type doping region.

8. The integrated circuit device according to claim 7, characterized in that The second vertical PN junction is deeper than the first vertical PN junction.

9. The integrated circuit device according to claim 7, characterized in that The semiconductor substrate includes an epitaxial layer with P-type doping directly above a buried layer with N-type doping, wherein the buried layer with N-type doping is directly below the transistor.

10. The integrated circuit device according to claim 7, characterized in that The P-well is coupled to a P-type doped body contact region through a P-type doped portion of the semiconductor substrate.

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