Interface test circuit for OCP board

Abstract

The utility model discloses an interface test circuit used for an OCP board, the test circuit is used for testing the OCP board, the test circuit comprises a sampling circuit, a digital display control circuit and a connector circuit, the connector circuit comprises a connector chip, a first connection circuit and a second connection circuit, the first connection circuit and the second connection circuit are electrically connected with the connector chip, the digital display control circuit comprises a module chip and a digital display board chip electrically connected with the module chip, the sampling circuit comprises a sampling chip, and the sampling chip in the sampling circuit is matched with each resistor connected with the sampling chip, so that batch OCP boards are detected, and the detection efficiency is improved. And a digital display board arranged on the digital display control circuit is used for displaying, so that a user can conveniently carry out visual operation on the data information of the OCP board, meanwhile, the overall reliability of displaying the detection result of the OCP board by the module chip is improved, and the user can conveniently record related data of the OCP board, so that the OCP board can be rapidly detected.

Description

Technical Field

[0001] The utility model relates to the technical field of circuits, and in particular to an interface test circuit for an OCP board. Background Art

[0002] With the rapid development of industrial manufacturing, people have higher and higher requirements for the detection of OCP boards on circuit boards. At present, the integration of circuit boards is getting higher and higher, and the required detection equipment is getting more and more complicated. How to quickly test the OCP board to ensure that these power modules can work reliably requires the use of circuit board testing equipment. The current OCP board cannot be connected point-to-point during the power-on process, so that the reliability of the detection result is not high during the voltage test. During the detection of the OCP board, multiple OCP boards need to be repeatedly plugged and unplugged into the slot. The operator needs to repeatedly cut off the power supply during the test, and the detection data is not accurate enough during the power-on process. The existing test equipment on the market needs to supply power to the OCP board separately, and the circuit needs to be disconnected on the mainboard during the detection. The OCP network card needs to be frequently plugged and unplugged during batch testing, and the plug-in interface on the wear device is also unreliable. It cannot be miniaturized, intelligent, and automated, and the reliability of the detection of the OCP board cannot be improved. The existing OCP test circuit has the problem of low efficiency in testing the OCP board. Utility Model Content

[0003] The utility model discloses an interface test circuit for an OCP board, aiming to overcome the problem of low OCP board test efficiency in the existing OCP test circuit.

[0004] An interface test circuit for an OCP board, wherein the test circuit is used to test a circuit board, the test circuit comprises: a sampling circuit, a digital display control circuit, and a connector circuit, the connector circuit comprises a connector chip and a first connection circuit and a second connection circuit electrically connected to the connector chip, the digital display control circuit comprises a module chip and a digital display board electrically connected to the module chip, and the sampling circuit comprises a sampling chip;

[0005] The sampling circuit includes: a sampling chip, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, a first power supply, a second power supply, a third power supply, and a fourth power supply, wherein a current output end of the first power supply is simultaneously connected to one end of the first capacitor, one end of the second capacitor, one end of the first resistor, and one end of the second resistor, the other end of the first capacitor and the other end of the second capacitor are both grounded, the other end of the first resistor is simultaneously connected to the current output end of the second power supply, one end of the fourth capacitor, one end of the third resistor, an IN-P port of the sampling chip, and a VBUS port of the sampling chip, the other end of the fourth capacitor is grounded, and the other end of the second resistor is connected to the IN-N port of the sampling chip. The third resistor is arranged in parallel at one side of the first resistor, the ground end of the sampling chip is grounded, the third power supply is connected to the VS port of the sampling chip and one end of the fifth capacitor, the other end of the fifth capacitor is grounded, the current output end of the fourth power supply is connected to one end of the fourth resistor, the other end of the fourth resistor is connected to the A1 port of the sampling chip, the A0 port of the sampling chip is connected to one end of the fifth resistor, the other end of the fifth resistor is grounded, the SDA port of the sampling chip is connected to one end of the sixth resistor, the other end of the sixth resistor is connected to the SDA port set in the module chip of the digital display control circuit, the SCL port of the sampling chip is connected to one end of the seventh resistor, the other end of the seventh resistor is connected to the SCL port set in the module chip of the digital display control circuit, and the GND port of the sampling chip is grounded;

[0006] After the module chip provided in the sampling circuit is electrically connected to the digital display control circuit, the display provided in the digital display control circuit can display the current current value.

[0007] An interface test circuit for an OCP board, wherein the digital display control circuit comprises: a module chip, an eighth resistor, a ninth resistor, a sixth capacitor, a seventh capacitor, an eighth capacitor, a ninth capacitor, a fifth power supply, and a sixth power supply, wherein the current output end of the fifth power supply is simultaneously connected to one end of the eighth resistor and one end of the ninth resistor, the other end of the eighth resistor is simultaneously connected to the SCL port of the module chip and one end of the sixth capacitor, the other end of the ninth resistor is simultaneously connected to the SDA port of the module chip and one end of the seventh capacitor, the other end of the eighth resistor and the other end of the ninth resistor are both grounded, and the VDD port of the module chip is simultaneously connected to one end of the eighth capacitor, one end of the ninth capacitor, and the current output end of the sixth power supply.

[0008] An interface test circuit for an OCP board, wherein the first connection circuit includes a tenth resistor, an eleventh resistor, a twelfth resistor, a thirteenth resistor, a fourteenth resistor, a fifteenth resistor, a sixteenth resistor, a seventeenth resistor, an eighteenth resistor, and a seventh power supply, the SMCLK port of the connector chip is simultaneously connected to one end of the twelfth resistor and one end of the thirteenth resistor, the SMDAT port of the connector chip is simultaneously connected to one end of the fourteenth resistor and one end of the eleventh resistor, the SMRST port of the connector chip is simultaneously connected to one end of the fifteenth resistor and one end of the tenth resistor, the other end of the tenth resistor, the tenth resistor, the SMCLK port of the connector chip are simultaneously connected to one end of the twelfth resistor and one end of the thirteenth resistor, the SMDAT port of the connector chip is simultaneously connected to one end of the fourteenth resistor and one end of the eleventh resistor, the SMRST port of the connector chip is simultaneously connected to one end of the fifteenth resistor and one end of the tenth resistor, the other end of the tenth resistor, the The other end of the first resistor and the other end of the twelfth resistor are both connected to the current output end of the seventh power supply, the other end of the thirteenth resistor is connected to a BMC-SCL port, the other end of the fourteenth resistor is connected to a BMC-SDA port, the other end of the fifteenth resistor is connected to a PLD-SMB port, the PERSTA port of the connector chip is connected to one end of the sixteenth resistor, the PERST1 port of the connector chip is connected to one end of the seventeenth resistor, the seventeenth resistor is connected to a RST-OCP3 port, and the PRSNTB2 port of the connector chip is connected to an OCP-PRSNTB test port.

[0009] An interface test circuit for an OCP board, wherein the second connection circuit includes: an eighteenth resistor and an eighth power supply, multiple EDGE ports provided on the connector chip are simultaneously connected to a signal input port of an OCP board, and the PERST0 port of the connector chip is connected to one end of the eighteenth resistor, the other end of the eighteenth resistor is connected to a RST-OCP port, and the current output end of the eighth power supply is connected to a current port provided on one side of the connector chip.

[0010] An interface test circuit for an OCP board, wherein one side of the connector chip is also connected to a signal transmission circuit, the signal transmission circuit includes a nineteenth resistor, a twentieth resistor, and a ninth power supply, a PWRBRK0 port of the connector chip is simultaneously connected to one end of the nineteenth resistor and one end of the twentieth resistor, the other end of the nineteenth resistor is connected to a current output end of the ninth power supply, the other end of the twentieth resistor is connected to an OCP-PWRBRK0 port, and a PRSNTB3 port of the connector chip is connected to an OCP-PRSNTVB3 port.

[0011] An interface test circuit for an OCP board, wherein the digital display board chip is electrically connected to a digital display board, and the digital display board is composed of a plurality of red display tubes, and the red display tubes form an "8"-shaped display unit, and a digital display board can include one or more display units.

[0012] An interface test circuit for an OCP board, wherein the supply voltage of the first power supply and the supply voltage of the second power supply are both 12V.

[0013] An interface test circuit for an OCP board, wherein the supply voltage of the third power supply and the supply voltage of the fourth power supply are both 3V.

[0014] An interface test circuit for an OCP board, wherein the supply voltage of the fifth power supply set in the digital display control circuit and the supply voltage of the sixth power supply are both 5V.

[0015] An interface test circuit for an OCP board, wherein the first connection circuit and the second connection circuit are both grounded.

[0016] Compared with the prior art, the utility model has the following advantages:

[0017] The utility model discloses an interface test circuit for an OCP board. The test circuit is used for testing the OCP board. The test circuit comprises: a sampling circuit, a digital display control circuit, and a connector circuit. The connector circuit comprises: a connector chip and a first connection circuit and a second connection circuit electrically connected to the connector chip. The digital display control circuit comprises a module chip and a digital display board chip electrically connected to the module chip. The sampling circuit comprises a sampling chip. The sampling chip in the sampling circuit and each resistor connected to the sampling chip cooperate to detect a batch of OCP boards. The digital display board provided by the digital display control circuit is then used for display, so that users can conveniently perform visual operation on the data information of the OCP board. Meanwhile, the overall reliability of the module chip displaying the detection result of the OCP board is improved, so that users can conveniently record the relevant data of the OCP board, thereby quickly detecting the OCP board. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions of the embodiments of the utility model, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of the utility model. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0019] Figure 1 An overall circuit diagram of a sampling circuit for an interface test circuit of an OCP board provided by an embodiment of the utility model;

[0020] Figure 2 A circuit diagram of a digital display control circuit for an interface test circuit of an OCP board provided by an embodiment of the utility model;

[0021] Figure 3 A circuit diagram of a first connection circuit of an interface test circuit for an OCP board provided by an embodiment of the utility model;

[0022] Figure 4 A circuit diagram of a second connection circuit of an interface test circuit for an OCP board provided by an embodiment of the utility model;

[0023] Figure 5 A circuit diagram of a signal transmission circuit for an interface test circuit of an OCP board provided by an embodiment of the utility model;

[0024] Figure 6 A circuit diagram of a connector circuit for an interface test circuit of an OCP board provided in an embodiment of the utility model.

[0025] Sampling circuit S1, digital display control circuit S2, connector circuit S3, first connection circuit S4, second connection circuit S5, signal transmission circuit S6;

[0026] Sampling chip U1, module chip U2, digital display board chip U3, connector chip U4;

[0027] A first power supply V1, a second power supply V2, a third power supply V3, a fourth power supply V4, a fifth power supply V5, a sixth power supply V6, a seventh power supply V7, an eighth power supply V8, and a ninth power supply V9;

[0028] A first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, a sixth capacitor C6, a seventh capacitor C7, an eighth capacitor C8, and a ninth capacitor C9;

[0029] The first resistor R1, the second resistor R2, the third resistor R3, the fourth resistor R4, the fifth resistor R5, the sixth resistor R6, the seventh resistor R7, the eighth resistor R8, the ninth resistor R9, the tenth resistor R10, the eleventh resistor R11, the twelfth resistor R12, the thirteenth resistor R13, the fourteenth resistor R14, the fifteenth resistor R15, the sixteenth resistor R16, the seventeenth resistor R17, the eighteenth resistor R18, the nineteenth resistor R19, and the twentieth resistor R20. DETAILED DESCRIPTION

[0030] The following will be combined with the drawings in the embodiments of the utility model to clearly and completely describe the technical solutions in the embodiments of the utility model. Obviously, the described embodiments are part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments of the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.

[0031] It should be understood that when used in this specification and the appended claims, the terms "include" and "comprises" indicate the presence of described features, integers, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or combinations thereof.

[0032] It should also be understood that the terms used in the utility model specification are only for the purpose of describing specific embodiments and are not intended to limit the utility model. As used in the utility model specification and the appended claims, unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" are intended to include plural forms.

[0033] It should be further understood that the term “and / or” used in the present specification and the appended claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0034] See also Figure 1 , Figure 2 , Figure 3 , Figure 4 as well as Figure 6 As shown in the figure, the test circuit is used to test the circuit board, and the test circuit includes: a sampling circuit S1, a digital display control circuit S2, and a connector circuit S3. The connector circuit S3 includes a connector chip U4 and a first connection circuit S4 and a second connection circuit S5 electrically connected to the connector chip U4. A main board (not shown in the figure) is also connected to one side of the first connection circuit S4. The digital display control circuit S2 includes a module chip U2 and a digital display board (not shown in the figure) electrically connected to the module chip U2. The sampling circuit S1 includes a sampling chip U1.

[0035] The sampling circuit S1 includes: a sampling chip U1, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, a first power supply V1, a second power supply V2, a third power supply V3, and a fourth power supply V4, wherein a current output end of the first power supply V1 is simultaneously connected to one end of the first capacitor C1, one end of the second capacitor C2, one end of the first resistor R1, and one end of the second resistor R2, the other end of the first capacitor C1 and the other end of the second capacitor C2 are both grounded, the other end of the first resistor R1 is simultaneously connected to the current output end of the second power supply V2, one end of the fourth capacitor C4, one end of the third resistor R3, the IN-P port of the sampling chip U1, and the VBUS port of the sampling chip U1, the other end of the fourth capacitor C4 is grounded, and the other end of the second resistor R2 is connected to the sampling chip U1. 1, the third resistor R3 is arranged in parallel on one side of the first resistor R1, the ground end of the sampling chip U1 is grounded, the third power supply V3 is connected to the VS port of the sampling chip U1 and one end of the fifth capacitor C5, the other end of the fifth capacitor C5 is grounded, the current output end of the fourth power supply V4 is connected to one end of the fourth resistor R4, the other end of the fourth resistor R4 is connected to the A1 port of the sampling chip U1, the A0 port of the sampling chip U1 is connected to one end of the fifth resistor R5, the other end of the fifth resistor R5 is grounded, the SDA port of the sampling chip U1 is connected to one end of the sixth resistor R6, the other end of the sixth resistor R6 is connected to the SDA port set in the module chip U2 of the digital display control circuit S2, the SCL port of the sampling chip U1 is connected to one end of the seventh resistor R7, the other end of the seventh resistor R7 is connected to the SCL port set in the module chip U2 of the digital display control circuit S2, and the GND port of the sampling chip U1 is grounded.

[0036] After the module chip U2 provided in the sampling circuit S1 is electrically connected to the digital display control circuit S2, the display provided in the digital display control circuit S2 can display the current current value.

[0037] Specifically, in the embodiment of the present scheme, the interface test circuit is suitable for performing a voltage test on an OCP circuit board. First, a plurality of EDGE ports provided at one end of the connector circuit S3 are electrically connected to the OCP board to perform a power-on test. A plurality of power supplies (a first power supply V1, a second power supply V2, a third power supply V3, and a fourth power supply V4) are provided at one end of the acquisition chip. Through four power supplies of different specifications, current is output to the acquisition chip to facilitate signal acquisition by the acquisition chip. At the same time, the SCL port and the SDA port provided on one side of the acquisition chip are respectively connected to the SCL port and the SDA port of the digital display board chip U3. The acquisition chip sends the collected data signal to the digital display board chip U 3 is used for signal forwarding. At this time, the digital display board chip U3 receives the forwarded data, and displays the data through the digital display board set on one side of the digital display board chip U3. One side of the digital display board chip U3 is directly electrically connected to the connector chip U4 set by the connector circuit S3, so that the acquisition chip can directly perform data acquisition after being electrically connected to the OCP board connected to the connector circuit S3, thereby reducing unnecessary acquisition steps. In this setting method, the OCP board is directly plugged into one side of the connector circuit S3. At this time, each connection port of the OCP board is connected one-to-one with multiple EDGE ports of the connector chip U4, without the need to set up multiple components to hinder, thereby facilitating the acquisition of the OCP board.

[0038] Further, in one embodiment, a test device is provided with a slot for an OCP board, and four connection holes are provided in the slot, namely a first connection hole, a second connection hole, a third connection hole, and a fourth connection hole, wherein a 5V power supply is configured to power the OCP board to be sampled, the first connection hole and the second connection hole are respectively connected to the positive connection terminal and the negative connection terminal of the power supply, the third connection hole is connected to a sampling port on the OCP board, the third connection hole is a connection hole for data transmission of sampled data, and one end of the first connection hole is also connected to a power supply port on the OCP board for powering the OCP board.

[0039] Further, in one embodiment, the sampling circuit S1 is provided with a plurality of sampling resistors (a second resistor R2, a fourth resistor R4, a fifth resistor R5, and a sixth resistor R6) and a plurality of capacitors (a third capacitor C3, a fifth capacitor C5, a sixth capacitor C6, and an eighth capacitor C8). After the sampling resistors are used in conjunction with the capacitors, the voltage of the OCP board to be tested is detected. The sampling chip U1 can detect the voltage fluctuation between 0V and 36V. When the detection voltage is P12V, it is the normal voltage. The device follows the bus power supply voltage and the shunt voltage drop. Through the combination of an internal multiplier, a programmable calibration value, a conversion timing, and an average, the current in amperes and the power in watts can be directly read. The digital display board chip U3 of the digital display control circuit S2 directly captures the data line (SCL port and SDA port) to detect the current and the voltage information, so that the multiple red display tubes of the digital display board are directly displayed in time, which is convenient for users to quickly detect the OCP board.

[0040] Furthermore, in one embodiment, a mainboard is also connected to one side of the first connection circuit, and the mainboard is used to perform voltage control on the connector chip so as to achieve a stable connection between the connector chip and the OCP board. Multiple ports on one side of the connector chip are respectively connected to multiple ports of the mainboard, and the ports including (P3E-CPU1-PEC-RX DN port, P3E-CPU1-PEC-RX-DP port, PCIE-OCP-CUK2-DN port, PCIE-OCP-CUK2-DP port and OCP3-PRSNTB1-N port) are all electrically connected to the mainboard, and multiple ports are set to perform voltage control on the connector chip.

[0041] See also Figure 2As shown in the figure, the digital display control circuit S2 includes: a module chip U2, an eighth resistor R8, a ninth resistor R9, a sixth capacitor C6, a seventh capacitor C7, an eighth capacitor C8, a ninth capacitor C9, a fifth power supply V5, and a sixth power supply V6. The SCL port and the SDA port set on one side of the sampling circuit are respectively connected to the SCL port and the SDA port set on the module chip. The current output end of the fifth power supply V5 is simultaneously connected to one end of the eighth resistor R8 and one end of the ninth resistor R9. The other end of the eighth resistor R8 is simultaneously connected to the S The CL port and one end of the sixth capacitor C6, the other end of the ninth resistor R9 is connected to the SDA port of the module chip U2 and one end of the seventh capacitor C7, the other end of the eighth resistor R8 and the other end of the ninth resistor R9 are both grounded, the VDD port of the module chip U2 is simultaneously connected to one end of the eighth capacitor C8, one end of the ninth capacitor C9 and the current output end of the sixth power supply V6, the DP port of the module chip is connected to the DP port of the digital display board chip, and the DIG2 port of the module chip is connected to the DIG2 port of the digital display board chip.

[0042] Specifically, in the embodiment of the present scheme, the digital display control circuit S2 is provided with multiple resistors (an eighth resistor R8 and a ninth resistor R9) and multiple capacitors (a sixth capacitor C6 and a seventh capacitor C7), which are respectively connected in series at the SCL port and the SDA port of the module chip U2. The unstable current is filtered by the sixth capacitor C6 and the seventh capacitor C7 to prevent the electrical signal output from one side of the acquisition chip from being affected by the large current, thereby affecting the numerical display of the digital display board assembled on the other side, reducing the influence of the unstable current on the accurate display of the numerical value of the digital display board, and improving the overall stability of the detected numerical value.

[0043] Furthermore, in one embodiment, the DP port of the module chip is connected to the DP port of the digital display board chip, and the DIG2 port of the module chip is connected to the DIG2 port of the digital display board chip. The DP port and the DIG port of the module chip are used to output electrical signals to one side of the digital display board chip, so as to display the voltage data of the OCP board on the red display tube of the digital display board, so that various voltage data of the OCP board can be visualized.

[0044] Furthermore, the eighth capacitor C8 and the ninth capacitor C9 provided on the other side of the module chip U2 are used to filter the large current flowing to one side of the digital display board, thereby preventing the large current from interfering with the normal display of the digital display board and improving the accuracy and reliability of the display data of the digital display board.

[0045] See also Figure 3As shown in the figure, the first connection circuit S4 includes a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, a thirteenth resistor R13, a fourteenth resistor R14, a fifteenth resistor R15, a sixteenth resistor R16, a seventeenth resistor R17, an eighteenth resistor R18, and a seventh power supply V7. The SMCLK port of the connector chip U4 is simultaneously connected to one end of the twelfth resistor R12 and one end of the thirteenth resistor R13. The SMDAT port of the connector chip U4 is simultaneously connected to one end of the fourteenth resistor R14 and one end of the eleventh resistor R11. The SMRST port of the connector chip U4 is simultaneously connected to one end of the fifteenth resistor R15 and one end of the tenth resistor R10. The other end of the tenth resistor R10 and the eleventh resistor R11 are connected to each other. The other end of the twelfth resistor R12 and the other end of the twelfth resistor R12 are both connected to the current output end of the seventh power supply V7, the other end of the thirteenth resistor R13 is connected to a BMC-SCL port, the other end of the fourteenth resistor R14 is connected to a BMC-SDA port, the other end of the fifteenth resistor R15 is connected to a PLD-SMB port, the PERSTA port of the connector chip U4 is connected to one end of the sixteenth resistor R16, the PERST1 of the connector chip U4 is connected to one end of the seventeenth resistor R17, the seventeenth resistor R17 is connected to a RST-OCP3 port, the PRSNTB2 of the connector chip U4 is connected to an OCP-PRSNTB test port, and the OCP-PRSNTB test port is also connected to the VS port of the sampling circuit.

[0046] Specifically, in the embodiment of the present scheme, the connector circuit S3 is composed of a connector chip U4 and connection circuits (a first connection circuit S4 and a second connection circuit S5) arranged on both sides of the connector chip U4. The first connection circuit S4 is provided with a plurality of resistors (a tenth resistor R10, an eleventh resistor R111, a twelfth resistor R12, a thirteenth resistor R13, a fourteenth resistor R14, a fifteenth resistor R15, and a sixteenth resistor R16). By providing a plurality of resistors in series with the seventh power supply V7, it is possible to prevent the current from flowing into the second connection circuit S5 from being too large, thereby affecting the normal voltage supply of the OCP board and preventing the current from being too large. This affects the normal operation of the OCP board, and the PERSTA port of the connector chip U4 is connected to one end of the sixteenth resistor R16, the PERST1 port of the connector chip U4 is connected to one end of the seventeenth resistor R17, the seventeenth resistor R17 is connected to a RST-OCP3 port, and the PRSNTB2 port of the connector chip U4 is connected to an OCP-PRSNTB test port. This setting method, through the use of the first connection circuit S4 in conjunction with the second connection circuit S5, is convenient for voltage detection of the OCP board, thereby improving the overall voltage detection efficiency of the OCP board.

[0047] Furthermore, in one embodiment, the OCP-PRSNTB test port is also connected to the VS port of the sampling circuit, so as to transmit the data of the OCP board to the sampling circuit in the form of an electrical signal. In this setting, after the sampling circuit is connected to the connector, it can directly obtain the relevant voltage parameter information of the OCP board, which is convenient for users to test the OCP board and improves the overall efficiency of the test.

[0048] See also Figure 2 As shown in the figure, the second connection circuit S5 includes: an eighteenth resistor R18, an eighth power supply V8, a plurality of EDGE ports set in the connector chip U4 are simultaneously connected to a signal input port of an OCP board, and the PERST0 port of the connector chip U4 is connected to one end of the eighteenth resistor R18, and the other end of the eighteenth resistor R18 is connected to a RST-OCP port, and the current output end of the eighth power supply V8 is connected to the current port set on one side of the connector chip U4.

[0049] Specifically, in the embodiment of the present scheme, the eighth power supply V8 provided in the second connection circuit S5 outputs current to one end of the first connection circuit S4 for power supply, so that the current on both sides is relatively stable. The output voltages of the seventh power supply V7 and the eighth power supply V8 are both 3.3V, so as to prevent the excessive current from affecting the detection result of the OCP detection. In one embodiment, the OCP-PRSNTB test port provided on one side of the first connection circuit S4 is connected to the output end of a mainboard (not shown in the figure), and the mainboard is used to control the on-off current of the connector chip U4. The first connection circuit S4 and the second connection circuit S5 cooperate with each other to ensure stable power supply to the OCP board. After the OCP board is plugged in, the overall efficiency of the detection of the OCP board is improved, and the time required for the detection of the OCP board is greatly reduced.

[0050] See also Figure 5 As shown in the figure, one side of the connector chip U4 is also connected to a signal transmission circuit S6, and the signal transmission circuit S6 includes a nineteenth resistor R19, a twentieth resistor R20, and a ninth power supply V9. The PWRBRK0 port of the connector chip U4 is simultaneously connected to one end of the nineteenth resistor R19 and one end of the twentieth resistor R20, the other end of the nineteenth resistor R19 is connected to the current output end of the ninth power supply V9, the other end of the twentieth resistor R20 is connected to an OCP-PWRBRK0 port, and the PRSNTB3 port of the connector chip U4 is connected to an OCP-PRSNTVB3 port.

[0051] Specifically, one side of the connector chip U4 is also connected to a signal transmission circuit S6, which is used to transfer electrical signals. In one embodiment, the signal transmission circuit S6 is connected to a main board, which is provided with multiple connection ports. When the main class receives the detection data, it records the detection data, performs feedback control on the current after the operation is completed, and adjusts the test voltage to accurately test the voltage and other data of the OCP board, and transmits the feedback electrical signal to the connector chip U4 through the OCP-PWRBRK0 port, thereby testing the overall detection efficiency of the circuit.

[0052] See also Figure 2 As shown in the figure, the digital display board chip U3 is electrically connected to a digital display board (not numbered in the figure), and the digital display board is composed of a plurality of red display tubes, and the red display tubes form an "8"-shaped display unit, then a digital display board may include one or more display units.

[0053] Specifically, the chip is electrically connected to a digital display board, and the digital display board is composed of a plurality of red display tubes, and the red display tubes form an "8"-shaped display unit. Then a digital display board may include one or more display units. During the detection process, the digital display board directly displays the value of the current voltage of the OCP board. In the embodiment of the present scheme, the digital display board is used to display various detection data of the OCP board, and the voltage of the OCP board can be detected according to the user's instructions. In one embodiment, when it is necessary to detect the OCP board to be detected, it is only necessary to plug the corresponding wire into the corresponding connection end of the OCP board, so as to facilitate rapid detection of the OCP board.

[0054] Furthermore, in one embodiment, two connection points are set in the horizontal direction of the OCP board, and the two connection points are set on the same straight line. The position of the straight line is located at 1 / 3 of the entire OCP board. The wiring method of the first connection point is: connected by a long wire set on one side of the edge of the OCP board (the wire is bent horizontally), and the wiring method of the second connection point is: connected by a wire set on the horizontal midline of the OCP board (the wire is bent horizontally). The first connection point corresponds to the third connection hole on the detection device, and the second connection point corresponds to the first connection hole on the detection device. The OCP board is electrically connected point-to-point to quickly detect the OCP board and improve the overall detection efficiency.

[0055] See also Figure 1 As shown in the figure, the supply voltage of the first power supply V1 and the supply voltage of the second power supply V2 are both 12V.

[0056] Specifically, the output voltages of the first power supply V1 and the second power supply V2 are both 12V. Multiple power supplies are provided to power the acquisition chip. Both the first power supply V1 and the second power supply V2 are used to power the sampling circuit S1. This arrangement improves the reliability of the detection results of the acquisition chip on the OCP board by providing stable power supply to multiple ports of the acquisition chip.

[0057] See also Figure 1 As shown in the figure, the supply voltage of the third power supply V3 and the supply voltage of the fourth power supply V4 are both 3V.

[0058] Specifically, the output voltages of the third power supply V3 and the fourth power supply V4 are both 12V. Multiple power supplies are set to power the acquisition chip. The third power supply V3 and the fourth power supply V4 are both used to power the sampling circuit S1. This setting method improves the reliability of the detection results of the acquisition chip on the OCP board by stably powering multiple ports of the acquisition chip.

[0059] See also Figure 2As shown in the figure, the supply voltage of the fifth power supply V5 and the supply voltage of the sixth power supply V6 set in the digital display control circuit S2 are both 5V.

[0060] Specifically, the supply voltages of the fifth power supply V5 and the sixth power supply V6 set in the digital display control circuit S2 are both 5V, which are used to provide stable power supply to the module chip U2. By providing stable power supply to multiple ports of the module chip U2, while improving the overall connection stability of the circuit, the overall reliability of the module chip U2 in displaying the test results of the OCP board is also improved, which makes it convenient for users to record relevant data of the OCP board and realize the authenticity of the test results.

[0061] See also Figure 3 as well as Figure 4 , as shown in the figure, wherein the first connection circuit S4 and the second connection circuit S5 are both grounded.

[0062] Specifically, the first connection circuit S4 and the second connection circuit S5 are both grounded. In one embodiment, two rows of grounded wires are provided on both sides of the connector chip U4. The wires close to the first connection circuit S4 are connected to the connector chip U4 and a ground terminal at the same time to prevent the connector chip U4 from being damaged by excessive voltage, so that the digital display control circuit S2 connected to the connector chip U4 can quickly detect the voltage and current of the OCP board to be tested, thereby improving the reliability of the detection of the OCP board.

[0063] The utility model discloses an interface test circuit for an OCP board. The test circuit is used for testing the OCP board. The test circuit comprises: a sampling circuit, a digital display control circuit, and a connector circuit. The connector circuit comprises: a connector chip and a first connection circuit and a second connection circuit electrically connected to the connector chip. The digital display control circuit comprises a module chip and a digital display board chip electrically connected to the module chip. The sampling circuit comprises a sampling chip. The sampling chip in the sampling circuit and each resistor connected to the sampling chip cooperate to detect a batch of OCP boards. The digital display board provided by the digital display control circuit is then used for display, so that users can conveniently perform visual operation on the data information of the OCP board. Meanwhile, the overall reliability of the module chip displaying the detection result of the OCP board is improved, so that users can conveniently record the relevant data of the OCP board, thereby quickly detecting the OCP board.

[0064] The above is only a specific implementation of the utility model, but the protection scope of the utility model is not limited thereto. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed by the utility model, and these modifications or replacements should be included in the protection scope of the utility model. Therefore, the protection scope of the utility model should be based on the protection scope of the claims.

Claims

1. An interface test circuit for an OCP board, characterized in that: The test circuit is used to test the OCP board, and the test circuit includes: a sampling circuit, a digital display control circuit, and a connector circuit. The connector circuit includes: a connector chip and a first connection circuit and a second connection circuit electrically connected to the connector chip. One side of the first connection circuit is also connected to a main board. The digital display control circuit includes a module chip and a digital display board chip electrically connected to the module chip. The sampling circuit includes a sampling chip. The sampling circuit includes: a sampling chip, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, a first power supply, a second power supply, a third power supply, and a fourth power supply, wherein a current output end of the first power supply is simultaneously connected to one end of the first capacitor, one end of the second capacitor, one end of the first resistor, and one end of the second resistor, the other end of the first capacitor and the other end of the second capacitor are both grounded, the other end of the first resistor is simultaneously connected to the current output end of the second power supply, one end of the fourth capacitor, one end of the third resistor, an IN-P port of the sampling chip, and a VBUS port of the sampling chip, the other end of the fourth capacitor is grounded, and the other end of the second resistor is connected to the IN-N port of the sampling chip. The third resistor is arranged in parallel at one side of the first resistor, the ground end of the sampling chip is grounded, the third power supply is connected to the VS port of the sampling chip and one end of the fifth capacitor, the other end of the fifth capacitor is grounded, the current output end of the fourth power supply is connected to one end of the fourth resistor, the other end of the fourth resistor is connected to the A1 port of the sampling chip, the A0 port of the sampling chip is connected to one end of the fifth resistor, the other end of the fifth resistor is grounded, the SDA port of the sampling chip is connected to one end of the sixth resistor, the other end of the sixth resistor is connected to the SDA port set in the module chip of the digital display control circuit, the SCL port of the sampling chip is connected to one end of the seventh resistor, the other end of the seventh resistor is connected to the SCL port set in the module chip of the digital display control circuit, and the GND port of the sampling chip is grounded; After the module chip provided in the sampling circuit is electrically connected to the digital display control circuit, the display provided in the digital display control circuit can display the current current value.

2. The interface test circuit for an OCP board according to claim 1, characterized in that: The digital display control circuit includes: a module chip, an eighth resistor, a ninth resistor, a sixth capacitor, a seventh capacitor, an eighth capacitor, a ninth capacitor, a fifth power supply, and a sixth power supply. The SCL port and the SDA port set on one side of the sampling circuit are respectively connected to the SCL port and the SDA port set on the module chip. The current output end of the fifth power supply is simultaneously connected to one end of the eighth resistor and one end of the ninth resistor. The other end of the eighth resistor is simultaneously connected to the SCL port of the module chip and one end of the sixth capacitor. The other end of the ninth resistor is connected to the SDA port of the module chip and one end of the seventh capacitor. The other end of the eighth resistor and the other end of the ninth resistor are both grounded. The VDD port of the module chip is simultaneously connected to one end of the eighth capacitor, one end of the ninth capacitor, and the current output end of the sixth power supply. The DP port of the module chip is connected to the DP port of the digital display board chip. The DIG2 port of the module chip is connected to the DIG2 port of the digital display board chip.

3. The interface test circuit for an OCP board according to claim 1, characterized in that: The first connection circuit includes a tenth resistor, an eleventh resistor, a twelfth resistor, a thirteenth resistor, a fourteenth resistor, a fifteenth resistor, a sixteenth resistor, a seventeenth resistor, an eighteenth resistor, and a seventh power supply, the SMCLK port of the connector chip is simultaneously connected to one end of the twelfth resistor and one end of the thirteenth resistor, the SMDAT port of the connector chip is simultaneously connected to one end of the fourteenth resistor and one end of the eleventh resistor, the SMRST port of the connector chip is simultaneously connected to one end of the fifteenth resistor and one end of the tenth resistor, the other end of the tenth resistor, the other end of the eleventh resistor, and the other end of the twelfth resistor are all connected to the seventh power supply. The current output end of the seven power supplies, the other end of the thirteenth resistor is connected to a BMC-SCL port, the other end of the fourteenth resistor is connected to a BMC-SDA port, the other end of the fifteenth resistor is connected to a PLD-SMB port, the PERSTA port of the connector chip is connected to one end of the sixteenth resistor, the PERST1 port of the connector chip is connected to one end of the seventeenth resistor, the seventeenth resistor is connected to a RST-OCP3 port, the PRSNTB2 port of the connector chip is connected to an OCP-PRSNTB test port, and the OCP-PRSNTB test port is also connected to the VS port of the sampling circuit.

4. The interface test circuit for an OCP board according to claim 1, characterized in that: The second connection circuit includes: an eighteenth resistor and an eighth power supply. The multiple EDGE ports set in the connector chip are simultaneously connected to the signal input port of an OCP board, and the PERST0 port of the connector chip is connected to one end of the eighteenth resistor, and the other end of the eighteenth resistor is connected to a RST-OCP port, and the current output end of the eighth power supply is connected to the current port set on one side of the connector chip.

5. The interface test circuit for an OCP board according to claim 1, characterized in that: One side of the connector chip is also connected to a signal transmission circuit, which includes a nineteenth resistor, a twentieth resistor, and a ninth power supply. The PWRBRK0 port of the connector chip is simultaneously connected to one end of the nineteenth resistor and one end of the twentieth resistor, the other end of the nineteenth resistor is connected to the current output end of the ninth power supply, the other end of the twentieth resistor is connected to an OCP-PWRBRK0 port, and the PRSNTB3 port of the connector chip is connected to an OCP-PRSNTVB3 port.

6. The interface test circuit for an OCP board according to claim 1, characterized in that: The digital display board chip is electrically connected to a digital display board, and the digital display board is composed of a plurality of red display tubes, and the red display tubes form an "8"-shaped display unit, so a digital display board may include one or more display units.

7. The interface test circuit for an OCP board according to claim 2, characterized in that: The supply voltage of the first power supply and the supply voltage of the second power supply are both 12V.

8. The interface test circuit for an OCP board according to claim 2, characterized in that: The supply voltage of the third power supply and the supply voltage of the fourth power supply are both 3V.

9. The interface test circuit for an OCP board according to claim 2, characterized in that: The supply voltage of the fifth power supply and the supply voltage of the sixth power supply provided in the digital display control circuit are both 5V.

10. The interface test circuit for an OCP board according to claim 1, characterized in that: The first connection circuit and the second connection circuit are both grounded.

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