Quantum device and superconducting quantum chip
By designing a Josephson junction with a shape of a single-character junction in a superconducting quantum chip and covering the superconducting metal layer on its top surface, leaving gaps to reduce dielectric loss, the problem of shortening the qubit relaxation time is solved, and the problem of improving the Chip performance.
Patent Information
- Application Number
- CN202420627247.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-03-28
- Publication Date
- 2025-01-14
- Estimated Expiration
- 2034-03-28
AI Technical Summary
In existing superconducting quantum chips, the relaxation time of qubits is greatly reduced due to dielectric loss, which in turn reduces the performance of qubits.
Design a quantum device, including forming a Josephson junction in a shape of a junction on the substrate, and covering its top surface with a superconducting metal layer, leaving a gap between the superconducting metal layer and the side surface of the Josephson junction, to reduce dielectric loss.
By reducing dielectric loss, the performance of the Josephson junction and the quality of superconducting quantum chips are improved, and the relaxation time of the qubit is extended.
Smart Images
Figure CN222356887U_ABST
Abstract
Description
Technical Field
[0001] This application belongs to the technical field of quantum bit chips, and in particular relates to a quantum device and a superconducting quantum chip. Background Technology
[0002] A quantum computer is a physical device that performs high-speed mathematical and logical operations, stores and processes quantum information according to the laws of quantum mechanics. A superconducting quantum chip, as the core structure for performing quantum computing, integrates at least one qubit, which is a physical structure formed on a selected substrate using semiconductor fabrication processes. In reality, the energy in a quantum chip dissipates along the material medium of the components surrounding the qubit and / or the air around the qubit, significantly reducing the relaxation time of the qubit and thus degrading its performance.
[0003] The dissipation of energy on a quantum chip along the material medium of the components surrounding the qubit and / or the air surrounding the qubit is called dielectric loss. Dielectric loss is the main factor affecting the relaxation time of the qubit, and dielectric loss is related to the structure of the quantum chip.
[0004] Therefore, how to reduce dielectric loss in quantum chip structures and improve the relaxation time of qubits are urgent problems to be solved in the design of superconducting quantum chips. Utility Model Content
[0005] The purpose of this application is to provide a quantum device and a superconducting quantum chip to solve the problem in the prior art where the relaxation time of the quantum bit is greatly reduced due to dielectric loss, thereby reducing the performance of the quantum bit. This application can improve the problem of large dielectric loss between the superconducting layer and the Josephson junction, thereby improving the performance of the Josephson junction.
[0006] To solve the above-mentioned technical problems, this utility model provides a quantum device, comprising:
[0007] Substrate;
[0008] A Josephson junction in the shape of a straight line is formed on the surface of the substrate and disposed along a first direction. The Josephson junction has a top surface facing away from the substrate, a front surface perpendicular to the first direction, and a side surface parallel to the first direction and perpendicular to the substrate.
[0009] A superconducting metal layer is formed on the surface of the substrate having the Josephson junction;
[0010] The superconducting metal layer contacts and covers the top surface of the Josephson junction, exposes the front surface in a first direction, and has a gap between it and the side surface.
[0011] Preferably, in the first direction, a portion of the superconducting metal layer has the same length as the Josephson junction, and the portion of the superconducting metal layer completely covers the surface of the Josephson junction facing away from the substrate.
[0012] Preferably, the quantum device further includes one or more of a resonant cavity, a signal line, and a capacitor, wherein the resonant cavity, the signal line, and the capacitor are formed in a region of the superconducting metal layer away from the Josephson junction.
[0013] Preferably, the superconducting metal layer is made of niobium.
[0014] Preferably, the Josephson junction comprises a first superconducting layer, a second superconducting layer, a barrier layer, a third superconducting layer, and a fourth superconducting layer stacked sequentially.
[0015] The surface of the first superconducting layer facing away from the second superconducting layer is in contact with the substrate, and the surface of the fourth superconducting layer facing away from the third superconducting layer is in contact with the superconducting metal layer.
[0016] Preferably, the materials of the first superconducting layer and the fourth superconducting layer are niobium.
[0017] Preferably, the second superconducting layer and the third superconducting layer are made of aluminum.
[0018] Preferably, in the direction perpendicular to the substrate, the second superconducting layer, the barrier layer, the third superconducting layer, and the fourth superconducting layer completely overlap in sequence;
[0019] In the first direction, the length of the first superconducting layer is not less than the length of the second superconducting layer;
[0020] The vertical projections of the second superconducting layer, the barrier layer, the third superconducting layer, and the fourth superconducting layer onto the substrate are located within the edge of the vertical projection of the first superconducting layer onto the substrate.
[0021] Preferably, the substrate is a sapphire substrate or a silicon substrate.
[0022] This application also provides a superconducting quantum chip, comprising:
[0023] The quantum devices described in any of the preceding claims; and
[0024] A signal port is fabricated coplanarly with the Josephson junction on the periphery of the substrate, and the signal port is used for telecommunication connection between the quantum device and external circuitry.
[0025] The difference from existing technologies lies in that this application forms a Josephson junction with a line-shaped structure and a superconducting metal layer on a substrate, wherein the superconducting metal layer covers the Josephson junction and is in contact with the top surface of the Josephson junction. Furthermore, the superconducting metal layer is positioned to expose the front surface of the Josephson junction, and a gap is left between it and the side surface of the Josephson junction to mitigate the problem of high dielectric loss between the superconducting metal layer and the Josephson junction, thereby improving the performance of the Josephson junction and the quality of the superconducting quantum chip. Attached Figure Description
[0026] Figure 1 This is a schematic diagram of the structure of the quantum device provided in the embodiments of this application;
[0027] Figure 2 A schematic diagram of the niobium-based Josephson junction located on a substrate, provided in an embodiment of this application;
[0028] Figure 3 This is a schematic diagram of the positioning surface of a niobium-based Josephson junction provided in an embodiment of this application.
[0029] Explanation of reference numerals in the attached figures: 1-substrate, 2-Josephson junction, 21-first superconducting layer, 22-second superconducting layer, 23-barrier layer, 24-third superconducting layer, 25-fourth superconducting layer, 3-superconducting metal layer. Detailed Implementation
[0030] The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.
[0031] In the description of this application, it should be understood that the terms "center", "upper", "lower", "left", "right", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.
[0032] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.
[0033] Currently, a niobium-based Josephson junction is being developed and fabricated. Direct detectors based on niobium-based Josephson junctions are attracting the attention of relevant technical personnel. The requirements for superconducting Josephson junctions used for direct detectors include at least a high critical temperature, low leakage current, strong noise immunity, and a certain manufacturing yield.
[0034] The novel niobium-based Josephson junction differs from the traditional Josephson junction in that it consists of a five-layer stacked structure, including materials such as aluminum and niobium. The fabrication of the novel niobium-based Josephson junction employs techniques such as exposure and development, high-vacuum evaporation, and etching to obtain a dimensionally controllable and stable niobium-based Josephson junction.
[0035] In the testing and use of superconducting quantum chips, to ensure that the superconducting parameters—critical current, critical magnetic field, and superconducting band gap—remain essentially constant, the operating temperature of superconducting quantum devices (superconducting quantum fundamental circuits, superconducting qubits, etc.) is typically limited to Tc*2 / 3. For superconducting quantum fundamental circuits, the higher the critical temperature Tc, the wider the operating range of the circuit.
[0036] Among current mainstream superconducting quantum chip technologies, Al-based superconducting quantum circuits are the most widely used. However, for experimental purposes, Al's critical temperature (Tc) is relatively low, only about 1.2K, which significantly limits the operating temperature range of the basic superconducting quantum circuits. Therefore, using niobium-based materials as the large-structure layer of superconducting quantum chips, i.e., using niobium-based materials as the wiring layer, is necessary not only to etch the area required for the Josephson junction but also to etch other components such as resonant cavities, capacitors, and transmission lines. Because niobium has a higher critical temperature (approximately 9K), the temperature range for testing is wider than when using aluminum as the large-structure material, resulting in increased noise tolerance and reduced sensitivity of the superconducting quantum chip.
[0037] The inventors of this application have discovered that when niobium-based thin films are used as the macrostructure layer of superconducting quantum chips, the oxide formed by the oxidation of the niobium-based thin film exhibits higher dielectric loss compared to aluminum-based thin film oxides. This negatively impacts the performance of the superconducting quantum chip and reduces its quality. Therefore, when using niobium-based thin films as the macrostructure layer, reducing the dielectric loss in the quantum chip structure and improving the relaxation time of the qubits are pressing issues that need to be addressed in the design of superconducting quantum chips.
[0038] Please refer to Figure 1 and Figure 3 This utility model provides a quantum device, including: a substrate 1, a Josephson junction 2 formed coplanarly on the surface of the substrate 1, and a superconducting metal layer 3.
[0039] Among them, the Josephson junction 2 is in the shape of a straight junction. For a Josephson junction with a straight junction shape, its two superconducting layers can be manufactured by extending in the same direction, and the direction in which the straight Josephson junction is manufactured is defined as the first direction, which is used as the positioning reference direction for subsequent devices. The straight Josephson junction 2 can also be defined to have a top surface away from the substrate 1, a front surface perpendicular to the first direction, and a side surface parallel to the first direction and perpendicular to the substrate 1. The superconducting metal layer 3, which is a large structure thin film, is formed on the surface of the substrate 1 with the Josephson junction 2 and is in partial contact with the surface of the substrate 1.
[0040] It is worth noting that, according to the quantum device described above, the superconducting metal layer 3 needs to cover the top surface of the Josephson junction 2 in a contact manner, and the Josephson junction 2 needs to expose the positive surface in the first direction through etching and other methods. Most importantly, there is a gap between the superconducting metal layer 3 and the side surface of the Josephson junction 2.
[0041] Regarding the problem of reducing dielectric loss and improving relaxation time of qubits in the above-mentioned quantum device, the inventors of this application propose the following: The superconducting metal layer 3, as a large-structure thin film, has a gap between itself and the Josephson junction 2, and is in contact with the top surface of the Josephson junction 2. This allows the superconducting metal layer 3 to be partially suspended by the Josephson junction 2. In this quantum device structure, the medium between the superconducting metal layer 3 and the Josephson junction 2 is air, and the energy loss from air is very small. If there were no gap between the superconducting metal layer 3 and the Josephson junction 2, and they were directly connected, there would be an "interface" in the middle, and the energy loss at this interface would be much greater than the energy loss from air. Therefore, the quantum device provided by this invention can reduce dielectric loss and improve relaxation time of qubits while using a niobium-based large structure to increase the range of test temperatures.
[0042] In one embodiment of this application, in a first direction, the length of a portion of the superconducting metal layer 3 is consistent with the length of the Josephson junction 2, and the portion of the superconducting metal layer 3 completely covers the surface of the Josephson junction 2 away from the substrate 1.
[0043] For the aforementioned quantum devices, the Josephson junction 2 is typically fabricated entirely on the surface of the substrate 1, and then etched to a suitable length. A superconducting metal layer 3 is then deposited on the surface of the substrate 1 with the Josephson junction 2 using methods such as magnetron sputtering. After the initial deposition, the superconducting metal layer 3 may completely cover the Josephson junction 2. Subsequently, the superconducting metal layer 3, after the initial deposition, can be etched as needed to partially cover the surface of the Josephson junction 2 away from the substrate 1. Furthermore, in the first direction, this portion of the superconducting metal layer 3 has the same length as the Josephson junction 2, just enough to cover the top surface of the Josephson junction 2. This can be understood as follows: in the first direction, the superconducting metal layer 3 is etched with two openings, exposing the front surface of the Josephson junction 2 through these two openings.
[0044] In one embodiment of this application, the quantum device can be part of a superconducting quantum chip. Therefore, the quantum device may further include a resonant cavity, and / or signal lines, and / or capacitors. Notably, the resonant cavity, and / or signal lines, and / or capacitors are fabricated in the region of the superconducting metal layer 3 away from the Josephson junction 2, and are connected to the Josephson junction 2 via appropriate means such as coupling, electrical connection, and inductance. When the quantum device is part of a superconducting quantum chip, other quantum elements may also be formed, not limited to the examples described above.
[0045] In one embodiment of this application, the superconducting metal layer 3 is made of niobium. As previously stated, when niobium is used as the large-scale structure (wiring layer) of a quantum device, the temperature range suitable for testing is wider than when Al is used. Currently, when Al is used as the large-scale structure, the cryogenic testing temperature range is 10 mK-50 mK, while aluminum has a critical temperature of 1.2 K. Testing with aluminum cannot be performed at temperatures above 200 mK, as rising too close to the critical temperature introduces thermal noise, increasing testing risks. When niobium, a superconducting material, is used as the large-scale structure, the cryogenic testing temperature can be maintained between 50 mK and 200 mK without interference from thermal noise. Therefore, choosing niobium as the material for the superconducting metal layer 3 is necessary.
[0046] Please refer to Figure 2 Josephson junction 2 includes a first superconducting layer 21, a second superconducting layer 22, a barrier layer 23, a third superconducting layer 24, and a fourth superconducting layer 25 stacked in one step; wherein, the surface of the first superconducting layer 21 facing away from the second superconducting layer 22 is in contact with the substrate 1, and the surface of the fourth superconducting layer 25 facing away from the third superconducting layer 24 is in contact with the superconducting metal layer 3.
[0047] Specifically, the materials of the first superconducting layer 21 and the fourth superconducting layer 25 are niobium.
[0048] The second superconducting layer 22 and the third superconducting layer 24 are made of aluminum.
[0049] Furthermore, in the direction perpendicular to the substrate 1, the second superconducting layer 22, the barrier layer 23, the third superconducting layer 24, and the fourth superconducting layer 25 completely overlap at once; and in the first direction, the length of the first superconducting layer 21 is not less than the length of the second superconducting layer 22; the vertical projections of the second superconducting layer 22, the barrier layer 23, the third superconducting layer 24, and the fourth superconducting layer 25 onto the surface of the substrate 1 are located within the edge of the vertical projection of the first superconducting layer 21 onto the substrate 1.
[0050] The aforementioned Josephson junction 2 structure is a niobium-based Josephson junction 2, with the following structural distribution: Nb bottom electrode -- Al-AlOx-Al layer -- Nb top electrode. Specifically, the Nb bottom electrode is the first superconducting layer 21, the Al-AlOx-Al layers are the second superconducting layer 22, the barrier layer 23, and the third superconducting layer 24, respectively, and the Nb top electrode is the fourth superconducting layer 25.
[0051] The manufacturing steps for niobium-based Josephson junction 2 are as follows:
[0052] S1: Defines an electrode region on substrate 1;
[0053] S2: An Nb bottom electrode is formed in the electrode region;
[0054] S3: An Al-AlOx-Al layer is formed on the Nb bottom electrode;
[0055] S4: A Nb top electrode is formed on the Al-AlOx-Al layer;
[0056] S5: Etching to obtain niobium-based Josephson junction 2.
[0057] In the direction perpendicular to substrate 1, the Nb top electrode is the same size as and completely overlaps with the Al-AlOx-Al layer, while the size of the Nb bottom electrode is set to be at least the same as the size of the Al-AlOx-Al layer, and the Al-AlOx-Al layer is completely stacked on the surface region of the Nb bottom electrode away from the substrate.
[0058] In one embodiment of this application, substrate 1 is a sapphire substrate or a silicon substrate. As is well known, substrate 1, as the superconducting bottom material, mainly plays the roles of physical support, thermal conduction, and electrical conduction. The material of substrate 1 can be silicon substrate, sapphire substrate, etc., and is not limited to the above example; it can be selected according to actual needs.
[0059] This application also provides a superconducting quantum chip, comprising: the aforementioned quantum device; and a signal port fabricated coplanarly with the Josephson junction 2 on the periphery of the substrate 1, the signal port being used for telecommunication connection between the quantum device and external circuitry. The signal port enables signal connection between the superconducting quantum chip and external circuitry, and / or instrument structures, and / or processors and / or displays, etc., to achieve signal exchange between the superconducting quantum chip and other devices; further explanation is not provided here.
[0060] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," or "specific example," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.
[0061] The above description, based on the embodiments shown in the drawings, details the structure, features, and effects of this application. The above description is only a preferred embodiment of this application, but this application does not limit the scope of implementation to what is shown in the drawings. Any changes made in accordance with the concept of this application, or modifications to equivalent embodiments, that do not exceed the spirit covered by the specification and drawings, should be within the protection scope of this application.
Claims
1. A quantum device, characterized in that: include: Substrate (1); A Josephson junction (2) in the shape of an inscribed junction is formed on the surface of the substrate (1) and arranged along a first direction, wherein the Josephson junction (2) has a top surface facing away from the substrate (1), a front surface perpendicular to the first direction, and a side surface parallel to the first direction and perpendicular to the substrate (1); A superconducting metal layer (3) formed on the surface of the substrate (1) having the Josephson junction (2); The superconducting metal layer (3) covers the top surface of the Josephson junction (2) in a contact manner, leaks out of the front surface in a first direction, and has a gap between the superconducting metal layer (3) and the side surface.
2. The quantum device according to claim 1, characterized in that In the first direction, the length of a portion of the superconducting metal layer (3) is consistent with the length of the Josephson junction (2), and the portion of the superconducting metal layer (3) completely covers the surface of the Josephson junction (2) facing away from the substrate (1).
3. The quantum device according to claim 1, characterized in that The quantum device further comprises one or more of a resonant cavity, a signal line and a capacitor, wherein the resonant cavity, the signal line and the capacitor are formed in a region where the superconducting metal layer (3) leaves the Josephson junction (2).
4. The quantum device according to any one of claims 1 to 3, characterized in that: The material of the superconducting metal layer (3) is niobium.
5. The quantum device according to claim 1, characterized in that The Josephson junction (2) comprises a first superconducting layer (21), a second superconducting layer (22), a barrier layer (23), a third superconducting layer (24) and a fourth superconducting layer (25) which are stacked in sequence; The surface of the first superconducting layer (21) facing away from the second superconducting layer (22) contacts the substrate (1), and the surface of the fourth superconducting layer (25) facing away from the third superconducting layer (24) contacts the superconducting metal layer (3).
6. The quantum device according to claim 5, characterized in that The material of the first superconducting layer (21) and the fourth superconducting layer (25) is niobium.
7. The quantum device according to claim 5, characterized in that The material of the second superconducting layer (22) and the third superconducting layer (24) is aluminum.
8. The quantum device according to claim 5, 6 or 7, characterized in that: In a direction perpendicular to the substrate (1), the second superconducting layer (22), the barrier layer (23), the third superconducting layer (24) and the fourth superconducting layer (25) completely overlap in sequence; In the first direction, the length of the first superconducting layer (21) is not less than the length of the second superconducting layer (22); The vertical projections of the second superconducting layer (22), the barrier layer (23), the third superconducting layer (24) and the fourth superconducting layer (25) on the substrate (1) are located within the edge of the vertical projection of the first superconducting layer (21) on the substrate (1).
9. The quantum device according to claim 1, characterized in that: The substrate (1) is a sapphire substrate (1) or a silicon substrate (1).
10. A superconducting quantum chip, characterized in that: include: The quantum device according to any one of claims 1 to 9; as well as A signal port is manufactured on the periphery of the substrate (1) coplanar with the Josephson junction (2), and the signal port is used for telecommunication connection between the quantum device and an external circuit.