High-sensitivity high-resolution flow chip

Abstract

The utility model relates to a high-sensitivity high-resolution flow chip. The device comprises a substrate, and the back surface of the substrate is provided with a back surface release cavity. The supporting structure layer is arranged on the substrate; the first insulating layer is arranged on the supporting structure layer; the upstream temperature measuring element thermopiles, the central heat source and the downstream temperature measuring element thermopiles are respectively arranged on the first insulating layer, and the multiple groups of upstream temperature measuring element thermopiles and the multiple groups of downstream temperature measuring element thermopiles are respectively distributed side by side along the longitudinal direction of the chip; and front release isolation through holes are formed between thermopiles of the adjacent upstream temperature measurement elements and between thermopiles of the adjacent downstream temperature measurement elements, and the front release isolation through holes extend to the back release cavity. According to the utility model, the sensitivity of the temperature measuring element to heat is improved and the power consumption of the chip is reduced.

Description

Technical Field

[0001] The utility model relates to the technical field of flow sensors, in particular to a high-sensitivity and high-resolution flow chip. Background Art

[0002] Thermal flow sensor is a device that uses thermal sensing effect for measurement, and is suitable for measuring the flow of gas and liquid. Its main components include hot wire sensor, compensation circuit, temperature compensation circuit and operational amplifier. Due to its advantages of high accuracy, fast response speed and no influence from medium, it is widely used in industrial automation, air conditioning, automobile industry, medical equipment, robots and other fields.

[0003] Existing flow chips have high power consumption, which not only increases the cost of use, but also limits their application in certain scenarios where power is limited or low power consumption is required. In addition, flow chips have certain limitations in measurement accuracy and resolution, which affects their use in some high-precision applications. Summary of the invention

[0004] To this end, the utility model provides a high-sensitivity and high-resolution flow chip, which improves the sensitivity of the temperature measuring element to heat and reduces the power consumption of the chip.

[0005] In order to solve the above technical problems, the utility model provides a high-sensitivity and high-resolution flow chip, comprising:

[0006] A substrate, wherein a back side release cavity is provided on the back side of the substrate;

[0007] A supporting structure layer is disposed on the substrate;

[0008] A first insulating layer, disposed on the supporting structure layer;

[0009] The upstream temperature measuring element thermopile, the central heat source and the downstream temperature measuring element thermopile are respectively arranged on the first insulating layer, wherein a plurality of groups of the upstream temperature measuring element thermopile and a plurality of groups of the downstream temperature measuring element thermopile are respectively arranged side by side along the longitudinal direction of the chip;

[0010] Among them, there are front release isolation through holes between adjacent upstream temperature measuring element thermoelectric piles and between adjacent downstream temperature measuring element thermoelectric piles, and the front release isolation through holes extend to the back release cavity.

[0011] In one embodiment of the present invention, the upstream temperature measuring element thermopile, the central heat source and the downstream temperature measuring element thermopile are covered with a passivation layer.

[0012] In one implementation of the present utility model, the front release isolation through hole is an inverted cone structure.

[0013] In one implementation of the utility model, the back release cavity is a trapezoidal structure.

[0014] In one embodiment of the utility model, the upstream temperature measuring element thermopile comprises an upstream temperature measuring element thermopile lower layer thermocouple and an upstream temperature measuring element thermopile upper layer thermocouple;

[0015] The downstream temperature measuring element thermopile comprises a downstream temperature measuring element thermopile lower layer thermocouple and a downstream temperature measuring element thermopile upper layer thermocouple;

[0016] The upstream temperature measuring element thermopile lower layer thermocouple and the downstream temperature measuring element thermopile lower layer thermocouple are covered with a second insulating layer;

[0017] The upper thermocouple of the upstream temperature measuring element thermopile and the upper thermocouple of the downstream temperature measuring element thermopile are covered with a third insulating layer.

[0018] In one embodiment of the utility model, it also includes a connecting wire structure that runs through the third insulating layer;

[0019] The connecting wire structure includes an upstream cold end connecting wire connected to the lower thermocouple of the upstream temperature measuring element thermopile, an upstream hot end connecting wire connected between the lower thermocouple of the upstream temperature measuring element thermopile and the upper thermocouple of the upstream temperature measuring element thermopile, a downstream cold end connecting wire connected to the lower thermocouple of the downstream temperature measuring element thermopile, a downstream hot end connecting wire connected between the lower thermocouple of the downstream temperature measuring element thermopile and the upper thermocouple of the downstream temperature measuring element thermopile, and a central heat source wire connected to the central heat source.

[0020] In one embodiment of the present invention, the upstream temperature measuring element thermopile and the downstream temperature measuring element thermopile are symmetrically arranged along the longitudinal symmetrical section of the chip.

[0021] In one embodiment of the present invention, the support structure layer includes a first silicon oxide support layer, a silicon nitride support layer and a second silicon oxide support layer which are sequentially arranged on the surface of the substrate.

[0022] In one embodiment of the utility model, a passivation layer is provided on the surface of the third insulating layer, and the front release isolation through hole sequentially penetrates the passivation layer, the third insulating layer, the second insulating layer, the first insulating layer, the second silicon oxide support layer, the silicon nitride support layer and the first silicon oxide support layer.

[0023] The above technical solution of the utility model has the following advantages compared with the prior art:

[0024] The high-sensitivity and high-resolution flow chip described in the utility model forms an isolation through hole for front release and a back release cavity to form an isolation through hole in the insulation layer between the adjacent thermocouple pairs of the temperature measuring element, thereby isolating the back heat transfer channel and improving the sensitivity of the temperature measuring element to heat. This allows the central heat source to be driven by only a very small voltage, and the temperature measuring element can sense the heat change, thereby improving the overall resolution of the chip and reducing the power consumption of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to make the content of the utility model more clearly understood, the utility model is further described in detail below based on specific embodiments of the utility model in combination with the accompanying drawings.

[0026] Figure 1 It is a schematic cross-sectional view of the chip of the utility model.

[0027] Figure 2 It is a schematic cross-sectional view of the chip of the utility model from another direction.

[0028] Figure 3 It is a schematic diagram of a thermopile temperature measuring element and a front release isolation through hole of the utility model.

[0029] Description of the Figures in the Specification:

[0030] 1. Substrate;

[0031] 2. A first silicon oxide support layer;

[0032] 3. Silicon nitride support layer;

[0033] 4. A second silicon oxide support layer;

[0034] 5a, the thermocouple of the lower layer of the thermopile of the upstream temperature measuring element; 5b, the thermocouple of the lower layer of the thermopile of the downstream temperature measuring element;

[0035] 6. Central heat source;

[0036] 7a, a first insulating layer; 7b, a second insulating layer; 7c, a third insulating layer;

[0037] 8a, upper thermocouple of the thermopile of the upstream temperature measuring element; 8b, upper thermocouple of the thermopile of the downstream temperature measuring element;

[0038] 91. Upstream cold end connecting wire; 92. Upstream hot end connecting wire; 93. Central heat source wire; 94. Downstream cold end connecting wire; 95. Downstream hot end connecting wire;

[0039] 10. Passivation layer;

[0040] 11. Front release isolation through hole;

[0041] 12. Back release cavity. DETAILED DESCRIPTION

[0042] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments so that those skilled in the art can better understand the present invention and implement it, but the embodiments are not intended to limit the present invention.

[0043] Reference Figures 1 to 3 As shown, a high-sensitivity and high-resolution flow chip of the utility model comprises:

[0044] A substrate 1, wherein a back side release cavity 12 is provided on the back side of the substrate 1;

[0045] A supporting structure layer, disposed on the substrate 1;

[0046] A first insulating layer 7a, disposed on the supporting structure layer;

[0047] The upstream temperature measuring element thermopile, the central heat source 6 and the downstream temperature measuring element thermopile are respectively arranged on the first insulating layer 7a, wherein a plurality of groups of the upstream temperature measuring element thermopile and a plurality of groups of the downstream temperature measuring element thermopile are respectively arranged side by side along the longitudinal direction of the chip (refer to Figure 2 shown);

[0048] Among them, there are front release isolation through holes 11 between adjacent upstream temperature measuring element thermoelectric piles and between adjacent downstream temperature measuring element thermoelectric piles, and the front release isolation through holes 11 extend to the back release cavity 12.

[0049] Specifically, the upstream temperature measuring element thermopile, the central heat source 6 and the downstream temperature measuring element thermopile are covered with a passivation layer 10 .

[0050] Specifically, the front release isolation through hole 11 is in an inverted cone structure; the back release cavity 12 is in a trapezoidal structure. Since the back of the substrate 1 is anisotropically dry-etched to form an inverted trapezoid, and the front is wet-etched, the aspect ratio can be made relatively large, but the front release isolation through hole 11 is small, so the deeper it is, the more difficult it is to etch, and finally an inverted cone structure is formed.

[0051] Specifically, the upstream temperature measuring element thermopile includes an upstream temperature measuring element thermopile lower layer thermocouple 5a and an upstream temperature measuring element thermopile upper layer thermocouple 8a;

[0052] The downstream temperature measuring element thermopile comprises a downstream temperature measuring element thermopile lower layer thermocouple 5b and a downstream temperature measuring element thermopile upper layer thermocouple 8b;

[0053] The upstream temperature measuring element thermopile lower layer thermocouple 5a and the downstream temperature measuring element thermopile lower layer thermocouple 5b are covered with a second insulating layer 7b;

[0054] The upper thermocouple 8a of the upstream temperature measuring element thermopile and the upper thermocouple 8b of the downstream temperature measuring element thermopile are covered with a third insulating layer 7c;

[0055] The first to third insulating layers 7c are all made of silicon oxide.

[0056] Specifically, it also includes a connecting wire structure that runs through the third insulating layer 7c;

[0057] The connecting wire structure includes an upstream cold end connecting wire 91 connected to the lower thermocouple 5a of the upstream temperature measuring element thermopile, an upstream hot end connecting wire 92 connected between the lower thermocouple 5a of the upstream temperature measuring element thermopile and the upper thermocouple 8a of the upstream temperature measuring element thermopile, a downstream cold end connecting wire 94 connected to the lower thermocouple 5b of the downstream temperature measuring element thermopile, a downstream hot end connecting wire 95 connected between the lower thermocouple 5b of the downstream temperature measuring element thermopile and the upper thermocouple 8b of the downstream temperature measuring element thermopile, and a central heat source wire 93 connected to the central heat source 6.

[0058] Specifically, the upstream temperature measuring element thermopile and the downstream temperature measuring element thermopile are symmetrically arranged along the longitudinal symmetrical section of the chip.

[0059] Specifically, the support structure layer includes a first silicon oxide support layer 2, a silicon nitride support layer 3 and a second silicon oxide support layer 4 which are sequentially arranged on the surface of the substrate 1.

[0060] Specifically, a passivation layer 10 is disposed on the surface of the third insulating layer 7c to enhance the overall anti-pollution capability of the chip; wherein the passivation layer 10 is made of silicon nitride.

[0061] Specifically, the front release isolation through hole 11 sequentially penetrates the passivation layer 10, the third insulating layer 7c, the second insulating layer 7b, the first insulating layer 7a, the second silicon oxide support layer 4, the silicon nitride support layer 3 and the first silicon oxide support layer 2.

[0062] In this embodiment, refer to Figure 3 As shown, each group of thermopile temperature measuring elements includes four rows of upstream temperature measuring element thermopiles and corresponding four rows of downstream temperature measuring element thermopiles. In each group of thermopile temperature measuring elements, two adjacent groups of upstream temperature measuring element thermopiles and two adjacent groups of downstream temperature measuring element thermopiles are connected by wires.

[0063] After the temperature measuring element senses the temperature, it will transfer heat from the hot end to the cold end, forming the Seebeck effect and generating a thermoelectric potential between the hot and cold ends. That is, this part of heat conduction is necessary and is also one of the important factors that determine the sensitivity of the chip, because the greater the temperature difference between the hot and cold ends, the greater the thermoelectric potential, the greater the output signal, and the greater the sensitivity of the chip. However, in addition to transferring heat to the cold end, the hot end will also transfer heat to the left and right adjacent thermocouples and the lower insulating support layer. By preparing the front isolation release hole, the hot end can be prevented from transferring heat to the left and right adjacent thermocouples. At the same time, in conjunction with the back release cavity 12, the lower insulating support layer between each group of thermocouples of the thermopile temperature measuring element is directly completely carved open, thereby blocking the heat transfer channel from the hot end to the bottom insulating support layer. Therefore, after the direction of the unnecessary heat transfer channel is reduced, when the hot end conducts heat, there is only one heat transfer channel, which is to flow to the cold end, so the thermoelectric potential between the hot and cold ends will be higher, and the chip sensitivity will also be higher.

[0064] In summary, by bidirectional release etching on the front and back sides, the insulating layer between the adjacent thermocouple pairs of the temperature measuring element is formed into an isolation through hole, thereby isolating the back heat transfer channel and improving the sensitivity of the temperature measuring element to heat. This allows the central heat source 6 to be driven by only a very small voltage, and the temperature measuring element can sense the heat change, thereby improving the overall resolution of the chip and reducing the chip power consumption.

[0065] Finally, it should be noted that the above specific implementation methods are only used to illustrate the technical solution of the utility model rather than to limit it. Although the utility model has been described in detail with reference to examples, ordinary technicians in the field should understand that the technical solution of the utility model can be modified or replaced by equivalents without departing from the spirit and scope of the technical solution of the utility model, which should be included in the scope of the claims of the utility model.

Claims

1. A high-sensitivity and high-resolution flow chip, characterized in that: include: A substrate (1), wherein a back side release cavity (12) is provided on the back side of the substrate (1); A supporting structure layer, arranged on the substrate (1); A first insulating layer (7a) is arranged on the supporting structure layer; The upstream temperature measuring element thermopile, the central heat source (6) and the downstream temperature measuring element thermopile are respectively arranged on the first insulating layer (7a), wherein a plurality of groups of the upstream temperature measuring element thermopile and a plurality of groups of the downstream temperature measuring element thermopile are respectively arranged side by side in the longitudinal direction of the chip; Wherein, the front release isolation through holes (11) between adjacent upstream temperature measuring element thermoelectric piles and between adjacent downstream temperature measuring element thermoelectric piles extend to the back release cavity (12).

2. A high-sensitivity and high-resolution flow chip according to claim 1, characterized in that: The upstream temperature measuring element thermopile, the central heat source (6) and the downstream temperature measuring element thermopile are covered with a passivation layer (10).

3. A high-sensitivity and high-resolution flow chip according to claim 1, characterized in that: The front release isolation through hole (11) is in an inverted cone structure.

4. A high-sensitivity and high-resolution flow chip according to claim 1, characterized in that: The back release cavity (12) has a trapezoidal structure.

5. A high-sensitivity and high-resolution flow chip according to claim 1, characterized in that: The upstream temperature measuring element thermopile comprises an upstream temperature measuring element thermopile lower layer thermocouple (5a) and an upstream temperature measuring element thermopile upper layer thermocouple (8a); The downstream temperature measuring element thermopile comprises a downstream temperature measuring element thermopile lower layer thermocouple (5b) and a downstream temperature measuring element thermopile upper layer thermocouple (8b); The upstream temperature measuring element thermopile lower layer thermocouple (5a) and the downstream temperature measuring element thermopile lower layer thermocouple (5b) are covered with a second insulating layer (7b); The upper thermocouple (8a) of the upstream temperature measuring element thermopile and the upper thermocouple (8b) of the downstream temperature measuring element thermopile are covered with a third insulating layer (7c).

6. A high-sensitivity and high-resolution flow chip according to claim 5, characterized in that: It also includes a connecting wire structure that passes through the third insulating layer (7c); The connecting wire structure comprises an upstream cold end connecting wire (91) connected to the lower thermocouple (5a) of the upstream temperature measuring element thermopile, an upstream hot end connecting wire (92) connected between the lower thermocouple (5a) of the upstream temperature measuring element thermopile and the upper thermocouple (8a) of the upstream temperature measuring element thermopile, a downstream cold end connecting wire (94) connected to the lower thermocouple (5b) of the downstream temperature measuring element thermopile, a downstream hot end connecting wire (95) connected between the lower thermocouple (5b) of the downstream temperature measuring element thermopile and the upper thermocouple (8b) of the downstream temperature measuring element thermopile, and a central heat source wire (93) connected to the central heat source (6).

7. A high-sensitivity and high-resolution flow chip according to claim 1, characterized in that: The upstream temperature measuring element thermopile and the downstream temperature measuring element thermopile are symmetrically arranged along the longitudinal symmetric section of the chip.

8. The high-sensitivity and high-resolution flow chip according to claim 5, characterized in that: The support structure layer comprises a first silicon oxide support layer (2), a silicon nitride support layer (3) and a second silicon oxide support layer (4) which are sequentially arranged on the surface of the substrate (1).

9. A high-sensitivity and high-resolution flow chip according to claim 8, characterized in that: A passivation layer (10) is provided on the surface of the third insulating layer (7c), and the front-side release isolation through hole (11) sequentially penetrates the passivation layer (10), the third insulating layer (7c), the second insulating layer (7b), the first insulating layer (7a), the second silicon oxide support layer (4), the silicon nitride support layer (3) and the first silicon oxide support layer (2).

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