Physical layer interface connection state detection circuit and control system
By using small signal amplification circuit and signal detection module in the Ethernet physical layer interface connection status detection circuit, the level signal changes on the network line are detected, and the problem of low time in the existing technology is solved, and the high-speed rail and intelligent driving system is realized Quick response to applications.
Patent Information
- Application Number
- CN202420694828.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-04-03
- Publication Date
- 2025-01-17
- Estimated Expiration
- 2034-04-03
AI Technical Summary
The existing technology has low time-sensitive detection of the connection status of the Ethernet physical layer interface and cannot meet the application scenarios with high time-sensitive requirements such as high-speed rail control systems and intelligent driving systems.
A physical layer interface connection state detection circuit is designed, including a small signal amplification circuit and a signal detection module. It amplifies and shaped the level signal transmitted on the receiving network line, judges the connection state of the interface, and generates an interrupt signal to send it to the external host. .
It significantly improves the response speed of the network system to changes in the physical layer connection state, and meets the timeliness requirements of efficient application scenarios.
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Figure CN222365081U_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of communication detection technology, and in particular to a physical layer interface connection status detection circuit and control system. Background Art
[0002] In order to improve the compatibility between computer systems, embedded systems and communication systems from different manufacturers, the International Organization for Standardization (ISO) has developed an abstract structured seven-layer model. Figure 1 As shown in the figure, the seven structured models divided by OSI are, from high to low, application layer, presentation layer, session layer, transport layer, network layer, data link layer and physical layer. The division of the structured model enables different functional modules (different layers) of the network to share different responsibilities, thereby reducing the complexity of the problem. Once a network failure occurs, the fault layer can be quickly located, which is convenient for finding and correcting errors. Standard interfaces are defined at each layer so that different network devices with the same peer layer can interoperate, and each layer is relatively independent. This is conducive to network technology updates, because each update can be performed within the relevant layer without changing the entire network.
[0003] In the case of following the ISO seven-layer model, such as Figure 2 As shown in the figure, user data is sent from host A to host B. At the sending end, it needs to pass through the application layer, transport layer, network layer, data link layer and physical layer. At each layer, a piece of data with specific meaning will be added to the user data (data encapsulation process), and finally it will be encoded into binary or binary-like data at the physical layer and sent out. At the receiving end, it is a reverse process. The data enters from the physical layer, and at each layer, a piece of data with specific meaning will be stripped off (data decapsulation process), and finally reaches the user layer. The time period used for this data sending process varies from manufacturer to manufacturer, but it is basically between ten milliseconds and twenty milliseconds.
[0004] In other words, the abstract seven-layer model developed by the International Organization for Standardization (ISO) has improved the compatibility of network devices from different manufacturers, but it has sacrificed the speed of network communication to a certain extent, especially for application scenarios with high speed requirements. The above time period can meet the requirements for general network applications, but it does not meet the requirements for some application scenarios with high timeliness requirements, such as high-speed rail control systems and intelligent driving systems. Summary of the invention
[0005] In view of this, an embodiment of the present application provides a physical layer interface connection status detection circuit and control system, which can effectively solve the problem of low efficiency of Ethernet physical layer interface connection status detection.
[0006] In a first aspect, an embodiment of the present application provides a physical layer interface connection state detection circuit, the circuit comprising: a small signal amplification circuit and a signal detection module; the input end of the small signal amplification circuit is used to connect a network cable, and the output end is communicatively connected to the signal detection module; the network cable is used to connect the physical layer chips of the first host and the second host through the corresponding medium connection interface;
[0007] The small signal amplifying circuit is used to receive the level signal transmitted on the network cable, amplify and shape the level signal, and output the amplified signal to the signal detection module;
[0008] The signal detection module is used to determine the connection status of the Ethernet physical layer interface according to the amplified signal.
[0009] In some embodiments, the signal detection module is specifically used to determine the connection state change of the Ethernet physical layer interface according to whether the amplified signal changes between a level continuous jump state and a level continuous unchanged state.
[0010] In some embodiments, the signal detection module is specifically used to determine that the connection state of the Ethernet physical layer interface is invalid when it is detected that the level of the amplified signal remains unchanged for N consecutive clock cycles, and to determine that the connection state of the Ethernet physical layer interface is valid when it is detected that the level of the amplified signal continues to jump for N consecutive clock cycles; 15>N>5.
[0011] In some embodiments, the signal detection module is further used to generate an interrupt signal after determining the connection status, and send the interrupt signal to the first host and the second host externally.
[0012] In some embodiments, the small signal amplification circuit includes any one of an operational amplifier, a triode, a field effect transistor and a Schmitt trigger.
[0013] In some embodiments, the amplification factor of the operational amplifier ranges from 2 to 4.
[0014] In some embodiments, the input end of the small signal amplifying circuit is connected to any line in the network cable to obtain the level signal on the corresponding line.
[0015] In some embodiments, the circuit further comprises an auxiliary small signal amplification circuit;
[0016] The input end of the auxiliary small signal amplifying circuit is used to connect to the second line in the network cable; the output end of the auxiliary small signal amplifying circuit is communicatively connected to the signal detection module to transmit the second amplified signal to the signal detection module; the second line is the other line in the network cable except the line connected to the small signal amplifying circuit;
[0017] The signal detection module is used to determine the connection state of the Ethernet physical layer interface again according to the second amplified signal within M clock cycles when determining that the external connection state of the Ethernet physical layer interface is invalid; M>0.
[0018] In some embodiments, the network cable is an Ethernet twisted pair cable or a fiber optic drive cable.
[0019] In a second aspect, an embodiment of the present application provides a control system, comprising: a first host, a second host, and a physical layer interface connection status detection circuit provided according to the first aspect of the present application; the first host and the second host are connected by a network cable control via the corresponding media connection interface, and are both communicatively connected to the status detection circuit to receive the connection status of the Ethernet physical layer interface.
[0020] The embodiments of the present application have the following beneficial effects:
[0021] The present application collects and amplifies the signals on the Ethernet twisted pair or optical fiber line through a small signal amplification circuit, and uses a signal detection module to monitor the signal status in real time, thereby greatly improving the response speed of the network system when the physical layer connection status of the network system changes. BRIEF DESCRIPTION OF THE DRAWINGS
[0022] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.
[0023] Figure 1 A schematic diagram of the structure of the seven-layer model of OSI division in the prior art of the embodiment of the present application is shown;
[0024] Figure 2 A schematic diagram of a data transmission process in accordance with the OSI standard in the prior art of an embodiment of the present application is shown;
[0025] Figure 3 A structural schematic diagram of a physical layer interface connection status detection circuit according to an embodiment of the present application is shown;
[0026] Figure 4A schematic diagram of a signal that changes from a continuous transition to a continuous transition in a physical layer interface connection state detection circuit according to an embodiment of the present application is shown;
[0027] Figure 5 A schematic diagram of a signal in which a continuous jump changes to a continuous unchanged state in a physical layer interface connection state detection circuit according to an embodiment of the present application is shown;
[0028] Figure 6 A connection diagram is shown when a small signal amplification circuit in a physical layer interface connection state detection circuit according to an embodiment of the present application uses an operational amplifier;
[0029] Figure 7 A connection diagram is shown when a small signal amplification circuit in a physical layer interface connection state detection circuit according to an embodiment of the present application uses a field effect transistor;
[0030] Figure 8 A connection diagram is shown when a small signal amplification circuit in a physical layer interface connection state detection circuit according to an embodiment of the present application uses a triode;
[0031] Fig. 9 A connection diagram is shown when a small signal amplification circuit in a physical layer interface connection state detection circuit according to an embodiment of the present application adopts a Schmitt trigger;
[0032] Fig.10 A structural schematic diagram of a control system according to an embodiment of the present application is shown.
[0033] Description of main component symbols:
[0034] 100-first host; 200-second host; 300-small signal amplification circuit; 400-signal detection module. DETAILED DESCRIPTION
[0035] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments.
[0036] The components of the embodiments of the present application generally described and shown in the drawings herein may be arranged and designed in various configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the application claimed for protection, but merely represents the selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present application.
[0037] Hereinafter, the terms "including", "having" and their cognates that can be used in various embodiments of the present application are intended only to indicate specific features, numbers, steps, operations, elements, components or a combination of the foregoing items, and should not be understood as first excluding the existence of one or more other features, numbers, steps, operations, elements, components or a combination of the foregoing items or increasing the possibility of one or more features, numbers, steps, operations, elements, components or a combination of the foregoing items. In addition, the terms "first", "second", "third" and the like are only used to distinguish descriptions and cannot be understood as indicating or implying relative importance.
[0038] Unless otherwise defined, all terms (including technical terms and scientific terms) used herein have the same meanings as those generally understood by those skilled in the art to which the various embodiments of the present application belong. The terms (such as those defined in generally used dictionaries) will be interpreted as having the same meanings as the contextual meanings in the relevant technical field and will not be interpreted as having idealized meanings or overly formal meanings unless clearly defined in the various embodiments of the present application.
[0039] In conjunction with the accompanying drawings, some embodiments of the present application are described in detail below. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.
[0040] The embodiments of the present application provide a physical layer interface connection status detection circuit and control system, which can effectively solve the problem of low timeliness of Ethernet physical layer interface connection status detection, so as to meet the application scenarios with relatively high timeliness requirements such as high-speed rail control systems and intelligent driving systems.
[0041] The media connection interface (media-related interface) is MDI / MDIX. Ethernet physical layer chips are connected through the MDI / MDIX interface. Common Ethernet media include twisted pair cables, and some physical layer chips also support optical fiber media. According to the prior art, when a twisted pair cable or optical fiber is plugged into a network port, the physical layer chips of the hosts at both ends will establish a connection; when the line is disconnected, the connection is terminated. After the connection is established, the working rate and duplex mode are negotiated, and finally a rate and duplex mode that can be accepted by the physical layer chips and the network cable at both ends of the network cable are established. Generally speaking, the rates and duplex modes are: 100M full-duplex or half-duplex, 1000M (full-duplex, Gigabit rarely uses half-duplex). The signal on the MDI / MDIX interface is a binary signal or a quasi-binary signal with a level jump mode compiled by the physical layer, which can be directly sent to the medium. Because the physical layer chip has a negotiation process, if one line connection of the MDI / MDIX medium fails, the physical layer negotiation fails, and the binary signal or quasi-binary signal on the MDI / MDIX disappears, so the circuit can measure any one line on the MDI. The present application uses a small signal amplifier circuit 300 to measure the signal waveform on the MDI / MDIX, and performs signal amplification and shaping, and finally detects the connection status of the Ethernet physical layer interface through the signal detection module.
[0042] The physical layer interface connection status detection circuit is described below in conjunction with some specific embodiments.
[0043] Figure 3 A schematic diagram of a physical layer interface connection state detection circuit according to an embodiment of the present application is shown. Exemplarily, the physical layer interface connection state detection circuit includes: a small signal amplification circuit 300 and a signal detection module 400 .
[0044] The input end of the small signal amplifier circuit 300 is used to connect to the network cable, and the output end is communicatively connected to the signal detection module 400. Further, the input end of the small signal amplifier circuit 300 is connected to any line in the network cable to obtain the level signal on the corresponding line.
[0045] The network cable is used to connect the physical layer chips of the first host 100 and the second host 200 through the corresponding media connection interface; the first host 100 and the second host 200 are master and slave devices in the high-speed rail control system or the intelligent driving system. Further, the network cable is an Ethernet twisted pair cable or an optical fiber drive cable.
[0046] The small signal amplifying circuit 300 is used to receive the level signal transmitted on the network cable, amplify and shape the level signal, and output the amplified signal to the signal detection module 400. The small signal amplifying circuit 300 includes any one of an operational amplifier, a triode, a field effect transistor and a Schmitt trigger.
[0047] The signal detection module 400 is used to determine the connection status of the Ethernet physical layer interface according to the amplified signal. Preferably, the signal detection module 400 is deployed on the first host 100 and the second host 200. For example, the output end of the small signal amplification circuit 300 is connected to the IO pin of the host (the first host 100 or the second host 200), and the signal detection module 400 in the host determines the connection status of the network interface by reading the state of the pin. However, the signal detection module 400 can also be deployed on an independent device that communicates with the first host 100 and the second host 200, which is not limited here.
[0048] Exemplarily, the signal detection module 400 is specifically used to determine the connection state change of the Ethernet physical layer interface according to whether the edge detection of the amplified signal is continuous, and whether the amplified signal changes between a state of continuous level jump and a state of continuous level change. Wherein, the continuous level change includes that the magnitude of the detection level voltage does not change, and the continuous level jump includes that the battery voltage magnitude changes continuously between a high level and a low level according to a set duty cycle. Further, the signal detection module 400 is specifically used to determine that the connection state of the Ethernet physical layer interface is an invalid connection when it is detected that the level of the amplified signal remains unchanged for N consecutive clock cycles, and to determine that the connection state of the Ethernet physical layer interface is a valid connection when it is detected that the level of the amplified signal continues to jump for N consecutive clock cycles; 15>N>5. Wherein, the invalid connection includes disconnection or disconnection.
[0049] Furthermore, the signal detection module 400 is further configured to generate an interrupt signal after determining the connection state, and send the interrupt signal to the first host 100 and the second host 200. The interrupt signal includes an interrupt signal corresponding to an invalid connection state and an interrupt signal corresponding to a valid connection state.
[0050] It can be understood that when the signal detection module 400 detects that the level state of the amplified signal changes from the original continuous state to receiving 10 rising edge signals in 10 clock cycles, it is determined that the physical layer interface of the application system on the first host 100 or the second host 200 has established a connection, and the waveform is as follows: Figure 4As shown; at this time, the signal detection module 400 triggers the generation of a "connection established" interrupt signal and sends it to the first host 100 and the second host 200. The application systems in the first host 100 and the second host 200 immediately enter the preset application processing.
[0051] When the signal detection module 400 detects that the level state of the amplified signal changes from the original continuous jump to a continuous unchanged state within 10 consecutive clock cycles, it can be determined that the physical layer connection of the application system is invalid (for example, disconnected). At this time, the signal detection module 400 triggers a "connection disconnected" interrupt signal and sends it to the host application system. The host application system immediately enters the preset application processing. The above waveform is as follows Figure 5 The above 10 clock cycles can be completed within a period of 100 microseconds even for the current slowest 10M Ethernet communication, which is significantly faster than the 10 to 20 milliseconds of the standard IOS transmission mode.
[0052] In one implementation, the small signal amplifier circuit 300 is an operational amplifier. Figure 6 As shown, this embodiment uses a common-phase amplifier circuit of an operational amplifier, the input end of the common-phase amplifier circuit is connected to a line in the network cable, and the output end is communicatively connected to the signal detection module 400. The output V o =V i (1+R f / R1), the magnification is 2 to 4, preferably, the magnification is 2, R f Select 100 kilo-ohms and 47 kilo-ohms for R1.
[0053] In one implementation, the small signal amplifier circuit 300 is a field effect transistor. Figure 7 As shown, exemplarily, the field effect tube adopts an N-type MOS tube. The drain D of the MOS tube is connected to the power supply VCC; the gate G is connected to any cable (line) of the Ethernet cable MDI / MDIX medium as the input signal VI; the source S is connected to the ground through a resistor, and the output signal VO is. According to the electrical characteristics of the N-type MOS tube, when the input signal VI is at a low level, the MOS is cut off, no current passes through the resistor Re, and the output signal VO is at a low level; correspondingly, when the input signal VI is at a high level, the MOS is turned on, current passes through the resistor Re, and the output signal VO is at a high level. The effect of implementing the detection scheme through a field effect tube is equivalent to the application of an operational amplifier.
[0054] In one implementation, the small signal amplifier circuit 300 is a triode. Figure 8As shown, the transistor is exemplarily selected as an NPN transistor. The collector c of the transistor is connected to the power supply VCC; the base b is connected to any cable of the Ethernet cable MDI / MDIX medium as the input signal VI; the emitter e is connected to the ground through a resistor, and the output signal VO is. According to the electrical characteristics of the NPN transistor, when the input signal VI is low, the transistor is cut off, no current passes through Re, and the output signal VO is low; correspondingly, when the input signal VI is high, the transistor is turned on, current passes through Re, and the output signal VO is high. The effect of implementing the detection scheme through a transistor is equivalent to using an operational amplifier.
[0055] In one implementation, the small signal amplifier circuit 300 is a Schmitt trigger. Fig. 9 As shown, the Schmitt trigger is implemented by selecting a positive Schmitt trigger. The Schmitt trigger adopts a potential triggering mode, and its output state VO is maintained by the input signal potential. The Schmitt trigger has two threshold voltages, namely the positive threshold voltage VT+ and the negative threshold voltage VT-, and the voltage value of VT+ is greater than VT-. It can be simply understood as: when the input signal VI reaches the positive threshold voltage VT+, VO outputs a high level and remains until the input signal VI drops to the negative threshold voltage VT-, VO outputs a low level. The positive threshold voltage range of the Schmitt trigger described in this embodiment is 2.0V~2.5V, and the negative threshold voltage range is 1.0V~1.5V. Using a Schmitt trigger to implement the signal detection module 400 can play a role in shaping the input signal and improving reliability, and its implementation effect is equivalent to the application of an operational amplifier.
[0056] In one implementation, in order to improve accuracy, the circuit further includes an auxiliary small signal amplification circuit 300;
[0057] The input end of the auxiliary small signal amplifying circuit 300 is used to connect to the second line in the network cable; the output end of the auxiliary small signal amplifying circuit 300 is communicatively connected to the signal detection module 400 to transmit the second amplified signal to the signal detection module 400; the second line is the line in the network cable except the line connected to the small signal amplifying circuit 300;
[0058] The signal detection module 400 is used to verify the connection status of the Ethernet physical layer interface according to the second amplified signal within M clock cycles when it is determined that the external connection status of the Ethernet physical layer interface is invalid. When the signal detection module 400 determines that the Ethernet physical layer interface is invalid according to the amplified signal output by the small signal amplifying circuit 300, it detects the second amplified signal obtained from the auxiliary small signal amplifying circuit 300 within M clock cycles; if the second amplified signal within M clock cycles is a continuous low level, it is determined that the connection is invalid, and if it is a continuous jump, an abnormal alarm is issued.
[0059] In one embodiment, in order to improve reliability, the circuit further includes an auxiliary small signal amplification circuit;
[0060] The input end of the auxiliary small signal amplifier circuit is used to connect to the second line in the network cable; the output end of the auxiliary small signal amplifier circuit is connected to the signal detection module to transmit the second amplified signal to the signal detection module; the second line is the other line in the network cable except the line connected to the small signal amplifier circuit. In other words, two small signal amplifier circuits are used to detect the connection status of the Ethernet physical layer interface.
[0061] The signal detection module is also used to determine the connection state of the Ethernet physical layer interface again according to the level state of the second amplified signal received within M clock cycles when it is determined that the external connection state of the Ethernet physical layer interface is invalid; M>0. Preferably, M=2. Exemplarily, if it is determined that the external connection state of the Ethernet physical layer interface is invalid according to the amplified signal of the small signal amplification circuit, the second amplified signal within M clock cycles obtained at the same time, or the second amplified signal within the subsequent M clock cycles is detected. If the second amplified signal is continuously changing within M clock cycles, an alarm is issued; if the second amplified signal is continuously unchanged within M clock cycles, it is determined that the external connection state of the Ethernet physical layer interface is invalid. In this way, misjudgment caused by a single network cable failure is avoided.
[0062] The present application uses a small signal amplifier circuit 300 to directly monitor the level status of any one of the MDI / MDIX lines, that is, uses a signal detection module 400 to directly monitor whether the signal status of the twisted pair or optical fiber driver changes, and immediately reports it to the system application layer (the system application layer of the first host 100 and the second host 200) through an interrupt. The system application layer makes corresponding response processing as needed, thereby significantly improving the rate of Ethernet communication and ensuring the security of the application system.
[0063] Fig.10A structural schematic diagram of a control system of an embodiment of the present application is shown. Exemplarily, the control system includes: a first host 100, a second host 200 and a physical layer interface connection status detection circuit of the present application; the first host 100 and the second host 200 are connected by a network cable control via a corresponding media connection interface, and are both connected to the state detection circuit for communication to receive the connection status of the Ethernet physical layer interface; wherein, any one of the first host 100 and the second host 200 is selected as the host, and the remaining one is selected as the slave, and the host includes an application control system; the application control system includes a high-speed rail control module or an intelligent driving module. The host system immediately enters the preset application processing upon receiving the interrupt signal.
[0064] It can be understood that the options in the above embodiment are also applicable to this embodiment, so they will not be described again here.
[0065] The present application also provides a terminal device. Exemplarily, the terminal device includes the above-mentioned physical layer interface connection status detection circuit.
[0066] The above description is only a specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application.
Claims
1. A physical layer interface connection status detection circuit, characterized in that: The circuit comprises: a small signal amplifying circuit and a signal detecting module; the input end of the small signal amplifying circuit is used to connect to a network cable, and the output end is communicatively connected to the signal detecting module; the network cable is used to connect the physical layer chips of the first host and the second host through the corresponding medium connection interface; The small signal amplifying circuit is used to receive the level signal transmitted on the network cable, amplify and shape the level signal, and output the amplified signal to the signal detection module; The signal detection module is used to determine the connection status of the Ethernet physical layer interface according to the amplified signal.
2. The physical layer interface connection status detection circuit according to claim 1, characterized in that: The signal detection module is specifically used to determine the connection state change of the Ethernet physical layer interface according to whether the amplified signal changes between a level continuous jump state and a level continuous unchanged state.
3. The physical layer interface connection status detection circuit according to claim 2, characterized in that: The signal detection module is specifically used to determine that the connection state of the Ethernet physical layer interface is invalid when it is detected that the level of the amplified signal remains unchanged for N consecutive clock cycles, and to determine that the connection state of the Ethernet physical layer interface is valid when it is detected that the level of the amplified signal continues to jump for N consecutive clock cycles; 15>N>5.
4. The physical layer interface connection status detection circuit according to claim 1, characterized in that: The signal detection module is further used to generate an interrupt signal after determining the connection state, and send the interrupt signal to the first host and the second host outside.
5. The physical layer interface connection status detection circuit according to claim 1, characterized in that: The small signal amplifying circuit includes any one of an operational amplifier, a triode, a field effect transistor and a Schmitt trigger.
6. The physical layer interface connection status detection circuit according to claim 5, characterized in that: The amplification factor of the operational amplifier ranges from 2 to 4.
7. The physical layer interface connection status detection circuit according to any one of claims 1 to 6, characterized in that: The input end of the small signal amplifying circuit is connected to any line in the network cable to obtain the level signal on the corresponding line.
8. The physical layer interface connection status detection circuit according to claim 7, characterized in that: The circuit also includes an auxiliary small signal amplification circuit; The input end of the auxiliary small signal amplifying circuit is used to connect to the second line in the network cable; the output end of the auxiliary small signal amplifying circuit is communicatively connected to the signal detection module to transmit the second amplified signal to the signal detection module; the second line is the other line in the network cable except the line connected to the small signal amplifying circuit; The signal detection module is used to determine the connection state of the Ethernet physical layer interface again according to the second amplified signal within M clock cycles when determining that the external connection state of the Ethernet physical layer interface is invalid; M>0.
9. The physical layer interface connection status detection circuit according to claim 1 or 8, characterized in that: The network cable is an Ethernet twisted pair cable or an optical fiber drive cable.
10. A control system, characterized in that: include: A first host, a second host and a physical layer interface connection status detection circuit according to any one of claims 1 to 9; the first host and the second host are connected by network cable control via corresponding media connection interfaces, and are both communicatively connected with the status detection circuit to receive the connection status of the Ethernet physical layer interface.