Solar cell, cell assembly and photovoltaic system

Abstract

The utility model is suitable for the technical field of solar cells, and provides a solar cell, a cell module and a photovoltaic system. The solar cell comprises a silicon substrate and a first doping layer, the silicon substrate comprises a central region and a corner edge region, the conduction type of the central region is N type, and the conduction type of the corner edge region is P type; the first doping layer is arranged on the first surface of the silicon substrate; the conduction type of the first doping layer is N type, a high-low junction is formed between the first doping layer and the central region, and a PN junction is formed between the first doping layer and the corner edge region; or, the conduction type of the first doping layer is P type, a PN junction is formed between the first doping layer and the central region, and a high-low junction is formed between the first doping layer and the corner edge region. Therefore, in the process of manufacturing the solar cell based on the silicon substrate, pollution of copper ions to the edge of the silicon substrate is borne by the corner edge area with the P-type conductive type, so that recombination caused by pollution of the copper ions to the edge of the silicon substrate is reduced, and the photoelectric conversion efficiency of the solar cell is improved.

Description

Technical Field

[0001] The present application relates to the technical field of solar cells, and in particular to a solar cell, a battery assembly, and a photovoltaic system. Background Art

[0002] Solar cells can convert sunlight into electrical energy, and solar cells are usually made based on silicon substrates, which can be N-type silicon substrates or P-type silicon substrates. In the related art, in the process of making solar cells based on silicon substrates, the edges of the silicon substrates are easily contaminated by metal ions, especially copper ions. Copper ion contamination will greatly increase the recombination of N-type silicon substrates, but has little effect on P-type silicon substrates. Based on this, how to reduce the adverse effects of copper ion contamination on the edges of silicon substrates has become an urgent problem to be solved. Utility Model Content

[0003] The present application provides a solar cell, a battery module, and a photovoltaic system, aiming to solve the technical problem of how to reduce the adverse effects of copper ion contamination on the edge of a silicon substrate in the prior art.

[0004] The present application is implemented as follows: the solar cell of the embodiment of the present application comprises:

[0005] A silicon substrate, wherein the silicon substrate comprises a central region and a corner edge region, the central region is of N-type conductivity, and the corner edge region is of P-type conductivity;

[0006] A first doped layer, disposed on the first surface of the silicon substrate;

[0007] The conductivity type of the first doped layer is N-type, forming a high-low junction with the central area and a PN junction with the corner edge area; or, the conductivity type of the first doped layer is P-type, forming a PN junction with the central area and a high-low junction with the corner edge area.

[0008] Specifically, the first doping layer is a diffusion doping layer.

[0009] Specifically, the first doped layer is a doped polysilicon layer or a doped amorphous silicon layer, a first passivation layer is provided between the first doped layer and the silicon substrate, and the first passivation layer is an intrinsic amorphous silicon layer or a silicon oxide layer.

[0010] Specifically, the first doped layer is a doped polysilicon layer, a first passivation layer is provided between the first doped layer and the silicon substrate, the first passivation layer is an intrinsic amorphous silicon layer or a silicon oxide layer, the silicon substrate forms an inner diffusion layer, a high-low junction is formed between the inner diffusion layer and the doped polysilicon, and the inner diffusion layer forms a high-low junction or a PN junction with the silicon substrate.

[0011] Specifically, the solar cell includes a second doped layer, and the second doped layer is arranged on the second surface of the silicon substrate;

[0012] When the conductivity type of the first doped layer is N-type, the conductivity type of the second doped layer is P-type, a PN junction is formed between the second doped layer and the central area, and a high-low junction is formed between the second doped layer and the corner edge area; or, when the conductivity type of the first doped layer is P-type, the conductivity type of the second doped layer is N-type, a high-low junction is formed between the second doped layer and the central area, and a PN junction is formed between the second doped layer and the corner edge area.

[0013] Specifically, the projections of the high-low junction formed between the first doped layer and the central region and the PN junction formed between the second doped layer and the central region in the thickness direction of the solar cell completely overlap;

[0014] Alternatively, the projections of the PN junction formed between the first doped layer and the central region and the high-low junction formed between the second doped layer and the central region in the thickness direction of the solar cell completely overlap.

[0015] Specifically, the silicon substrate includes an intermediate passivation region, which is located between the central region and the corner edge region, and has a resistivity greater than that of the central region and greater than that of the corner edge region.

[0016] Specifically, the resistivity of the intermediate passivation region is greater than or equal to 1000Ω·cm.

[0017] Specifically, the central region includes an N-type doping element, and the N-type doping element includes at least one element of the fifth main group element and the sixth main group element.

[0018] Specifically, the corner edge region includes a P-type doping element, and the P-type doping element includes at least one element of the third main group elements.

[0019] Specifically, the silicon substrate includes a side edge region, the side edge region is located between two adjacent corner edge regions, and the conductivity type of the side edge region is P type.

[0020] Specifically, the surface of the central area in the thickness direction of the silicon substrate is circular, the center of the circle is the center point of the silicon substrate, and the radius is 1 / 5-1 / 2 of the side length of the silicon substrate.

[0021] Specifically, the corner edge region includes a first corner side and a second corner side, the length of the first corner side is 1 / 100-1 / 2 of the side length of the silicon substrate, and the length of the second corner side is 1 / 100-1 / 2 of the side length of the silicon substrate.

[0022] Specifically, a ratio of the resistivity of the corner edge region to the resistivity of the central region is greater than or equal to 1.2.

[0023] Specifically, the resistivity of the central region is greater than or equal to 10Ω·cm.

[0024] Specifically, the resistivity of the corner edge region is greater than or equal to 100Ω·cm.

[0025] Specifically, the acceptor impurity concentration of the corner edge region is lower than the acceptor impurity concentration of the central region, and the acceptor impurity concentration of the central region is lower than the donor impurity concentration of the central region.

[0026] Specifically, the donor impurity concentration in the corner edge region is lower than that in the central region, and the donor impurity concentration in the corner edge region is lower than that in the acceptor impurity concentration in the corner edge region.

[0027] Specifically, the doping elements in the central region and the corner edge region both include a P-type doping element and an N-type doping element, the doping concentration of the N-type doping element in the central region is greater than the doping concentration of the P-type doping element in the central region, and the doping concentration of the P-type doping element in the corner edge region is greater than the doping concentration of the N-type doping element in the corner edge region;

[0028] The absolute value of the slope of the concentration curve of the N-type doping element is greater than the absolute value of the slope of the concentration curve of the P-type doping element;

[0029] The horizontal axis of the concentration curve of the N-type doping element is the distance from the test position of the silicon substrate to the center point of the silicon substrate, and the vertical axis is the concentration of the N-type doping element at the test position; the horizontal axis of the concentration curve of the P-type doping element is the distance from the test position to the center point of the silicon substrate, and the vertical axis is the concentration of the P-type doping element at the test position.

[0030] Specifically, the absolute value of the slope of the concentration curve of the N-type doping element and the absolute value of the slope of the concentration curve of the P-type doping element satisfy the following formula:

[0031]

[0032] Among them, a is the side length of the silicon substrate, N1 is the doping concentration of the N-type doping element in the central area, P1 is the doping concentration of the P-type doping element in the central area, K1 is the absolute value of the slope of the concentration curve of the N-type doping element, and K2 is the absolute value of the slope of the concentration curve of the P-type doping element.

[0033] The present application also provides a battery assembly, comprising any of the above-mentioned solar cells.

[0034] The present application also provides a photovoltaic system, comprising the above-mentioned battery assembly.

[0035] In the solar cell, battery assembly, and photovoltaic system of the embodiment of the present application, since the conductivity type of the central area of ​​the silicon substrate is N-type and the conductivity type of the corner edge area is P-type, in the process of making a solar cell based on a silicon substrate, the corner edge area with a conductivity type of P-type is used to withstand the contamination of the edge of the silicon substrate by copper ions, thereby reducing the recombination caused by the contamination of the edge of the silicon substrate by copper ions. At the same time, the first doped layer forms a high-low junction and a PN junction with the central area and the corner edge area, respectively, or forms a PN junction and a high-low junction with the central area and the corner edge area, respectively, so that the minority carriers inside can become majority carriers after entering the edge, and the minority carriers at the edge can become majority carriers after entering the central area, thereby improving the carrier life. At the same time, a strong electric field is formed between the central area and the corner edge area, and a fully surrounded field passivation effect is formed above and below and around the central area. Moreover, the conductivity types of the central area and the corner edge area are N-type and P-type, respectively, and a PN junction can be formed in the silicon substrate, forming a better field passivation effect in the solar cell, which is conducive to carrier transmission. In this way, it is conducive to improving the photoelectric conversion efficiency of the solar cell.

[0036] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 is a schematic structural diagram of a solar cell provided by an embodiment of the present application;

[0038] Figure 2 is a schematic structural diagram of a silicon substrate of a solar cell provided in one embodiment of the present application;

[0039] Figure 3 is a schematic structural diagram of a silicon substrate of a solar cell provided in one embodiment of the present application;

[0040] Figure 4 is a schematic structural diagram of a silicon substrate of a solar cell provided in one embodiment of the present application;

[0041] Figure 5is a schematic structural diagram of a silicon substrate of a solar cell provided in one embodiment of the present application;

[0042] Figure 6 is a schematic structural diagram of a solar cell provided by an embodiment of the present application;

[0043] Figure 7 is a schematic structural diagram of a solar cell provided by an embodiment of the present application;

[0044] Figure 8 is a schematic structural diagram of a solar cell provided by an embodiment of the present application;

[0045] Fig. 9 is a schematic diagram of doping concentration distribution of a silicon substrate of a solar cell provided in one embodiment of the present application;

[0046] Description of main component symbols:

[0047] Solar cell 1000, silicon substrate 10, central region 11, corner edge region 12, first corner side 121, second corner side 122, intermediate passivation region 13, side edge region 14; first doped layer 21, first passivation layer 22, inner diffusion layer 23, first passivation anti-reflection layer 24, first electrode 25, second doped layer 31, second passivation anti-reflection layer 32, second electrode 33. DETAILED DESCRIPTION

[0048] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and should not be construed as limiting the present application. In addition, it should be understood that the specific embodiments described herein are only used to explain the present application and are not intended to limit the present application.

[0049] In the description of the present application, it should be understood that the terms "upper", "lower", "back", "front", etc., indicating orientations or positional relationships are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0050] In the present application, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may include that the first and second features are in direct contact, or may include that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, a first feature being "above", "above" and "above" a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being "below", "below" and "below" a second feature includes that the first feature is directly below and obliquely below the second feature, or simply indicates that the first feature is lower in level than the second feature.

[0051] The disclosure below provides many different embodiments or examples to realize the different structures of the present application. In order to simplify the disclosure of the present application, the parts and settings of specific examples are described below. Of course, they are only examples, and the purpose is not to limit the present application. In addition, the present application can repeat reference numbers and / or reference letters in different examples, and this repetition is for the purpose of simplification and clarity, and does not indicate the relationship between the various embodiments and / or settings discussed in itself. In addition, the various specific processes and examples of materials provided by the present application, but those of ordinary skill in the art can be aware of the application of other processes and / or the use scenarios of other materials.

[0052] In the present application, since the conductivity type of the central area of ​​the silicon substrate is N-type and the conductivity type of the corner edge area is P-type, in the process of making a solar cell based on a silicon substrate, the corner edge area with a conductivity type of P-type is used to withstand the contamination of the edge of the silicon substrate by copper ions, thereby reducing the recombination caused by the copper ion contamination of the edge of the silicon substrate. At the same time, the first doped layer forms a high-low junction and a PN junction with the central area and the corner edge area, or forms a PN junction and a high-low junction with the central area and the corner edge area, respectively, so that the minority carriers inside can become majority carriers after entering the edge, and the minority carriers at the edge can become majority carriers after entering the central area, thereby improving the carrier life. At the same time, a strong electric field is formed between the central area and the corner edge area, and a fully surrounded field passivation effect is formed above and below and around the central area. Moreover, the conductivity types of the central area and the corner edge area are N-type and P-type, respectively, and a PN junction can be formed in the silicon substrate, forming a better field passivation effect in the solar cell, which is conducive to carrier transmission. In this way, it is conducive to improving the photoelectric conversion efficiency of the solar cell.

[0053] Embodiment 1

[0054] See also Figure 1 , Figure 2 , Figure 3 , Figure 4 and Figure 5The solar cell 1000 of the embodiment of the present application includes a silicon substrate 10 and a first doped layer 21. The silicon substrate 10 includes a central region 11 and a corner edge region 12. The conductivity type of the central region 11 is N-type, and the conductivity type of the corner edge region 12 is P-type. The first doped layer 21 is arranged on the first surface of the silicon substrate 10. The conductivity type of the first doped layer 21 is N-type, and a high-low junction is formed between the first doped layer 21 and the central region 11, and a PN junction is formed between the first doped layer 21 and the corner edge region 12; or, the conductivity type of the first doped layer 21 is P-type, and a PN junction is formed between the first doped layer 21 and the central region 11, and a high-low junction is formed between the first doped layer 21 and the corner edge region 12.

[0055] In the solar cell 1000 of the embodiment of the present application, since the conductivity type of the central region 11 of the silicon substrate 10 is N-type and the conductivity type of the corner edge region 12 is P-type, in the process of manufacturing the solar cell 1000 based on the silicon substrate 10, the corner edge region 12 with the conductivity type of P-type is used to bear the contamination of the edge of the silicon substrate 10 by copper ions, thereby reducing the recombination caused by the copper ion contamination of the edge of the silicon substrate 10. At the same time, the first doping layer 21 forms a high-low junction and a PN junction with the central region 11 and the corner edge region 12, respectively, or forms a PN junction and a high-low junction with the central region 11 and the corner edge region 12, respectively, so that the minority carriers in the interior can become majority carriers after entering the edge, and the minority carriers at the edge can become majority carriers after entering the central region 11, thereby improving the carrier lifetime. At the same time, a strong electric field is formed between the central region 11 and the corner edge region 12, and a fully enclosed field passivation effect is formed above, below and around the central region 11. Moreover, the conductivity types of the central region 11 and the corner edge region 12 are N-type and P-type respectively, which can form a PN junction in the silicon substrate 10, and form a better field passivation effect in the solar cell 1000, which is beneficial to carrier transmission. In this way, the photoelectric conversion efficiency of the solar cell 1000 is improved.

[0056] In the present application, the silicon substrate 10 is a single crystal silicon substrate 10. It can be understood that in other embodiments, the silicon substrate 10 may also be a polycrystalline silicon substrate 10, which is not limited here.

[0057] In this embodiment, the silicon substrate 10 is square, and the four corners of the silicon substrate 10 are chamfered. It can be understood that in other embodiments, the silicon substrate 10 can be rectangular, circular, elliptical, triangular or other forms; the corners of the silicon substrate 10 can be rounded, pointed or other forms; the shapes of multiple corners of the silicon substrate 10 can be the same or different.

[0058] Specifically, the central region 11 refers to a spatial region extending outward from the center line of the silicon substrate 10 in the thickness direction. The center line forms a center point on two surfaces in the thickness direction of the silicon substrate 10. When viewed from the thickness direction of the silicon substrate 10, the central region 11 extends outward from the center point, such as Figure 2 , Figure 3 , Figure 4 and Figure 5 That is to say, the central region 11 is not formed only on the surface of the silicon substrate 10, but is a spatial region with thickness.

[0059] Specifically, the corner edge region 12 refers to a spatial region extending from the cutting surface of the corner of the silicon substrate 10 to the center line of the silicon substrate 10. It can be understood that the cross section of the silicon rod 100 is circular, and the silicon substrate 10 forms a corner, so the silicon rod 100 must be cut to form a cutting surface at the corner. For example, in the case where the corner of the silicon substrate 10 is chamfered or rounded, the cutting surface is a surface formed by cutting the chamfered or rounded corner.

[0060] Further, as mentioned above, the center line forms a center point on both surfaces in the thickness direction of the silicon substrate 10. Therefore, from the thickness direction of the silicon substrate 10, the corner edge region 12 extends from the edge line of the corner of the silicon substrate 10 to the center point, as shown in FIG. Figure 2 , Figure 3 , Figure 4 and Figure 5 That is to say, the corner edge region 12 is not formed only on the surface of the silicon substrate 10, but is a spatial region having thickness.

[0061] Specifically, the thickness of the silicon substrate 10 may be 30 μm-300 μm, for example, 30 um, 40 um, 50 um, 60 um, 70 um, 80 um, 90 um, 100 um, 150 um, 200 um, 250 um, 300 um. In this way, it is possible to avoid the silicon substrate 10 being too thin, which may result in a too low concentration of photogenerated carriers, and it is also possible to avoid the silicon substrate 10 being too thick, which may result in an excessively high cost of the battery.

[0062] Specifically, “the conductivity type of the central region 11 is N type” means that the conductivity type presented by the central region 11 is N type. This does not mean that the type of doping elements in the central region 11 is limited.

[0063] Further, in some embodiments, the central region 11 may not include P-type doping elements, but include N-type doping elements, so that the conductivity type of the central region 11 is N-type. In other embodiments, the central region 11 may also include P-type doping elements and N-type doping elements, and the concentration of the N-type doping elements is greater than the concentration of the P-type doping elements, so that the conductivity type of the central region 11 is N-type.

[0064] Specifically, “the conductivity type of the corner edge region 12 is P type” means that the conductivity type presented by the corner edge region 12 is P type. This does not mean that the type of doping element of the corner edge region 12 is limited.

[0065] Further, in some embodiments, the corner edge region 12 may not include N-type doping elements, but include P-type doping elements, so that the conductivity type of the corner edge region 12 is P-type. In other embodiments, the corner edge region 12 may also include P-type doping elements and N-type doping elements, and the concentration of the P-type doping elements is greater than the concentration of the N-type doping elements, so that the conductivity type of the central region 11 is P-type.

[0066] Specifically, the two surfaces of the silicon substrate 10 in the thickness direction are respectively the first surface and the second surface. The first surface may be the light-facing surface and the second surface may be the backlight surface; or the first surface may be the backlight surface and the second surface may be the light-facing surface. This is not limited here.

[0067] Specifically, “the first doping layer 21 is disposed on the first surface of the silicon substrate 10” may mean that the first doping layer 21 is diffused on the first surface, or may mean that the first doping layer 21 is deposited on the first surface. The specific form in which the first doping layer 21 is disposed on the first surface of the silicon substrate 10 is not limited herein.

[0068] In some embodiments, the first doped layer 21 has an N-type conductivity type, forms a high-low junction with the N-type central region 11 , and forms a PN junction with the P-type corner edge region 12 .

[0069] Please note that when the conductivity type of the first doped layer 21 is N-type, the range of the high-low junction formed between the first doped layer 21 and the silicon substrate 10 corresponds to the range of the region of the silicon substrate 10 with N-type conductivity. The region of the silicon substrate 10 with N-type conductivity may completely overlap with the central region 11 or may exceed the central region 11. When the region of the silicon substrate 10 with N-type conductivity exceeds the central region 11, the high-low junction formed between the first doped layer 21 and the silicon substrate 10 also exceeds the central region 11.

[0070] Similarly, when the conductivity type of the first doped layer 21 is N-type, the range of the PN junction formed between the first doped layer 21 and the silicon substrate 10 corresponds to the range of the region where the conductivity type of the silicon substrate 10 is P-type. The region where the conductivity type of the silicon substrate 10 is P-type may completely overlap with the corner edge region 12, or may exceed the corner edge region 12. When the region where the conductivity type of the silicon substrate 10 is P-type exceeds the corner edge region 12, the PN junction formed between the first doped layer 21 and the silicon substrate 10 also exceeds the corner edge region 12.

[0071] In some embodiments, the first doped layer 21 is of P-type conductivity, forms a PN junction with the central region 11 of N-type conductivity, and forms a high-low junction with the corner edge region 12 of P-type conductivity.

[0072] Please note that when the first doped layer 21 is of P-type conductivity, the range of the PN junction formed between the first doped layer 21 and the silicon substrate 10 corresponds to the range of the region of the silicon substrate 10 of N-type conductivity. The region of the silicon substrate 10 of N-type conductivity may completely overlap with the central region 11 or may exceed the central region 11. When the region of the silicon substrate 10 of N-type conductivity exceeds the central region 11, the PN junction formed between the first doped layer 21 and the silicon substrate 10 also exceeds the central region 11.

[0073] Similarly, when the first doped layer 21 is of P-type conductivity, the range of the high-low junction formed between the first doped layer 21 and the silicon substrate 10 corresponds to the range of the region of the silicon substrate 10 of P-type conductivity. The region of the silicon substrate 10 of P-type conductivity may completely overlap with the corner edge region 12, or may exceed the corner edge region 12. When the region of the silicon substrate 10 of P-type conductivity exceeds the corner edge region 12, the high-low junction formed between the first doped layer 21 and the silicon substrate 10 also exceeds the corner edge region 12.

[0074] Specifically, the solar cell 1000 may further include a first passivation anti-reflection layer 24 and a first electrode 25. The first passivation anti-reflection layer 24 is stacked on the first doped layer 21. The first electrode 25 passes through the first passivation anti-reflection layer 24 and connects to the first doped layer 21. The first passivation anti-reflection layer 24 includes at least one of an aluminum oxide layer, a silicon nitride layer, a silicon oxide layer, and a silicon oxynitride layer. The first electrode 25 includes at least one of a copper electrode, an aluminum electrode, and a silver electrode.

[0075] Specifically, the solar cell 1000 may further include a second passivation anti-reflection layer 32 and a second electrode 33. The second passivation anti-reflection layer 32 is disposed on the second surface of the silicon substrate 10. The second electrode 33 passes through the second passivation anti-reflection layer 32 and connects to the silicon substrate 10. The second passivation anti-reflection layer 32 includes at least one of an aluminum oxide layer, a silicon nitride layer, a silicon oxide layer, and a silicon oxynitride layer. The second electrode 33 includes at least one of a copper electrode, an aluminum electrode, and a silver electrode.

[0076] Embodiment 2

[0077] In some embodiments, the first doped layer 21 is a diffuse doped layer.

[0078] In this way, a diffusion process can be used to dope impurities into the silicon substrate 10, thereby forming a first doping layer 21 on the silicon substrate 10, which makes it easy for the first doping layer 21 to achieve high concentration, deep junction with the silicon substrate 10, and less surface damage.

[0079] It is understood that in other embodiments, the first doping layer 21 may be an ion implantation doping layer, so that the number of doping atoms and the doping depth can be better controlled, the lateral diffusion effect is small, and the required temperature is low.

[0080] Embodiment 3

[0081] See also Figure 6 In some embodiments, the first doped layer 21 is a doped polysilicon layer or a doped amorphous silicon layer, and a first passivation layer 22 is provided between the first doped layer 21 and the silicon substrate 10, and the first passivation layer 22 is an intrinsic amorphous silicon layer or a silicon oxide layer.

[0082] In this way, the first passivation layer 22 and the first doping layer 21 stacked on the silicon substrate 10 form a passivation contact structure, providing a passivation effect for the solar cell 1000. The first passivation layer 22 allows the majority carriers to tunnel into the first doping layer 21, while blocking the recombination of the minority carriers, thereby achieving the lateral transmission of the majority carriers in the first doping layer 21 and being collected by the metal electrode of the solar cell 1000, thereby reducing the recombination of the metal contact area, which is beneficial to improving the open circuit voltage and short circuit current of the solar cell 1000.

[0083] In one example, the first doped layer 21 is a doped polysilicon layer, and an intrinsic amorphous silicon layer is provided between the first doped layer 21 and the silicon substrate 10; in another example, the first doped layer 21 is a doped polysilicon layer, and a silicon oxide layer is provided between the first doped layer 21 and the silicon substrate 10; in yet another example, the first doped layer 21 is a doped amorphous silicon layer, and an intrinsic amorphous silicon layer is provided between the first doped layer 21 and the silicon substrate 10; in another example, the first doped layer 21 is a doped amorphous silicon layer, and a silicon oxide layer is provided between the first doped layer 21 and the silicon substrate 10.

[0084] It can be understood that the first passivation layer 22 is formed with a hole structure. The first doped layer 21 passes through the first passivation layer 22 to form a high-low junction or a PN junction with the silicon substrate 10. The PN junction and the high-low junction formed by the first doped layer 21 and the single crystal silicon substrate 10 are both heterojunctions.

[0085] Embodiment 4

[0086] See also Figure 7In some embodiments, the first doped layer 21 is a doped polysilicon layer, a first passivation layer 22 is provided between the first doped layer 21 and the silicon substrate 10, the first passivation layer 22 is an intrinsic amorphous silicon layer or a silicon oxide layer, the silicon substrate 10 forms an inner diffusion layer 23, a high-low junction is formed between the inner diffusion layer 23 and the doped polysilicon, and the inner diffusion layer 23 and the silicon substrate 10 form a high-low junction or a PN junction.

[0087] In this way, a better passivation effect is provided for the solar cell 1000 , and the recombination of the metal contact area can be further reduced, which is beneficial to further improve the open circuit voltage and short circuit current of the solar cell 1000 .

[0088] It can be understood that since the inner diffusion layer 23 is formed by the doped polysilicon layer diffusing through the first passivation layer 22 to the silicon substrate 10, the inner diffusion layer 23 and the doped polysilicon layer have the same conductivity type, so a high-low junction is formed between the inner diffusion layer 23 and the doped polysilicon. The conductivity type of the central region 11 of the silicon substrate 10 is N-type, and the conductivity type of the corner edge region 12 is P-type. Therefore, when the conductivity type of the inner diffusion layer 23 is N-type, the inner diffusion layer 23 forms a high-low junction with the central region 11 and a PN junction with the corner edge region 12; when the conductivity type of the inner diffusion layer 23 is P-type, the inner diffusion layer 23 forms a PN junction with the central region 11 and a high-low junction with the corner edge region 12.

[0089] In one example, the first doped layer 21 is a doped polysilicon layer, and an intrinsic amorphous silicon layer is provided between the first doped layer 21 and the silicon substrate 10 ; in another example, the first doped layer 21 is a doped polysilicon layer, and a silicon oxide layer is provided between the first doped layer 21 and the silicon substrate 10 .

[0090] Embodiment 5

[0091] See also Figure 8 In some embodiments, the solar cell 1000 includes a second doping layer 31, and the second doping layer 31 is disposed on the second surface of the silicon substrate 10;

[0092] When the conductivity type of the first doped layer 21 is N-type, the conductivity type of the second doped layer 31 is P-type, a PN junction is formed between the second doped layer 31 and the central area 11, and a high-low junction is formed between the second doped layer 31 and the corner edge area 12; or, when the conductivity type of the first doped layer 21 is P-type, the conductivity type of the second doped layer 31 is N-type, a high-low junction is formed between the second doped layer 31 and the central area 11, and a PN junction is formed between the second doped layer 31 and the corner edge area 12.

[0093] In this way, both the first and second surfaces of the silicon substrate 10 form doping layers, thereby forming a PN junction or a high-low junction, so that both surfaces of the solar cell 1000 in the thickness direction can receive light to generate electricity, which is beneficial to improving the photoelectric conversion efficiency of the solar cell 1000.

[0094] Specifically, “the second doping layer 31 is disposed on the second surface of the silicon substrate 10” may mean that the second doping layer 31 is diffused on the second surface, or may mean that the second doping layer 31 is deposited on the second surface. The specific form in which the second doping layer 31 is disposed on the second surface of the silicon substrate 10 is not limited herein.

[0095] In some embodiments, the second doping layer 31 has an N-type conductivity type, forms a high-low junction with the N-type central region 11 , and forms a PN junction with the P-type corner edge region 12 .

[0096] Please note that when the conductivity type of the second doped layer 31 is N-type, the range of the high-low junction formed between the second doped layer 31 and the silicon substrate 10 corresponds to the range of the region of the silicon substrate 10 with N-type conductivity. The region of the silicon substrate 10 with N-type conductivity may completely overlap with the central region 11 or may exceed the central region 11. When the region of the silicon substrate 10 with N-type conductivity exceeds the central region 11, the high-low junction formed between the second doped layer 31 and the silicon substrate 10 also exceeds the central region 11.

[0097] Similarly, when the conductivity type of the second doped layer 31 is N-type, the range of the PN junction formed between the second doped layer 31 and the silicon substrate 10 corresponds to the range of the region where the conductivity type of the silicon substrate 10 is P-type. The region where the conductivity type of the silicon substrate 10 is P-type may completely overlap with the corner edge region 12, or may exceed the corner edge region 12. When the region where the conductivity type of the silicon substrate 10 is P-type exceeds the corner edge region 12, the PN junction formed between the second doped layer 31 and the silicon substrate 10 also exceeds the corner edge region 12.

[0098] In some embodiments, the second doped layer 31 is of P-type conductivity, forms a PN junction with the central region 11 of N-type conductivity, and forms a high-low junction with the corner edge region 12 of P-type conductivity.

[0099] Please note that when the conductivity type of the second doped layer 31 is P-type, the range of the PN junction formed between the second doped layer 31 and the silicon substrate 10 corresponds to the range of the region of the silicon substrate 10 that is N-type in conductivity. The region of the silicon substrate 10 that is N-type in conductivity may completely overlap with the central region 11, or may exceed the central region 11. When the region of the silicon substrate 10 that is N-type in conductivity exceeds the central region 11, the PN junction formed between the second doped layer 31 and the silicon substrate 10 also exceeds the central region 11.

[0100] Similarly, when the conductivity type of the second doped layer 31 is P-type, the range of the high-low junction formed between the second doped layer 31 and the silicon substrate 10 corresponds to the range of the region where the conductivity type of the silicon substrate 10 is P-type. The region where the conductivity type of the silicon substrate 10 is P-type may completely overlap with the corner edge region 12, or may exceed the corner edge region 12. When the region where the conductivity type of the silicon substrate 10 is P-type exceeds the corner edge region 12, the high-low junction formed between the second doped layer 31 and the silicon substrate 10 also exceeds the corner edge region 12.

[0101] In some embodiments, the second doping layer 31 is a diffuse doping layer.

[0102] In this way, a diffusion process can be used to dope impurities into the silicon substrate 10, thereby forming a second doping layer 31 on the silicon substrate 10, which makes it easy for the second doping layer 31 to achieve high concentration, deep junction with the silicon substrate 10, and less surface damage.

[0103] It is understood that in other embodiments, the second doping layer 31 may be an ion implantation doping layer, so that the number of doping atoms and the doping depth can be better controlled, the lateral diffusion effect is small, and the required temperature is low.

[0104] In some embodiments, the second doped layer 31 is a doped polysilicon layer or a doped amorphous silicon layer. A second passivation layer is disposed between the second doped layer 31 and the silicon substrate 10 . The second passivation layer is an intrinsic amorphous silicon layer or a silicon oxide layer.

[0105] In this way, the second passivation layer and the second doping layer 31 stacked on the silicon substrate 10 form a passivation contact structure, providing a passivation effect for the solar cell 1000. The second passivation layer can allow majority carriers to tunnel into the second doping layer 31, while blocking minority carriers from recombination, thereby achieving lateral transmission of majority carriers in the second doping layer 31 and being collected by the metal electrode of the solar cell 1000, thereby reducing the recombination of the metal contact area, which is beneficial to improving the open circuit voltage and short circuit current of the solar cell 1000.

[0106] In one example, the second doping layer 31 is a doped polysilicon layer, and an intrinsic amorphous silicon layer is provided between the second doping layer 31 and the silicon substrate 10; in another example, the second doping layer 31 is a doped polysilicon layer, and a silicon oxide layer is provided between the second doping layer 31 and the silicon substrate 10; in yet another example, the second doping layer 31 is a doped amorphous silicon layer, and an intrinsic amorphous silicon layer is provided between the second doping layer 31 and the silicon substrate 10; in another example, the second doping layer 31 is a doped amorphous silicon layer, and a silicon oxide layer is provided between the second doping layer 31 and the silicon substrate 10.

[0107] It can be understood that the second passivation layer is formed with a hole structure. The second doped layer 31 passes through the second passivation layer to form a high-low junction or a PN junction with the silicon substrate 10. The PN junction and the high-low junction formed by the second doped layer 31 and the silicon substrate 10 of single crystal silicon are both heterojunctions.

[0108] In some embodiments, the second doped layer 31 is a doped polysilicon layer, a second passivation layer is provided between the second doped layer 31 and the silicon substrate 10, the second passivation layer is an intrinsic amorphous silicon layer or a silicon oxide layer, the silicon substrate 10 forms an inner diffusion layer 23, a high-low junction is formed between the inner diffusion layer 23 and the doped polysilicon, and the inner diffusion layer 23 and the silicon substrate 10 form a high-low junction or a PN junction.

[0109] In this way, a better passivation effect is provided for the solar cell 1000 , and the recombination of the metal contact area can be further reduced, which is beneficial to further improve the open circuit voltage and short circuit current of the solar cell 1000 .

[0110] It can be understood that since the inner diffusion layer 23 is formed by the doped polysilicon layer diffusing through the second passivation layer to the silicon substrate 10, the inner diffusion layer 23 and the doped polysilicon layer have the same conductivity type, and therefore, a high-low junction is formed between the inner diffusion layer 23 and the doped polysilicon. The conductivity type of the central region 11 of the silicon substrate 10 is N-type, and the conductivity type of the corner edge region 12 is P-type. Therefore, when the conductivity type of the inner diffusion layer 23 is N-type, the inner diffusion layer 23 forms a high-low junction with the central region 11 and a PN junction with the corner edge region 12; when the conductivity type of the inner diffusion layer 23 is P-type, the inner diffusion layer 23 forms a PN junction with the central region 11 and a high-low junction with the corner edge region 12.

[0111] In one example, the second doped layer 31 is a doped polysilicon layer, and an intrinsic amorphous silicon layer is provided between the second doped layer 31 and the silicon substrate 10 ; in another example, the second doped layer 31 is a doped polysilicon layer, and a silicon oxide layer is provided between the second doped layer 31 and the silicon substrate 10 .

[0112] Embodiment 6

[0113] In some embodiments, the projections of the high-low junction formed between the first doping layer 21 and the central region 11 and the PN junction formed between the second doping layer 31 and the central region 11 in the thickness direction of the solar cell 1000 completely overlap.

[0114] In some embodiments, the projections of the PN junction formed between the first doping layer 21 and the central region 11 and the high-low junction formed between the second doping layer 31 and the central region 11 in the thickness direction of the solar cell 1000 completely overlap.

[0115] In this way, the high-low junction and the PN junction form the effect of minority carrier extraction surface, making the effect of two-sided field passivation better.

[0116] It can be understood that in other embodiments, the projection of the high-low junction formed between the first doped layer 21 and the central region 11 in the thickness direction of the solar cell 1000 may cover and exceed the projection of the PN junction formed between the second doped layer 31 and the central region 11 in the thickness direction of the solar cell 1000 in the same plane; the projection of the PN junction formed between the second doped layer 31 and the central region 11 in the thickness direction of the solar cell 1000 may cover and exceed the projection of the high-low junction formed between the first doped layer 21 and the central region 11 in the thickness direction of the solar cell 1000 in the same plane; the projection of the high-low junction formed between the first doped layer 21 and the central region 11 in the thickness direction of the solar cell 1000 may intersect with the projection of the PN junction formed between the second doped layer 31 and the central region 11 in the thickness direction of the solar cell 1000 in the same plane.

[0117] It can be understood that in other embodiments, the projection of the PN junction formed between the first doped layer 21 and the central region 11 in the thickness direction of the solar cell 1000 may cover and exceed the projection of the high-low junction formed between the second doped layer 31 and the central region 11 in the thickness direction of the solar cell 1000 in the same plane; the projection of the high-low junction formed between the second doped layer 31 and the central region 11 in the thickness direction of the solar cell 1000 may cover and exceed the projection of the PN junction formed between the first doped layer 21 and the central region 11 in the thickness direction of the solar cell 1000 in the same plane; the projection of the PN junction formed between the first doped layer 21 and the central region 11 in the thickness direction of the solar cell 1000 may intersect with the projection of the high-low junction formed between the second doped layer 31 and the central region 11 in the thickness direction of the solar cell 1000 in the same plane.

[0118] Embodiment 7

[0119] See also Figure 1 and Figure 2 In some embodiments, the silicon substrate 10 includes an intermediate passivation region 13, which is located between the central region 11 and the corner edge region 12, and the resistivity of the intermediate passivation region 13 is greater than the resistivity of the central region 11, and the resistivity of the intermediate passivation region 13 is greater than the resistivity of the corner edge region 12.

[0120] In this way, a strong electric field is formed between the central region 11 and the corner edge region 12, a PIN junction is formed in the silicon substrate 10, and the recombination of PN direct contact is reduced. In the solar cell 1000, a fully surrounding field passivation effect is formed above, below and around the central region 11, which is beneficial to carrier transmission.

[0121] Specifically, the intermediate passivation region 13 is located between the central region 11 and the corner edge region 12, which means that the intermediate passivation region 13 separates the central region 11 from the corner edge region 12. It can be understood that the intermediate passivation region 13 can achieve a transition in doping element concentration between the central region 11 and the corner edge region 12, where the donor concentration (such as oxygen donor) is equivalent to the acceptor concentration, and the transition in conductivity type can also be achieved.

[0122] Embodiment 8

[0123] See also Figure 2 , Figure 3 and Figure 4 In some embodiments, the resistivity of the intermediate passivation region 13 is greater than or equal to 1000Ω·cm, for example, 1000Ω·cm, 1010Ω·cm, 1100Ω·cm, 1500Ω·cm, 1800Ω·cm, 2000Ω·cm, 2010Ω·cm, 2100Ω·cm, 2500Ω·cm, 2800Ω·cm.

[0124] In this way, after the solar cell 1000 is manufactured, the surrounding field passivation effect can be further improved in the solar cell 1000, which is beneficial to further improve carrier transport.

[0125] Embodiment 9

[0126] In some embodiments, the doping element of the central region 11 includes an N-type doping element, and the N-type doping element includes at least one of a fifth main group element and a sixth main group element.

[0127] Specifically, the fifth main group elements include nitrogen, phosphorus, arsenic, antimony, and bismuth.

[0128] Specifically, the sixth main group elements include oxygen, sulfur, selenium, tellurium, and polonium.

[0129] That is, the doping element of the central region 11 includes at least one of nitrogen, phosphorus, arsenic, antimony, bismuth, oxygen, sulfur, selenium, tellurium, and polonium. In this way, a variety of doping elements are provided, making the doping elements of the central region 11 more flexible and adaptable to more actual production scenarios.

[0130] In one example, the doping elements of the central region 11 include oxygen, nitrogen, phosphorus, and arsenic. In another example, the doping elements of the central region 11 include oxygen and phosphorus. This is not limited here.

[0131] Embodiment 10

[0132] In some embodiments, the doping element of the corner edge region 12 includes a P-type doping element, and the P-type doping element includes at least one element of the third main group elements.

[0133] Specifically, the third main group elements include boron, aluminum, gallium, indium, and thallium.

[0134] That is, the doping element of the corner edge region 12 includes at least one of boron, aluminum, gallium, indium, and thallium. In this way, multiple doping elements are provided, making the doping elements of the corner edge region 12 more flexible and adaptable to more actual production scenarios.

[0135] In one example, the doping element of the corner edge region 12 includes boron and aluminum. In another example, the doping element of the corner edge region 12 includes boron. This is not limited here.

[0136] Embodiment 11

[0137] See also Figure 4 and Figure 5 In some embodiments, the silicon substrate 10 includes a side edge region 14 , the side edge region 14 is located between two adjacent corner edge regions 12 , and the conductivity type of the side edge region 14 is P type.

[0138] In this way, not only the conductivity type of the corner edge region 12 is P type, but the conductivity type of the side edge region 14 between two adjacent corner edge regions 12 is also P type, so that the side edge region 14 of the silicon substrate 10 can also withstand the contamination of copper ions, further reducing the recombination caused by copper ion contamination of the edge of the silicon substrate 10, which is beneficial to improving the photoelectric conversion efficiency.

[0139] Specifically, the edge region 14 refers to a spatial region extending from a cutting plane of the side length of the silicon substrate 10 to the center line of the silicon substrate 10. It can be understood that the cross section of the silicon rod 100 is circular, and the silicon substrate 10 is formed in a square shape, so the silicon rod 100 must be cut to form a cutting plane at the side length of the square.

[0140] Further, as before, the center line forms a center point on both surfaces in the thickness direction of the silicon substrate 10. Therefore, from the thickness direction of the silicon substrate 10, the edge region 14 extends from the edge line of the side length of the silicon substrate 10 to the center point, as shown in FIG. Figure 4 and Figure 5 That is to say, the edge region 14 is not formed only on the surface of the silicon substrate 10, but is a spatial region with thickness.

[0141] It can be understood that the side edge region 14 can be the region between the corner edge regions 12 on both sides, and can be connected to the corner edge regions 12 on both sides. Figure 5 The side edge region 14 may also be the intersection of the corner edge regions 12 on both sides, such as Figure 4 The edge region 14 may be the long side of the silicon substrate 10 between the corner edge regions 12 on both sides, as shown in FIG. Figure 2 and Figure 3 shown.

[0142] Embodiment 12

[0143] See also Figure 2 and Figure 3 In some embodiments, the surface of the central region 11 in the thickness direction of the silicon substrate 10 is circular, the center of the circle is the center point of the silicon substrate 10, and the radius is 1 / 5-1 / 2 of the side length of the silicon substrate 10. For example, 0.2, 0.25, 0.3, 0.35, 0.4, 0.45, 0.48, 0.5.

[0144] In this way, the size of the central area 11 is within an appropriate range, which can avoid the smaller range of the PN junction formed in the silicon substrate 10 and the poor field passivation effect caused by the size being too small, and can also avoid the smaller range of the corner edge area 12 and the poor recombination effect caused by reducing copper ion contamination of the edge of the silicon substrate 10 due to the size being too large.

[0145] Embodiment 13

[0146] See also Figure 2 , Figure 3 and Figure 4 In some embodiments, the corner edge region 12 includes a first corner side 121 and a second corner side 122 , wherein the length d1 of the first corner side 121 is 1 / 100-1 / 2 of the side length d0 of the silicon substrate 10 , and the length d2 of the second corner side 122 is 1 / 100-1 / 2 of the side length d0 of the silicon substrate 10 .

[0147] In this way, the lengths of the two corner sides of the corner edge region 12 are within an appropriate range, thereby making the corner edge region 12 within an appropriate range, which can avoid the poor recombination effect caused by the reduction of copper ion contamination of the edge of the silicon substrate 10 due to the corner edge region 12 being too small, and can also avoid the small range of the PN junction formed in the silicon substrate 10 and the poor field passivation effect caused by the corner edge region 12 being too large.

[0148] Specifically, the first corner edge 121 and the second corner edge 122 refer to the portion of the long side of the silicon substrate 10 in the corner edge region 12. It can be understood that the long side of the silicon substrate 10 does not include the rounded or chamfered arc side, but refers to the long side at both ends of the rounded or chamfered corner.

[0149] Specifically, the length of the first corner side 121 is, for example, 0.01, 0.08, 0.1, 0.15, 0.2, 0.25, 0.3, 0.35, 0.4, 0.45, or 0.5 of the side length of the silicon substrate 10 .

[0150] Specifically, the length of the second corner edge 122 is, for example, 0.01, 0.08, 0.1, 0.15, 0.2, 0.25, 0.3, 0.35, 0.4, 0.45, or 0.5 of the side length of the silicon substrate 10 .

[0151] Specifically, the length of the first corner side 121 and the length of the second corner side 122 may be the same or different.

[0152] It can be understood that when the length of the first corner edge 121 and the second corner edge 122 is 1 / 2 of the side length of the silicon substrate 10, the conductivity type of all the outer edges of the silicon substrate 10 is P type, such as Figure 4 and Figure 5 shown.

[0153] Embodiment 14

[0154] See also Figure 2 In some embodiments, the ratio of the resistivity of the corner edge region 12 to the resistivity of the central region 11 is greater than or equal to 1.2, for example, 1.2, 1.5, 1.8, 2, 3, 4, 7, 8, etc.

[0155] In this way, the resistivity of the corner edge region 12 is much greater than that of the central region 11, which is beneficial to reduce recombination and improve conversion efficiency. It can be understood that the resistivity of the corner edge region 12 is much greater than that of the central region 11, which means that the P-type doping concentration of the corner edge region 12 is lower than that of the central region 11, so the P-type doping elements, such as group III elements, can be reduced in the corner edge region 12, thereby reducing the compound pairs formed by the group III elements and oxygen in the corner edge region 12 and the recombination caused by the doping elements themselves, thereby improving the conversion efficiency.

[0156] Embodiment 15

[0157] In some embodiments, the resistivity of the central region 11 is greater than or equal to 10Ω·cm, for example, 10Ω·cm, 13Ω·cm, 50Ω·cm, 100Ω·cm, 108Ω·cm, 191Ω·cm, 120Ω·cm, 203Ω·cm, 711Ω·cm, etc.

[0158] In this way, the resistivity of the central region 11 is within an appropriate range, which can avoid the high central oxygen content and high oxygen donor concentration caused by the resistivity of the central region 11 being too small, thereby avoiding the formation of oxygen precipitation in the battery manufacturing process and affecting the battery efficiency and yield.

[0159] Preferably, the resistivity of the central region 11 is greater than or equal to 500Ω·cm, for example, 500Ω·cm, 502Ω·cm, 550Ω·cm, 600Ω·cm, 700Ω·cm, 800Ω·cm, 900Ω·cm, etc. In this way, the battery efficiency and yield are further improved.

[0160] Embodiment 16

[0161] In some embodiments, the resistivity of the corner edge region 12 is greater than or equal to 100Ω·cm, for example, 100Ω·cm, 110Ω·cm, 150Ω·cm, 200Ω·cm, 483Ω·cm, 1059Ω·cm, 3523Ω·cm, 947Ω·cm, 1512Ω·cm, etc.

[0162] In this way, the resistivity of the corner edge region 12 is within an appropriate range, which can prevent the resistivity of the corner edge region 12 from being too small. The resistivity of the corner edge region 12 can be further increased by controlling the rate of reduction of the acceptor doping concentration during the crystal pulling process.

[0163] Preferably, the resistivity of the corner edge region 12 is greater than or equal to 1000Ω·cm, for example, 1000Ω·cm, 1002Ω·cm, 1100Ω·cm, 1200Ω·cm, 1500Ω·cm, 1800Ω·cm, etc. In this way, the battery efficiency is further improved.

[0164] Embodiment 17

[0165] See also Figure 2 In some embodiments, the acceptor impurity concentration of the corner edge region 12 is less than the acceptor impurity concentration of the central region 11 .

[0166] In this way, the recombination caused by copper pollution can be further reduced, which is beneficial to improving the photoelectric conversion efficiency of the solar cell 1000 made based on the silicon substrate 10.

[0167] Specifically, the acceptor impurity refers to a P-type doping element, and the donor impurity refers to an N-type doping element.

[0168] It can be understood that since the acceptor impurity concentration in the corner edge region 12 is lower than the acceptor impurity concentration in the central region 11, the P-type doping elements, such as group III elements, can be reduced in the corner edge region 12, thereby reducing the composite pairs formed by the group III elements and oxygen in the corner edge region 12 and the recombination caused by the doping elements themselves, thereby improving the conversion efficiency.

[0169] It can be understood that since the acceptor impurity concentration of the central region 11 is lower than the donor impurity concentration of the central region 11 , the central region 11 exhibits an N-type.

[0170] Embodiment 18

[0171] See also Figure 2 In some embodiments, the donor impurity concentration of the corner edge region 12 is less than that of the central region 11 , and the donor impurity concentration of the corner edge region 12 is less than that of the acceptor impurity concentration of the corner edge region 12 .

[0172] In this way, it is ensured that the conductivity type of the corner edge region 12 of the silicon substrate 10 is P type, and the conductivity type of the central region 11 is N type.

[0173] Embodiment 19

[0174] See also Figure 2 In some embodiments, the ratio of the acceptor impurity concentration in the central region 11 to the acceptor impurity concentration in the corner edge region 12 is 1.01-10.

[0175] In this way, the ratio of the acceptor impurity concentration in the central area 11 to the acceptor impurity concentration in the corner edge area 12 is in an appropriate range, greater than 1, which can avoid the situation where the crystallization interface is too flat, the pulling speed is slow, and the yield is low due to a too small ratio, and can also avoid the situation where the crystallization interface is more concave toward the melt, the thermal stress is large, and it is easy to break into polycrystalline due to a too large ratio.

[0176] Embodiment 19

[0177] See also Figure 2 In some embodiments, the acceptor impurity concentration in the corner edge region 12 is less than or equal to 10 15 atoms / cm 3 For example, 1×10 15 atoms / cm 3 , 0.8×10 15 atoms / cm 3 , 0.5×10 15 atoms / cm 3 , 0.1×1015 atoms / cm 3 wait.

[0178] In this way, the acceptor impurity concentration in the corner edge region 12 is within an appropriate range, which can avoid the excessive acceptor impurity concentration in the corner edge region 12 causing the formation of complex pairs with oxygen and the large number of complexes caused by the doping elements themselves, which is beneficial to improving the conversion efficiency.

[0179] Embodiment 20

[0180] See also Fig. 9 In some embodiments, the doping elements in the central region 11 and the corner edge region 12 both include P-type doping elements and N-type doping elements, the doping concentration of the N-type doping elements in the central region 11 is greater than the doping concentration of the P-type doping elements in the central region 11, and the doping concentration of the P-type doping elements in the corner edge region 12 is greater than the doping concentration of the N-type doping elements in the corner edge region 12; the absolute value K1 of the slope of the concentration curve of the N-type doping element is greater than the absolute value K2 of the slope of the concentration curve of the P-type doping element; the abscissa of the concentration curve of the N-type doping element is the distance from the test position of the silicon substrate 10 to the center point of the silicon substrate 10, and the ordinate is the concentration of the N-type doping element at the test position; the abscissa of the concentration curve of the P-type doping element is the distance from the test position to the center point of the silicon substrate 10, and the ordinate is the concentration of the P-type doping element at the test position.

[0181] In this way, since the absolute value of the slope K1 of the concentration curve of the N-type doping element is greater than the absolute value of the slope K2 of the concentration curve of the P-type doping element, the concentration of the N-type doping element can drop faster than the concentration of the P-type doping element from the center point of the silicon substrate 10 to the outside, thereby ensuring that the conductivity type of the central area 11 is N-type, while the conductivity type of the corner edge area 12 is P-type.

[0182] Specifically, in Fig. 9 In the example, 0 corresponds to the center point of the silicon substrate 10, and R corresponds to the position in the silicon substrate 10 where the distance to the center point is the largest. Obviously, at the center point of the silicon substrate 10, the doping concentration N1 of the N-type doping element is greater than the doping concentration P1 of the P-type doping element, which ensures that the conductivity type in the central area 11 is N-type. Obviously, at the position in the silicon substrate 10 where the distance to the center point is the largest, that is, the very edge of the corner edge area 12, the doping concentration N2 of the N-type doping element is less than the doping concentration P2 of the P-type doping element, which ensures that the conductivity type at the very edge of the corner edge area 12 is P-type. Obviously, the intersection of the concentration curve of the N-type doping element and the concentration curve of the P-type doping element is located in the middle area 13, at which time the concentrations of the N-type doping element and the P-type doping element are equal.

[0183] Embodiment 21

[0184] See also Fig. 9 In some embodiments, the absolute value of the slope of the concentration curve of the N-type doping element and the absolute value of the slope of the concentration curve of the P-type doping element satisfy the following formula:

[0185]

[0186] Among them, a is the side length of the silicon substrate, N1 is the doping concentration of the N-type doping element in the central area 11, P1 is the doping concentration of the P-type doping element in the central area 11, K1 is the absolute value of the slope of the concentration curve of the N-type doping element, and K2 is the absolute value of the slope of the concentration curve of the P-type doping element.

[0187] In this way, the difference between the absolute value K1 of the slope of the concentration curve of the N-type doping element and the absolute value K2 of the slope of the concentration curve of the P-type doping element is within an appropriate range, which can avoid the central area 11 being too small due to a large difference, and can also avoid the central area 11 being too large due to a small difference or even the absence of the P-type corner edge area 12 in the silicon substrate.

[0188] Embodiment 22

[0189] The battery assembly of the embodiment of the present application includes the solar cell 1000 of any one of Embodiments 1 to 21.

[0190] In the battery assembly of the embodiment of the present application, since the conductivity type of the central region 11 of the silicon substrate 10 in the solar cell 1000 is N-type, and the conductivity type of the corner edge region 12 is P-type, in the process of manufacturing the solar cell 1000 based on the silicon substrate 10, the corner edge region 12 with the conductivity type of P-type is used to bear the contamination of the edge of the silicon substrate 10 by copper ions, thereby reducing the recombination caused by the copper ion contamination of the edge of the silicon substrate 10. At the same time, the first doping layer 21 forms a high-low junction and a PN junction with the central region 11 and the corner edge region 12, respectively, or forms a PN junction and a high-low junction with the central region 11 and the corner edge region 12, respectively, so that the minority carriers in the interior can become majority carriers after entering the edge, and the minority carriers at the edge can become majority carriers after entering the central region 11, thereby improving the carrier lifetime. At the same time, a strong electric field is formed between the central region 11 and the corner edge region 12, and a fully enclosed field passivation effect is formed above and below and around the central region 11. Moreover, the conductivity types of the central region 11 and the corner edge region 12 are N-type and P-type respectively, which can form a PN junction in the silicon substrate 10, and form a better field passivation effect in the solar cell 1000, which is beneficial to carrier transmission. In this way, the photoelectric conversion efficiency of the solar cell 1000 is improved.

[0191] In this embodiment, multiple solar cells 1000 in the battery assembly can be connected in series in sequence to form a battery string, thereby realizing the series bus output of the current. For example, the series connection of the battery cells can be realized by setting welding strips (bus bars, interconnecting strips), conductive backplanes, etc.

[0192] It is understandable that in such an embodiment, the battery assembly may further include a metal frame, a back plate, photovoltaic glass and an adhesive film. The adhesive film may be filled between the front and back of the solar cell 1000 and the photovoltaic glass, adjacent cells, etc. As a filler, it may be a transparent colloid with good light transmittance and aging resistance. For example, the adhesive film may be an EVA adhesive film or a POE adhesive film. The specific selection may be based on actual conditions and is not limited here.

[0193] Photovoltaic glass can cover the adhesive film on the front side of the solar cell 1000. The photovoltaic glass can be ultra-white glass, which has high light transmittance, high transparency, and excellent physical, mechanical and optical properties. For example, the light transmittance of ultra-white glass can reach more than 92%, which can protect the solar cell 1000 without affecting the efficiency of the solar cell 1000 as much as possible. At the same time, the adhesive film can bond the photovoltaic glass and the solar cell 1000 together, and the presence of the adhesive film can seal and insulate the solar cell 1000 and make it waterproof and moisture-proof.

[0194] The backplane can be attached to the adhesive film on the back of the solar cell 1000. The backplane can protect and support the solar cell 1000 and has reliable insulation, water resistance and aging resistance. There are multiple options for the backplane, which can usually be tempered glass, organic glass, aluminum alloy TPT composite adhesive film, etc. It can be set according to specific circumstances and is not limited here. The whole composed of the backplane, solar cell 1000, adhesive film and photovoltaic glass can be set on a metal frame. The metal frame serves as the main external support structure of the entire battery assembly and can stably support and install the battery assembly. For example, the battery assembly can be installed at the required location through the metal frame.

[0195] Embodiment 23

[0196] The photovoltaic system of the embodiment of the present application includes the battery assembly of embodiment twenty-one.

[0197] In the photovoltaic system of the embodiment of the present application, since the conductivity type of the central region 11 of the silicon substrate 10 in the solar cell 1000 is N-type, and the conductivity type of the corner edge region 12 is P-type, in the process of manufacturing the solar cell 1000 based on the silicon substrate 10, the corner edge region 12 with the conductivity type of P-type is used to withstand the contamination of the edge of the silicon substrate 10 by copper ions, thereby reducing the recombination caused by the copper ion contamination of the edge of the silicon substrate 10. At the same time, the first doping layer 21 forms a high-low junction and a PN junction with the central region 11 and the corner edge region 12, respectively, or forms a PN junction and a high-low junction with the central region 11 and the corner edge region 12, respectively, so that the minority carriers in the interior can become majority carriers after entering the edge, and the minority carriers at the edge can become majority carriers after entering the central region 11, thereby improving the carrier lifetime. At the same time, a strong electric field is formed between the central region 11 and the corner edge region 12, and a fully enclosed field passivation effect is formed above and below and around the central region 11. Moreover, the conductivity types of the central region 11 and the corner edge region 12 are N-type and P-type respectively, which can form a PN junction in the silicon substrate 10, and form a better field passivation effect in the solar cell 1000, which is beneficial to carrier transmission. In this way, the photoelectric conversion efficiency of the solar cell 1000 is improved.

[0198] In this embodiment, the photovoltaic system can be applied to photovoltaic power stations, such as ground power stations, rooftop power stations, water power stations, etc., and can also be applied to equipment or devices that use solar energy to generate electricity, such as user solar power supplies, solar street lights, solar cars, solar buildings, etc. Of course, it can be understood that the application scenarios of the photovoltaic system are not limited to this, that is to say, the photovoltaic system can be applied in all fields that require solar energy to generate electricity. Taking the photovoltaic power generation system network as an example, the photovoltaic system may include a photovoltaic array, a junction box and an inverter. The photovoltaic array may be an array combination of multiple battery components. For example, multiple battery components can form multiple photovoltaic arrays. The photovoltaic array is connected to the junction box. The junction box can converge the current generated by the photovoltaic array. The converged current flows through the inverter and is converted into the alternating current required by the mains power grid, and then connected to the mains network to realize solar power supply.

[0199] The following will use a battery in the related art as a comparative example for comparison with the solar cell 1000 of the present application.

[0200] A battery in the related art is used as comparative example 1. The conductivity type of the central area and the corner edge area of ​​the silicon wafer is N-type. The battery made based on this silicon wafer has an open circuit voltage of 0.711V and a short circuit current of 42.7mA / cm 2 , the filling factor is 0.842 and the conversion efficiency is 25.56%.

[0201] Another battery in the related art is used as comparative example 2. The conductivity type of the central area and the corner edge area of ​​the silicon wafer is P-type. The battery made based on this silicon wafer has an open circuit voltage of 0.715V and a short circuit current of 42.8mA / cm 2 , the filling factor is 0.841 and the conversion efficiency is 25.74%.

[0202] The solar cell 1000 in one example of the present application is a TopCon cell, the conductivity type of the central area 11 is N-type, the conductivity type of the corner edge area 12 is P-type, the central area 11 is centered at the center point of the silicon wafer, and the radius is 1 / 5 of the side length of the silicon wafer. The open circuit voltage is 0.723V, and the short circuit current is 42.7mA / cm 2 , the filling factor is 0.848 and the conversion efficiency is 26.18%.

[0203] The solar cell 1000 in one example of the present application is a TopCon cell, the conductivity type of the central area 11 is N-type, the conductivity type of the corner edge area 12 is P-type, the central area 11 is centered at the center point of the silicon wafer, and the radius is 1 / 2 of the side length of the silicon wafer. The open circuit voltage is 0.727V, and the short circuit current is 42.8mA / cm 2 , the filling factor is 0.852 and the conversion efficiency is 26.51%.

[0204] Obviously, compared with the battery in the related art, the solar cell 1000 of the embodiment of the present application has a higher open circuit voltage, the same short circuit current, a higher fill factor, and a significantly improved conversion efficiency.

[0205] In the description of this specification, the description with reference to the terms "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiments or examples are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0206] In addition, the above are only preferred embodiments of the present application and are not intended to limit the present application. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims

1. A solar cell, characterized in that: include: A silicon substrate, wherein the silicon substrate comprises a central region and a corner edge region, the central region is of N-type conductivity, and the corner edge region is of P-type conductivity; A first doped layer, disposed on the first surface of the silicon substrate; The conductivity type of the first doped layer is N-type, forming a high-low junction with the central area and a PN junction with the corner edge area; or, the conductivity type of the first doped layer is P-type, forming a PN junction with the central area and a high-low junction with the corner edge area.

2. The solar cell according to claim 1, characterized in that The first doping layer is a diffusion doping layer.

3. The solar cell according to claim 1, characterized in that The first doped layer is a doped polysilicon layer or a doped amorphous silicon layer. A first passivation layer is provided between the first doped layer and the silicon substrate. The first passivation layer is an intrinsic amorphous silicon layer or a silicon oxide layer.

4. The solar cell according to claim 1, characterized in that The first doped layer is a doped polysilicon layer, a first passivation layer is arranged between the first doped layer and the silicon substrate, the first passivation layer is an intrinsic amorphous silicon layer or a silicon oxide layer, the silicon substrate forms an inner diffusion layer, a high-low junction is formed between the inner diffusion layer and the doped polysilicon, and the inner diffusion layer forms a high-low junction or a PN junction with the silicon substrate.

5. The solar cell according to claim 1, characterized in that: The solar cell comprises a second doped layer, and the second doped layer is arranged on the second surface of the silicon substrate; When the conductivity type of the first doped layer is N-type, the conductivity type of the second doped layer is P-type, a PN junction is formed between the second doped layer and the central area, and a high-low junction is formed between the second doped layer and the corner edge area; or, when the conductivity type of the first doped layer is P-type, the conductivity type of the second doped layer is N-type, a high-low junction is formed between the second doped layer and the central area, and a PN junction is formed between the second doped layer and the corner edge area.

6. The solar cell according to claim 5, characterized in that: The projections of the high-low junction formed between the first doped layer and the central region and the PN junction formed between the second doped layer and the central region in the thickness direction of the solar cell completely overlap; Alternatively, the projections of the PN junction formed between the first doped layer and the central region and the high-low junction formed between the second doped layer and the central region in the thickness direction of the solar cell completely overlap.

7. The solar cell according to claim 1, characterized in that The silicon substrate includes an intermediate passivation region, which is located between the central region and the corner edge region, and has a resistivity greater than that of the central region and greater than that of the corner edge region.

8. The solar cell according to claim 7, characterized in that: The resistivity of the intermediate passivation region is greater than or equal to 1000Ω·cm.

9. The solar cell according to claim 1, characterized in that: The silicon substrate comprises a side edge region, the side edge region is located between two adjacent corner edge regions, and the conductivity type of the side edge region is P type.

10. The solar cell according to claim 1, characterized in that: The surface of the central area in the thickness direction of the silicon substrate is circular, the center of the circle is the center point of the silicon substrate, and the radius is 1 / 5-1 / 2 of the side length of the silicon substrate.

11. The solar cell according to claim 1, characterized in that: The corner edge region includes a first corner side and a second corner side, the length of the first corner side is 1 / 100-1 / 2 of the side length of the silicon substrate, and the length of the second corner side is 1 / 100-1 / 2 of the side length of the silicon substrate.

12. The solar cell according to claim 1, characterized in that A ratio of the resistivity of the corner edge region to the resistivity of the central region is greater than or equal to 1.

2.

13. The solar cell according to claim 1, characterized in that The resistivity of the central region is greater than or equal to 10Ω·cm.

14. The solar cell according to claim 1, characterized in that The resistivity of the corner edge region is greater than or equal to 100Ω·cm.

15. A battery assembly, characterized in that: A solar cell comprising the solar cell according to any one of claims 1 to 14.

16. A photovoltaic system, characterized in that: A battery assembly comprising the battery assembly of claim 15.

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