Synchronous rectification PWM drive circuit structure

Abstract

The utility model relates to a synchronous rectification PWM (Pulse Width Modulation) drive circuit structure, which comprises an XOR and NAND logic circuit U1, a filtering delay circuit and an enabling logic drive circuit. A PWM signal can be efficiently and accurately enabled and turned off, a main circuit power device is protected, the service life of the power device is prolonged, and the reliability of whole equipment is improved; the defect of delay dead time of the main power tube and the synchronous rectifier tube is made up; a synchronous rectifier tube PWM driving signal is obtained by ingeniously using the logic gate relation of primary and secondary PWM of the transformer, it is ensured that primary energy and secondary energy of a main transformer of a main circuit need safe, reliable and synchronous energy transmission, and a main power device is prevented from being damaged.

Description

Technical Field

[0001] The utility model relates to a power supply control technology, in particular to a synchronous rectification PWM drive circuit structure. Background Art

[0002] In recent years, the requirements for power conversion efficiency and energy saving in industrial energy such as low-voltage and high-current electroplating, electrolysis, and metal smelting have become increasingly higher. At present, the power switches of most switching power supplies are composed of IGBTs and rectifier diodes, and rectifier diodes are used for rectification. However, diodes have the disadvantages of large voltage drop, resulting in high conduction losses and large energy losses. At the same time, it is necessary to control the primary energy and secondary energy of the main circuit transformer to transmit energy safely and reliably synchronously. Utility Model Content

[0003] In view of the above situation, it is necessary to provide a synchronous rectification PWM drive circuit structure that solves at least one of the above problems, including an XOR and NOT logic circuit U1, a filter delay circuit and an enable logic drive circuit;

[0004] The four PWM signals generated by the PWM main control chip U3 enter the XOR and NOT logic circuit U1;

[0005] The XOR and NOT logic circuit U1 is connected in series with the filter delay circuit;

[0006] The filtering delay circuit is connected in series with the enabling logic driving circuit;

[0007] The XOR and NOT logic circuit U1 is used to take the XOR and NOT of the PWM signal and generate a transformer positive and negative cycle synchronous rectifier tube drive signal;

[0008] The filtering delay circuit is used to obtain a synchronous rectification PWM signal for driving the secondary synchronous rectification MOS tube of the main transformer to turn on and off;

[0009] The enabling logic driving circuit is used to control the on and off of the synchronous rectification PWM signal.

[0010] As a further solution of the utility model: the XOR and NOT logic circuit U1 includes four two-input NOR gates U1A, U1B, U1C, and U1D;

[0011] The NOR gate U1A is connected in series with the NOR gate U1C, and the NOR gate U1D is connected in series with the NOR gate U1B;

[0012] The input terminals A and B of the NOR gate U1A are respectively connected to the No. 7 and No. 8 pins of the PWM main control chip U3 for receiving PWM-A and PWM-C signals, and the output terminal Y of the NOR gate U1A is simultaneously connected to the input terminals A and B of the NOR gate U1C;

[0013] The input terminals A and B of the NOR gate U1D are respectively connected to the No. 6 and No. 5 pins of the PWM main control chip U3 for receiving PWM-B and PWM-D signals, and the output terminal Y of the NOR gate U1D is simultaneously connected to the input terminals A and B of the NOR gate U1B;

[0014] The output terminals Y of the NOR gate U1C and the NOR gate U1B are connected to the in-A pin and the in-B pin of the driving latch chip U2 of the enabling logic driving circuit respectively through the filtering delay circuit.

[0015] As a further solution of the utility model: the filtering delay circuit includes resistors R3 and R9 and capacitors C2 and C4;

[0016] The resistor R3 is connected in series between the output terminal Y of the NOR gate U1C and the in-A pin of the driving latch chip U2, and the capacitor C2 is connected in parallel to the ground between the resistor R3 and the in-A pin to generate a synchronous rectification signal PWM-SA to enter the in-A pin;

[0017] The resistor R9 is connected in series between the output terminal Y of the NOR gate U1B and the in-B pin of the driving latch chip U2, and the capacitor C4 is connected in parallel to the ground between the resistor R9 and the in-B pin to generate a synchronous rectification signal PWM-SB and enter the in-B pin.

[0018] As a further solution of the utility model: the enabling logic driving circuit further includes a fault signal detection circuit;

[0019] The fault signal detection circuit comprises a transistor Q1, the base of the transistor Q1 is connected to the fault signal source via a resistor R10;

[0020] The collector of the transistor Q1 is connected to the power supply and the ENA pin and the ENB pin of the driving latch chip U2;

[0021] The emitter of the transistor Q1 is grounded, and the GND pin of the driving latch chip U2 is connected to the emitter of the transistor Q1;

[0022] The out-A pin and the out-B pin of the driving latch chip U2 are respectively connected to the gate of the synchronous rectifier tube, and output PWM-SRA and PWM-SRB signals.

[0023] The utility model proposes to select an enable driving logic chip (U2). When an external Fault signal is detected, Q is turned on, and the enable level of the U2 driving logic chip is low, U2 automatically and quickly and accurately turns off the synchronous rectification PWM (PWM_SRA, PWM_SRB) signal, and the energy is transferred by the main MOS tube body diode, so that the main circuit transformer rectification MOS tube power device can be protected from damage, greatly improving the reliability of the whole machine power supply. The R3, C2 filter delay circuit and the R9, C4 filter delay circuit respectively delay the U3-10 output pin signal and the U3-4 output signal with a time constant τ, and obtain PWM_SA and PWMSB with a certain dead time relative to the main transformer primary main power tube drive (PWM_A, PWM_B, PWM_C, PWM_D). PWM_SA and PWMSB are used to drive the main transformer secondary synchronous rectification MOS tube to open and close. This method avoids the risk of the main transformer primary power tube and secondary power tube being short-circuited and causing the tube to explode, improving The stability of the power supply equipment; using the XOR and NOT gate logic circuit (U1), taking PWM_A and PWM_C XOR and NOT, and then through the NOT gate to obtain the transformer positive cycle synchronous rectifier tube drive PWM_SA; taking PWM_B and PWM_D XOR and NOT, and then through the NOT gate to obtain the transformer negative cycle synchronous rectifier tube drive PWM_SB, the circuit has clear logic, combined with the energy flow characteristics of the phase-shifted full-bridge main topology circuit, accurately and reliably completes the synchronous rectification energy transfer, reduces the voltage drop loss of the MOS tube and improves the conversion efficiency of the whole machine, and achieves the "green" power grid and energy-saving goals. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 It is a circuit schematic diagram of an embodiment of the utility model;

[0025] Figure 2 This is a timing diagram of synchronous rectification signal generation according to an embodiment of the utility model. DETAILED DESCRIPTION

[0026] In order to make the purpose, technical solution and advantages of the utility model more clear, the utility model is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the utility model and are not used to limit the utility model.

[0027] In the description of the present invention, unless otherwise specified, "multiple" means two or more; the terms "center", "longitudinal", "lateral", "up", "down", "left", "right", "inside", "outside", "front end", "rear end", "head", "tail", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", "third", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance.

[0028] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installation", "connection" and "connection" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be an indirect connection through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood by specific circumstances.

[0029] like Figure 1-Figure 2 As shown, a synchronous rectification PWM drive circuit structure includes an XOR and NOT logic circuit U1, a filter delay circuit and an enable logic drive circuit;

[0030] The four PWM signals generated by the PWM main control chip U3 enter the XOR and NOT logic circuit U1;

[0031] The XOR and NOT logic circuit U1 is connected in series with the filter delay circuit;

[0032] The filtering delay circuit is connected in series with the enabling logic driving circuit;

[0033] The XOR and NOT logic circuit U1 is used to take the XOR and NOT of the PWM signal and generate a transformer positive and negative cycle synchronous rectifier tube drive signal;

[0034] The filtering delay circuit is used to obtain a synchronous rectification PWM signal for driving the secondary synchronous rectification MOS tube of the main transformer to turn on and off;

[0035] The enabling logic driving circuit is used to control the on and off of the synchronous rectification PWM signal.

[0036] As a further solution of the utility model: the XOR and NOT logic circuit U1 includes four two-input NOR gates U1A, U1B, U1C, and U1D;

[0037] The NOR gate U1A is connected in series with the NOR gate U1C, and the NOR gate U1D is connected in series with the NOR gate U1B;

[0038] The input terminals A and B of the NOR gate U1A are respectively connected to the No. 7 and No. 8 pins of the PWM main control chip U3 for receiving PWM-A and PWM-C signals, and the output terminal Y of the NOR gate U1A is simultaneously connected to the input terminals A and B of the NOR gate U1C;

[0039] The input terminals A and B of the NOR gate U1D are respectively connected to the No. 6 and No. 5 pins of the PWM main control chip U3 for receiving PWM-B and PWM-D signals, and the output terminal Y of the NOR gate U1D is simultaneously connected to the input terminals A and B of the NOR gate U1B;

[0040] The output terminals Y of the NOR gate U1C and the NOR gate U1B are connected to the in-A pin and the in-B pin of the driving latch chip U2 of the enabling logic driving circuit respectively through the filtering delay circuit.

[0041] The utility model ingeniously uses an XOR and NOT gate logic circuit (U1), takes PWM_A and PWM_C XOR and then obtains the transformer positive cycle synchronous rectifier tube drive PWM_SA through a NOT gate; takes PWM_B and PWM_D XOR and then obtains the transformer negative cycle synchronous rectifier tube drive PWM_SB through a NOT gate. The circuit has clear logic and combines the energy flow characteristics of the phase-shifted full-bridge main topology circuit to accurately and reliably complete the synchronous rectification energy transfer, reduce the voltage drop loss of the MOS tube and improve the conversion efficiency of the whole machine, and achieve the "green" power grid and energy-saving goals.

[0042] As a further solution of the utility model: the filtering delay circuit includes resistors R3 and R9 and capacitors C2 and C4;

[0043] The resistor R3 is connected in series between the output terminal Y of the NOR gate U1C and the in-A pin of the driving latch chip U2, and the capacitor C2 is connected in parallel to the ground between the resistor R3 and the in-A pin to generate a synchronous rectification signal PWM-SA to enter the in-A pin;

[0044] The resistor R9 is connected in series between the output terminal Y of the NOR gate U1B and the in-B pin of the driving latch chip U2, and the capacitor C4 is connected in parallel to the ground between the resistor R9 and the in-B pin to generate a synchronous rectification signal PWM-SB and enter the in-B pin.

[0045] The R3, C2 filtering delay circuit and the R9, C4 filtering delay circuit proposed in the utility model respectively delay the U3-10 output pin signal and the U3-4 output signal by a time constant τ, and obtain PWM_SA and PWMSB with a certain dead time relative to the primary main power tube drive (PWM_A, PWM_B, PWM_C, PWM_D) of the main transformer. PWM_SA and PWMSB are used to drive the secondary synchronous rectification MOS tube of the main transformer to open and close. This method avoids the risk of the primary power tube and the secondary power tube of the main transformer being short-circuited and causing the tube to explode, thereby improving the stability of the power supply equipment.

[0046] As a further solution of the utility model: the enabling logic driving circuit further includes a fault signal detection circuit;

[0047] The fault signal detection circuit comprises a transistor Q1, the base of the transistor Q1 is connected to the fault signal source via a resistor R10;

[0048] The collector of the transistor Q1 is connected to the power supply and the ENA pin and the ENB pin of the driving latch chip U2;

[0049] The emitter of the transistor Q1 is grounded, and the GND pin of the driving latch chip U2 is connected to the emitter of the transistor Q1;

[0050] The out-A pin and the out-B pin of the driving latch chip U2 are respectively connected to the gate of the synchronous rectifier tube, and output PWM-SRA and PWM-SRB signals.

[0051] The utility model proposes to select an enable driving logic chip (U2). When an external Fault signal is detected, Q is turned on, and the enable level of the U2 driving logic chip is low, then U2 automatically, quickly and accurately turns off the synchronous rectification PWM (PWM_SRA, PWM_SRB) signal, and the energy is transferred by the main MOS tube body diode, so that the main circuit transformer rectification MOS tube power device can be protected from damage, thereby greatly improving the reliability of the power supply of the whole machine.

[0052] In the above embodiment, the model of U1 is CD4001B, the model of U2 is UCC27524DR, and the model of U3 is UCC2895.

[0053] The above description is only a preferred embodiment of the present invention and does not constitute any form of limitation to the present invention. Although the present invention has been disclosed as a preferred embodiment as above, it is not intended to limit the present invention. Any technician familiar with the profession can make some changes or modify the technical contents disclosed above into equivalent embodiments without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention still fall within the scope of the technical solution of the present invention.

Claims

1. A synchronous rectification PWM drive circuit structure, characterized in that: It includes an XOR and NOT logic circuit U1, a filter delay circuit and an enable logic drive circuit; The four PWM signals generated by the PWM main control chip U3 enter the XOR and NOT logic circuit U1; The XOR and NOT logic circuit U1 is connected in series with the filter delay circuit; The filtering delay circuit is connected in series with the enabling logic driving circuit; The XOR and NOT logic circuit U1 is used to take the XOR and NOT of the PWM signal and generate a transformer positive and negative cycle synchronous rectifier tube drive signal; The filtering delay circuit is used to obtain a synchronous rectification PWM signal for driving the secondary synchronous rectification MOS tube of the main transformer to turn on and off; The enabling logic driving circuit is used to control the on and off of the synchronous rectification PWM signal.

2. The synchronous rectification PWM driving circuit structure according to claim 1, characterized in that: The XOR and NOR logic circuit U1 includes four two-input NOR gates U1A, U1B, U1C, and U1D; The NOR gate U1A is connected in series with the NOR gate U1C, and the NOR gate U1D is connected in series with the NOR gate U1B; The input terminals A and B of the NOR gate U1A are respectively connected to the No. 7 and No. 8 pins of the PWM main control chip U3 for receiving PWM-A and PWM-C signals, and the output terminal Y of the NOR gate U1A is simultaneously connected to the input terminals A and B of the NOR gate U1C; The input terminals A and B of the NOR gate U1D are respectively connected to the No. 6 and No. 5 pins of the PWM main control chip U3 for receiving PWM-B and PWM-D signals, and the output terminal Y of the NOR gate U1D is simultaneously connected to the input terminals A and B of the NOR gate U1B; The output terminals Y of the NOR gate U1C and the NOR gate U1B are connected to the in-A pin and the in-B pin of the driving latch chip U2 of the enabling logic driving circuit respectively through the filtering delay circuit.

3. The synchronous rectification PWM driving circuit structure as claimed in claim 2, characterized in that: The filtering delay circuit includes resistors R3 and R9 and capacitors C2 and C4; The resistor R3 is connected in series between the output terminal Y of the NOR gate U1C and the in-A pin of the driving latch chip U2, and the capacitor C2 is connected in parallel to the ground between the resistor R3 and the in-A pin to generate a synchronous rectification signal PWM-SA to enter the in-A pin; The resistor R9 is connected in series between the output terminal Y of the NOR gate U1B and the in-B pin of the driving latch chip U2, and the capacitor C4 is connected in parallel to the ground between the resistor R9 and the in-B pin to generate a synchronous rectification signal PWM-SB and enter the in-B pin.

4. The synchronous rectification PWM driving circuit structure as claimed in claim 2, characterized in that: The enabling logic driving circuit also includes a fault signal detection circuit; The fault signal detection circuit comprises a transistor Q1, the base of the transistor Q1 is connected to the fault signal source via a resistor R10; The collector of the transistor Q1 is connected to the power supply and the ENA pin and the ENB pin of the driving latch chip U2; The emitter of the transistor Q1 is grounded, and the GND pin of the driving latch chip U2 is connected to the emitter of the transistor Q1; The out-A pin and the out-B pin of the driving latch chip U2 are respectively connected to the gate of the synchronous rectifier tube, and output PWM-SRA and PWM-SRB signals.

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