High-voltage interlocking detection circuit

Abstract

The utility model discloses a high-voltage interlocking detection circuit, which comprises a first low-pass filter circuit connected with a first high-voltage signal end and a second low-pass filter circuit connected with a second high-voltage signal end, wherein the joint between the first high-voltage signal end and the first low-pass filter circuit is also provided with a level signal injection end, and the joint between the second high-voltage signal end and the second low-pass filter circuit is also provided with a level signal feedback end; the first high-voltage signal end and the second high-voltage signal end are plugs in high-voltage interlocking connection respectively; the high-voltage interlocking detection device is simple in structure, reliable in high-voltage interlocking detection effect, low in cost and suitable for large-scale popularization and application.

Description

Technical Field

[0001] The utility model belongs to the field of vehicle drive control, and in particular relates to a high-voltage interlock detection circuit. Background Art

[0002] In the field of automobile drive control, in order to achieve a safe driving effect, the prior art usually sets a high-voltage interlock detection circuit between the battery and the load. However, the existing high-voltage interlock detection circuit generally has the defects of complex circuit structure and high detection cost.

[0003] Therefore, the applicant hopes to seek technical solutions to solve the technical problems. Utility Model Content

[0004] In view of this, the purpose of the utility model is to provide a high-voltage interlock detection circuit with a simple structure, reliable high-voltage interlock detection effect, low cost, and suitable for large-scale promotion and application.

[0005] The technical solution adopted by the utility model is as follows:

[0006] A high-voltage interlock detection circuit comprises a first low-pass filter circuit connected to a first high-voltage signal terminal and a second low-pass filter circuit connected to a second high-voltage signal terminal; wherein,

[0007] A level signal injection terminal is also provided at the connection between the first high-voltage signal terminal and the first low-pass filter circuit, and a level signal feedback terminal is also provided at the connection between the second high-voltage signal terminal and the second low-pass filter circuit;

[0008] The first high-voltage signal terminal and the second high-voltage signal terminal are respectively high-voltage interlocking connection plugs.

[0009] Preferably, the level signal injection terminal is electrically connected to a battery management system BMS, and the battery management system BMS provides a level signal.

[0010] Preferably, the level signal feedback terminal is electrically connected to a battery management system BMS, and feeds back a level signal to the battery management system BMS.

[0011] Preferably, the first low-pass filter circuit includes a first chip resistor and a first capacitor, wherein the first chip resistor is connected between the first high-voltage signal terminal and ground; and the first capacitor is connected between the first high-voltage signal terminal and ground.

[0012] Preferably, the resistance range of the first chip resistor is 250-350 kilo-ohms, and the capacitance of the first capacitor is 0.5-1.5 nF.

[0013] Preferably, the first chip resistor adopts a 0603 packaging structure, and the first capacitor adopts a multilayer ceramic capacitor.

[0014] Preferably, the second low-pass filter circuit includes a second chip resistor and a second capacitor, wherein the second chip resistor is connected between the second high-voltage signal terminal and ground; and the second capacitor is connected between the second high-voltage signal terminal and ground.

[0015] Preferably, the resistance range of the second chip resistor is 250-350 kilo-ohms, and the capacitance of the second capacitor is 0.5-1.5nF; at the same time, the resistance of the second chip resistor is equal to the resistance of the first chip resistor, and the capacitance of the second capacitor is equal to the capacitance of the first capacitor.

[0016] Preferably, the second chip resistor adopts a 0603 packaging structure, and the second capacitor adopts a multilayer ceramic capacitor.

[0017] Preferably, the battery management system BMS is a battery management system BMS for an electric vehicle.

[0018] It should be specially noted that the “0603 packaging structure” referred to in the entire application refers to a well-known packaging name for a surface-mount component; and the “BMS” referred to in the entire application is the abbreviation of the English “Battery Management System”.

[0019] The utility model proposes a first low-pass filter circuit connected to a first high-voltage signal terminal and a second low-pass filter circuit connected to a second high-voltage signal terminal, and a level signal injection terminal is also provided at the connection between the first high-voltage signal terminal and the first low-pass filter circuit, and a level signal feedback terminal is also provided at the connection between the second high-voltage signal terminal and the second low-pass filter circuit; when the present application is actually working, the battery management system BMS sends a level signal to the level signal injection terminal CON7-1, passes through the first high-voltage signal terminal, and is filtered by the first low-pass filter circuit and the second low-pass filter circuit, and then returns to the second high-voltage signal terminal and the level signal feedback terminal; when the battery management system BMS detects that the level signal feedback terminal returns a level signal, it confirms that the high-voltage interlock signal is intact, and there is no high-voltage plug disconnection or poor contact, and then the load is energized (otherwise the load is not energized), ensuring the safety of vehicles and personnel, with a simple structure, reliable high-voltage interlock detection effect, low cost, and suitable for large-scale promotion and application. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 It is a schematic diagram of a high voltage interlock detection circuit in a specific implementation manner of the utility model. DETAILED DESCRIPTION

[0021] An embodiment of the utility model discloses a high-voltage interlock detection circuit, comprising a first low-pass filter circuit connected to a first high-voltage signal terminal and a second low-pass filter circuit connected to a second high-voltage signal terminal; wherein a level signal injection terminal is also provided at the connection between the first high-voltage signal terminal and the first low-pass filter circuit, and a level signal feedback terminal is also provided at the connection between the second high-voltage signal terminal and the second low-pass filter circuit; the first low-pass filter circuit and the second low-pass filter circuit are electrically connected.

[0022] In order to more clearly illustrate the embodiments of the utility model or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the utility model. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0023] See also Figure 1 As shown, this embodiment proposes a high-voltage interlock detection circuit, including a first low-pass filter circuit connected to the first high-voltage signal terminal J3-1 and a second low-pass filter circuit connected to the second high-voltage signal terminal J3-2; wherein, a level signal injection terminal CON7-1 is further provided at the connection between the first high-voltage signal terminal J3-1 and the first low-pass filter circuit, and a level signal feedback terminal CON8-1 is further provided at the connection between the second high-voltage signal terminal J3-2 and the second low-pass filter circuit; the first high-voltage signal terminal J3-1 and the second high-voltage signal terminal J3-2 are respectively high-voltage interlock connection plugs; in actual operation, the first low-pass filter circuit filters the HV_side signal of the first high-voltage signal terminal J3-1 and the level signal injection terminal CON7-1; the second low-pass filter circuit filters the HV_side signal of the second high-voltage signal terminal J3-2 and the level signal feedback terminal CON8-1.

[0024] Preferably, in the present embodiment, the level signal injection terminal CON7-1 is electrically connected to the battery management system BMS, and the battery management system BMS provides a level signal; preferably, in the present embodiment, the level signal feedback terminal CON8-1 is electrically connected to the battery management system BMS, and the level signal is fed back to the battery management system BMS; specifically preferably, in the present embodiment, the battery management system BMS is a battery management system BMS for an electric vehicle.

[0025] Preferably, in the present embodiment, the first low-pass filter circuit includes a first chip resistor R94 and a first capacitor C49, wherein the first chip resistor R94 is connected between the first high-voltage signal terminal J3-1 and the ground GND_LV; the first capacitor C49 is connected between the first high-voltage signal terminal J3-1 and the ground GND_LV; further preferably, in the present embodiment, the resistance range of the first chip resistor R94 is 250-350 kilo-ohms, and the capacitance of the first capacitor C49 is 0.5-1.5nF; the first chip resistor R94 adopts a 0603 packaging structure, and the first capacitor C49 adopts a multilayer ceramic capacitor.

[0026] Preferably, in this embodiment, the second low-pass filter circuit includes a second chip resistor R97 and a second capacitor C67, wherein the second chip resistor R97 is connected between the second high-voltage signal terminal J3-2 and the ground GND_LV; the second capacitor C67 is connected between the second high-voltage signal terminal J3-2 and the ground GND_LV; wherein, in this embodiment, the positive electrode of the first capacitor C49 is connected to the positive electrode of the second capacitor C67.

[0027] Further preferably, in the present embodiment, the resistance range of the second chip resistor R97 is 250-350 kilo-ohms, and the capacitance of the second capacitor C67 is 0.5-1.5nF; at the same time, the resistance of the second chip resistor R97 is equal to the resistance of the first chip resistor R94, and the capacitance of the second capacitor C67 is equal to the capacitance of the first capacitor C49; the second chip resistor R97 adopts a 0603 packaging structure, and the second capacitor C67 adopts a multilayer ceramic capacitor.

[0028] Specifically preferably, in this embodiment, the resistance of the first chip resistor R94 and the resistance of the first chip resistor R94 are both 300 kilo-ohms (kΩ), and the power is both 0.125W; the capacitance of the first capacitor C49 and the capacitance of the second capacitor C67 are both 1nF, and the withstand voltage is both 50V.

[0029] In actual operation of this embodiment, the battery management system BMS sends a level signal to the level signal injection terminal CON7-1, passes through the first high-voltage signal terminal, and is filtered by the first low-pass filter circuit and the second low-pass filter circuit, and then returns to the second high-voltage signal terminal and the level signal feedback terminal; when the battery management system BMS detects that the level signal feedback terminal returns a level signal, it confirms that the high-voltage interlock signal is intact, and there is no disconnection or poor contact between the first high-voltage signal terminal J3-1 and the second high-voltage signal terminal J3-2. Only then will the vehicle load be energized (otherwise the vehicle load will not be energized), thereby ensuring the safety of the vehicle and personnel. The structure is simple, the high-voltage interlock detection effect is reliable, the cost is low, and it is suitable for large-scale promotion and application.

[0030] It is obvious to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the present invention can be implemented in other specific forms without departing from the spirit or essential features of the present invention. Therefore, the embodiments should be regarded as exemplary and non-restrictive from any point of view, and the scope of the present invention is defined by the appended claims rather than the above description, and it is intended that all changes falling within the meaning and scope of the equivalent elements of the claims be included in the present invention. Any reference numeral in a claim should not be regarded as limiting the claim to which it relates.

[0031] In addition, it should be understood that although the present specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.

Claims

1. A high voltage interlock detection circuit, characterized in that: It includes a first low-pass filter circuit connected to the first high-voltage signal terminal (J3-1) and a second low-pass filter circuit connected to the second high-voltage signal terminal (J3-2); wherein, A level signal injection terminal (CON7-1) is further provided at the connection between the first high-voltage signal terminal (J3-1) and the first low-pass filter circuit, and a level signal feedback terminal (CON8-1) is further provided at the connection between the second high-voltage signal terminal (J3-2) and the second low-pass filter circuit; The first high-voltage signal terminal (J3-1) and the second high-voltage signal terminal (J3-2) are respectively high-voltage interlocking connection plugs.

2. The high voltage interlock detection circuit according to claim 1, characterized in that: The level signal injection terminal (CON7-1) is electrically connected to a battery management system BMS, and the battery management system BMS provides a level signal.

3. The high voltage interlock detection circuit according to claim 1, characterized in that: The level signal feedback terminal (CON8-1) is electrically connected to a battery management system BMS, and feeds back a level signal to the battery management system BMS.

4. The high voltage interlock detection circuit according to claim 1, characterized in that: The first low-pass filter circuit includes a first chip resistor (R94) and a first capacitor (C49), wherein the first chip resistor (R94) is connected between the first high-voltage signal terminal (J3-1) and the ground (GND_LV); and the first capacitor (C49) is connected between the first high-voltage signal terminal (J3-1) and the ground (GND_LV).

5. The high voltage interlock detection circuit according to claim 4, characterized in that: The resistance range of the first chip resistor (R94) is 250-350 kilo-ohms, and the capacitance of the first capacitor (C49) is 0.5-1.5 nF.

6. The high voltage interlock detection circuit according to claim 4, characterized in that: The first chip resistor (R94) adopts a 0603 packaging structure, and the first capacitor (C49) adopts a multilayer ceramic capacitor.

7. The high voltage interlock detection circuit according to claim 4, characterized in that: The second low-pass filter circuit includes a second chip resistor (R97) and a second capacitor (C67), wherein the second chip resistor (R97) is connected between the second high-voltage signal terminal (J3-2) and the ground (GND_LV); and the second capacitor (C67) is connected between the second high-voltage signal terminal (J3-2) and the ground (GND_LV).

8. The high voltage interlock detection circuit according to claim 7, characterized in that: The resistance range of the second chip resistor (R97) is 250-350 kilo-ohms, and the capacitance of the second capacitor (C67) is 0.5-1.5 nF; at the same time, the resistance of the second chip resistor (R97) is equal to the resistance of the first chip resistor (R94), and the capacitance of the second capacitor (C67) is equal to the capacitance of the first capacitor (C49).

9. The high voltage interlock detection circuit according to claim 7, characterized in that: The second chip resistor (R97) adopts a 0603 package structure, and the second capacitor (C67) adopts a multilayer ceramic capacitor.

10. The high voltage interlock detection circuit according to claim 2, characterized in that: The battery management system BMS is a battery management system BMS for an electric vehicle.

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