Packaging structure

Abstract

Some embodiments of the present application provide a package structure comprising: a wire structure comprising a first hole and a bridge line disposed around the first hole; a first electronic component over the lead structure; and a second electronic component located above the lead structure and disposed adjacent to the first electronic component, in which, in a plan view, the bridge circuit and the first hole are located between the first electronic component and the second electronic component. According to the packaging structure provided by the invention, the first hole is formed in the wire structure, so that the warping of the packaging structure is reduced.

Description

Technical Field

[0001] An embodiment of the present application relates to a packaging structure. Background Art

[0002] At present, the back chip packaging of multi-chips of fan-out panel-level fan-out packages (PNL) is shipped as a whole panel-level fan-out package (PNL), but the existing panel-level fan-out packages (PNL) generally have problems such as warping. For details, see Figures 1A to 1E , Figure 1A A cross-sectional view of a portion of a panel-level fan-out package (PNL) is shown. Figure 1B A cross-sectional view of a panel-level fan-out package (PNL) 10 with electronic components 14 connected thereto is shown, and Figure 1C to Figure 1D The warpage behavior W of a panel-level fan-out package (PNL) 10 and the resulting corresponding impact C (eg, extrusion) are shown. Figures 1A to 1D It can be seen that the panel-level fan-out package (PNL) 10 mainly encapsulates the multi-layer redistribution structure (RDL) 11 of 8P7M (i.e., there are 8 dielectric layers and corresponding 7 metal layer lines) and the array-arranged chips 13 together with the molding compound (CPD) 12. Since the multi-layer redistribution structure 11 is an 8P7M high-layer structure and extends continuously, the multi-layer redistribution structure 11 will have a larger shrinkage degree due to the superposition when it is cured and shrunk. In addition, after the panel-level fan-out package (PNL) 10 is debonded, the warping behavior of the entire panel-level fan-out package (PNL) 10 will bend in the direction of RDL (8P7M) (see Figure 1C After that, when the molding compound (CPD) 12 is further thinned (i.e., ground), the warpage W of the panel-level fan-out package (PNL) 10 will reach 10000μm (the standard is 2000μm), which is far beyond the standard, making it difficult to subsequently solder electronic components 14 such as VRM (voltage regulator module) or connectors.

[0003] Next, see Figure 1E , Figure 1E Shows Figure 1B The warpage of the panel-level fan-out package (PNL) 10 at various stages is shown, wherein, in the abscissa, Debond represents the stage of debonding the carrier commonly used in the art from the panel-level fan-out package (PNL) 10, G / D represents the stage of grinding the surface of the molding compound (CPD) 12, and BSF represents the stage of using the back side film (BSF); the ordinate represents Figure 1B The warpage of the panel-level fan-out package (PNL) 10 is shown in FIG. Figure 1EIn the figure shown, PNL ASSY also represents the warpage of the panel-level fan-out package (PNL) 10, and the specific value of the corresponding warpage is shown here. Figures 1A to 1E ,exist Figure 1B In the panel-level fan-out package (PNL) 10 shown, a chip 13 is arranged on a redistribution structure 11 of 8P7M (i.e., there are 8 dielectric layers and corresponding 7 metal layer lines), and the chip 13 is such as a serial deserializer (SerDes), a computer component, etc., and then the corresponding chip 13 is encapsulated by a molding compound 12. During these processes, see Figure 1C and Figure 1E After debonding (DeBond), the warpage is pulled toward the crying face direction by the 8P7M redistribution structure 11, and the warpage is 3250μm at this time. After grinding the surface of the molding compound (G / D), the warpage can reach 10000μm, which exceeds the warpage specification of 2000μm in the field. Even using the back side film (BSF) cannot bring the warpage back to the specification, because the warpage can reach 6000μm at this time, which is much larger than the specification of 2000μm. Therefore, the above-mentioned panel-level fan-out package (PNL) 10 has the following problems:

[0004] 1. The redistribution structure 11 in the panel-level fan-out package (PNL) 10 requires 8P7M, and for telecommunications and interference prevention considerations, the circuit will be made thicker, resulting in a thick and multi-layer redistribution structure 11;

[0005] 2. The redistribution structure 11 is a high shrinkage material. The thicker it is, the more serious the warping will be.

[0006] 3. The shrinkage of the molding compound (CPD) 12 and the associated coefficient of thermal expansion (CTE) make it difficult to pull the warpage of the panel-level fan-out package (PNL) 10 back to within the specification of less than 2000 μm; and

[0007] 4. The existing redistribution structure 11 cannot be thinned.

[0008] In summary, in the special performance package product composed of the panel-level fan-out package (PNL) 10 (i.e., 1PCPNL (1 PNL) is required as a package product), the PNL warpage specification is ±2000μm, while the current package warpage is greater than 2000μm. Therefore, the current package yield is 0%. Utility Model Content

[0009] In order to solve the problem that in the back-chip packaging structure of multiple chips in a fan-out panel-level fan-out package (PNL), since the redistribution structure (RDL) is an 8P7M high-layer structure and extends continuously, resulting in a larger shrinkage degree during RDL curing and shrinkage due to overlapping, the problem can be solved by reducing the continuous structure of RDL.

[0010] Some embodiments of the present application provide a packaging structure, comprising: a wire structure, comprising a first hole and a bridging circuit arranged around the first hole; a first electronic component located above the wire structure; and a second electronic component located above the wire structure and arranged adjacent to the first electronic component, wherein, when viewed from above, the bridging circuit and the first hole are located between the first electronic component and the second electronic component.

[0011] In some embodiments, in a top view, the first hole is closer to a first corner of the first electronic component than to the bridge line.

[0012] In some embodiments, in a plan view, the first electronic component has a first edge and a second edge adjacent to the first edge, and the first hole extends along the first edge to the second edge.

[0013] In some embodiments, the packaging structure further includes:

[0014] The second hole is adjacent to a second corner of the first electronic component, wherein the second corner and the first corner are located on the same side of the first electronic component.

[0015] In some embodiments, the bridge line is located between the first hole and the second hole.

[0016] In some embodiments, the packaging structure further includes:

[0017] A molding compound is located over the conductive structure and extends into the first hole.

[0018] In some embodiments, a bottom surface of the molding compound is flush with a bottom surface of the first hole, wherein the bottom surface of the molding compound and the bottom surface of the first hole are surfaces away from the first electronic component.

[0019] In some embodiments, a portion of the molding compound extends beyond a bottom surface of the conductive structure away from the first electronic component.

[0020] In some embodiments, the portion of the molding compound that extends beyond the bottom surface of the conductive line structure includes a curved surface.

[0021] In some embodiments, the curved surface is convex.

[0022] In some embodiments, when viewed from above, the first hole has a shape including a cross, a saddle, a circle and / or an X.

[0023] In some embodiments, the plurality of first holes are disposed at sides of the first electronic component and the second electronic component when viewed from above.

[0024] In some embodiments, in a plan view, a plurality of the first holes are evenly distributed between the first electronic component and the second electronic component.

[0025] In some embodiments, when viewed from above, the plurality of first holes are arranged in an array.

[0026] In some embodiments, a sidewall of the first hole is formed by a dielectric layer in the conductive line structure, wherein the bridge line is embedded in the dielectric layer.

[0027] In some embodiments, the molding compound further seals the first electronic component and the second electronic component, and a top surface of the molding compound is flush with top surfaces of the first electronic component and the second electronic component, wherein the top surface of the molding compound and the top surfaces of the first electronic component and the second electronic component are surfaces away from the wire structure.

[0028] In some embodiments, a first line of the bridge line close to the first hole is thinner than a second line of the bridge line far from the first hole.

[0029] Other embodiments of the present application provide a packaging structure, comprising: a conductive line structure including a plurality of first holes and a bridging line; a plurality of electronic components arranged above the conductive line structure; and a molding compound that seals the plurality of electronic components and extends into the plurality of first holes, wherein the first holes are located between adjacent electronic components of the plurality of electronic components, and when viewed from above, the bridging line surrounds the plurality of first holes and extends between the adjacent electronic components.

[0030] In some embodiments, in a top view, the first hole is closer to a corner of the electronic component than to the bridge line.

[0031] In some embodiments, the plurality of first holes are evenly dispersed between the adjacent electronic components when viewed from above.

[0032] With the packaging structure provided by the present application, the warping of the packaging structure is reduced by providing a first hole in the conductive line structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] When read in conjunction with the accompanying drawings, various aspects of the present invention can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for the sake of clarity of discussion, the size of the various components can be arbitrarily increased or reduced.

[0034] Figures 1A to 1E A prior art panel-level fan-out package (PNL) and its corresponding warpage are shown.

[0035] Figure 2A and Figure 2B A warpage comparison between an existing panel-level fan-out package (PNL) and a package structure provided according to some embodiments of the present application is shown.

[0036] Figure 3A , Figure 3A-1 to Figure 3A-2 as well as Figure 3B-Figure 3E A packaging structure according to some embodiments of the present application is shown.

[0037] Figures 4 to 6 The process flow of the packaging structure according to some embodiments of the present application is shown. DETAILED DESCRIPTION

[0038] The following disclosure provides many different embodiments or examples for realizing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. In addition, when "approximately", "about", "substantially", etc. are used to describe a numerical value or a numerical range, unless otherwise specified, the term is intended to cover a numerical value within ±10% of the described numerical value. For example, the term "about 5nm" covers a size range from 4.5nm to 5.5nm.

[0039] Some embodiments of the present application provide a packaging structure, which reduces the warpage of the corresponding packaging structure by reducing the continuous structure of the original 8P7M wire structure. Specifically, the present application reduces the problem of interconnection between wire structures by disconnecting local parts of the wire structure, thereby reducing the warpage of the corresponding packaging structure.

[0040] Specifically, see the FIG. 2A to FIG. 2B , Figure 2A FIG. 1 shows the warpage of a corresponding panel-level fan-out package of an 8P7M redistribution structure (RDL) 11 used in the prior art (wherein 1000 represents a carrier such as glass, etc.), and Figure 2B FIG. 1 shows the warpage of a 8P7M conductive line structure 101 including a plurality of holes O (formed by laser S). Figure 2A The 8P7M redistribution structure 11 used in the prior art shown in FIG. Figure 2A The warping produced in the structure shown is as high as -2 mm (wherein the “-” sign indicates that the warping will bend in the direction of the carrier 1000 , and 2 mm is the distance from the top to the bottom of the redistribution structure 11 ).

[0041] for Figure 2B The 8P7M conductor structure 101 shown includes a plurality of holes O. The 8P7M conductor structure 101 is Figure 2B The warpage generated in the structure shown is reduced (decreased) to <-1mm (where the "-" sign indicates that the warpage will bend in the direction of the carrier 1000, and 1mm is the distance from the top to the bottom of the conductor structure 101). It should be noted that the warpage only involves the magnitude of the value, not the sign. Therefore, reducing (decreased) to <-1mm means that the corresponding value (without the sign) is below 1mm. In summary, since the redistribution structure 11 has a high shrinkage characteristic, it leads to Figure 2A In the present application, for the 8P7M wire structure 101, the warpage of the corresponding wire structure 101 is reduced to <-1 mm (without reference to the sign) by the plurality of holes O provided in the present application. Therefore, the package structure 100 / 200 (see below) formed by the corresponding wire structure 101 can be ensured. Figure 3A and Figure 3A-1 )’s warpage is within ±2000μm, i.e., ensured to be within specifications.

[0042] It can be seen that the original 8P7M redistribution structure 11 is transformed into a corresponding wire structure 101 with multiple holes O, and the local part of the corresponding wire structure 101 is disconnected, the linkage problem between the wire structures 101 is reduced, and the warping degree of the corresponding structure is reduced. Even if a crying face structure is still formed when warping occurs, the warping is significantly reduced compared with the original.

[0043] The embodiment of the present application provides a packaging structure 100, see FIG. 3A to FIG. 3E , Figure 3A 1 shows a cross-sectional view of a package structure 100 according to some embodiments of the present application. Figure 3B Shows Figure 3A A partial top view of the package structure 100 is shown, and Figure 3C Shows Figure 3B Detailed view of region A in a partial top view of FIG. Specifically, see Figure 3A The package structure 100 includes: a conductive line structure 101, including a first hole 101O1 and a bridge line 101m arranged around the first hole 101O1. Figure 3CWhen the conductor structure 101 in the present application is established or manufactured, some areas without bridge lines 101m are left (intentionally left blank), thereby leaving a pure dielectric area (such as a polyimide (PI) area) formed by the dielectric layer 101t of the conductor structure 101, so that when the first hole 101O1 is formed in the conductor structure 101 later, the corresponding bridge line 101m is bypassed, and the bridge line 101m is arranged around the first hole 101O1. In addition, in the present application, a portion of the pure dielectric area of ​​the dielectric layer 101t is burned away by laser to expose the portion where the first hole 101O1 is to be formed, thereby disconnecting the effect of the warping effect of the interconnection between the conductor structures 101. It should be noted that in the present application, the conductor structure 101 is not completely cut into a block, but a blank area of ​​a pure dielectric area of ​​the dielectric layer 101t is intentionally left blank by winding, and the pure dielectric area is burned away by laser to achieve the purpose of disconnecting the interconnection between the conductor structures 101. In the above embodiment, the conductive line structure 101 may be a redistribution structure. In the above embodiment, the dielectric layer 101t may be a polymer layer such as polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB), etc., and the bridge line 101m may be made of a metal such as copper, tin, etc.

[0044] Continue to see Figure 3A , the package structure 100 also includes a plurality of electronic components 103 located above the conductor structure 101, such as a first electronic component 103-1 to a fourth electronic component 103-4. In the following description, the first electronic component 103-1 and the second electronic component 103-2 disposed adjacent to the first electronic component 103-1 are used for description, but it should be understood by those skilled in the art that the arrangement between the second electronic component 103-2 and the third electronic component 103-3 and between the third electronic component 103-3 and the fourth electronic component 103-4 is the same or similar to that between the first electronic component 103-1 and the second electronic component 103-2, and only the first electronic component 103-1 and the second electronic component 103-2 are used as examples here and are not repeatedly described. In some embodiments, the first electronic component 103-1 to the fourth electronic component 103-4 may be a wafer. In some embodiments, the first electronic component 103-1 to the fourth electronic component 103-4 may include a computer, a serial deserializer (SerDes), etc. In some specific embodiments, the first electronic component 103 - 1 and the fourth electronic component 103 - 4 are serializers and deserializers, and the second electronic component 103 - 2 and the third electronic component 103 - 3 are computers.

[0045] Next, see FIG. 3B to FIG. 3C , Figure 3B and Figure 3C Shows Figure 3A A top view of the package structure 100, wherein Figure 3B and Figure 3C In the top view, some structures are not visible, and Figure 3C Shows Figure 3B Detailed view of area A in a partial top view. Figure 3C It can be seen from the figure that, in a top view, the bridge circuit 101m and the first hole 101O1 are located between the first electronic component 103-1 and the second electronic component 103-2. Figure 3C It can be seen from the figure that, in a top view, the first hole 101O1 is closer to the first corner 103-1c1 of the first electronic component 103-1 than the bridge line 101m. Similarly, it is also closer to the adjacent corner 103-2c of the second electronic component 103-2. Figure 3B and Figure 3C It can still be seen that, in a top view, the first electronic component 103-1 has a first edge 103-1s1 and a second edge 103-1s2 adjacent to the first edge 103-1s1, and the first hole 101O1 extends along the first edge 103-1s1 of the first electronic component 103-1 to the second edge 103-1s2 of the first electronic component 103-1, that is, the first hole 101O1 may be in an L shape. In the embodiment of the present application, the second electronic component 103-2 also has a first edge 103-2s1 and a second edge 103-2s2 adjacent to the first edge 103-2s1, and the first hole 101O1 further extends along the first edge 103-2s1 of the second electronic component 103-2 to the second edge 103-2s2 of the first electronic component 103-2, therefore, the first hole 101O1 may be as shown in FIG. FIG. 3B to FIG. 3C In addition, the first hole 10101 may be in any suitable shape, such as but not limited to a saddle shape, a circle and / or an "X" shape.

[0046] In a further embodiment, the package structure 100 further includes a second hole 101O2 adjacent to the second corner 103-1c2 of the first electronic component 103-1. Figure 3B and Figure 3C It can be seen from FIG. 1 that the second corner 103-1c2 and the first corner 103-1c1 are located on the same side of the first electronic component 103-1. Figure 3C As can be seen in FIG. 1 , the bridge line 101m is located between the first hole 101O1 and the second hole 101O2, that is, the bridge line 101m bypasses the corresponding first hole 101O1 and the second hole 101O2, etc., and is connected to the pad 103P of the corresponding electronic component 103. Figure 3CAs shown, the first line 101m1 of the bridge circuit 101m near the first hole 101O1 is thinner than the second line 101m2 of the bridge circuit 101m far from the first hole 101O1. It can be seen that the bridge circuit 101m will be wound near the first hole 101O1, and in order to avoid the bridge circuit 101m being too dense near the first hole 101O1, the bridge circuit 101m is designed so that the first line 101m1 near the first hole 101O1 is thinner than the second line 101m2 of the bridge circuit 101m far from the first hole 101O1. In addition, in some embodiments, the second hole 101O2 is similar to the first hole 101O1 and will not be described in detail here.

[0047] See also Figure 3A , the package structure 100 further includes: a molding compound 102, which is located above the conductive wire structure 101 and extends into the first hole 101O1. In the present application, the molding compound 102 can extend into any hole of the conductive wire structure 101, such as the first hole 101O1, the second hole 101O2... In some embodiments, the molding compound 102 can be a molding compound, a bottom filler, etc. Further, by using the molding compound 102, the molding compound 102 with a relatively low coefficient of thermal expansion (CTE) is flowed into these first holes 101O1, so that the molding compound 102 replaces the conductive wire structure 101 at the first hole 101O1, thereby reducing the equivalent thermal expansion coefficient of the conductive wire structure 101, which can further reduce the warpage of the package structure 100. The coefficient of thermal expansion (CTE) of the conductive line structure 101 formed of the molding compound 102 such as molding compound, the bridge line 101 m formed of metal copper, and the dielectric layer 101 t formed of a dielectric material such as polyimide (PI) is shown in Table 1 below.

[0048] Table 1 Corresponding thermal expansion coefficients of the molding compound 102 such as molding compound and the conductor structure 101

[0049]

[0050]

[0051] It can be seen from Table 1 above that the coefficient of thermal expansion (CTE) of the molding compound 102 such as molding material is 8-13 ppm, which is significantly smaller than the coefficient of thermal expansion (CTE) of the wire structure 101 composed of the bridge line 101m (60 ppm) formed by metal copper and the dielectric layer 101t (17 ppm) formed by the dielectric material of polyimide (PI). Therefore, the molding compound area 102 can be used to reduce the equivalent thermal expansion coefficient of the wire structure 101, thereby achieving the effect of further reducing the warpage of the package structure 100.

[0052] In further embodiments, see Figure 3A , the bottom surface 102d of the molding compound 102 is flush with the bottom surface 101O1d of the first hole 101O1, Figure 3A As can be seen in FIG. 1 , the bottom surface 102d of the mold compound 102 and the bottom surface 101O1d of the first hole 101O1 are away from the surface of the first electronic component 103-1. Figure 3A-1 In the partial packaging structure 200 shown, a portion of the molding compound 102 extends beyond the bottom surface 101d of the conductive line structure 101 away from the first electronic component 103-1. This may be caused by over-etching when etching the conductive line structure 101 to form the first hole 101O1, but this situation is relatively rare. Further, the portion of the molding compound 102 extending beyond the bottom surface 101d of the conductive line structure 101 includes a curved surface 102q, and in some embodiments, the curved surface 102zq is a convex surface, that is, a convex surface facing away from the conductive line structure 101. In addition, the molding compound 102 further seals the first electronic component 103-1 and the second electronic component 103-2, and the top surface 102t of the molding compound 102 is flush with the top surfaces 103t of the first electronic component 103-1 and the second electronic component 103-2, from Figure 3A As can be seen from the figure, the top surface 102t of the molding compound 102 and the top surfaces 103t of the first electronic component 103-1 and the second electronic component 103-2 are surfaces away from the conductive line structure 101. In a further embodiment, the sidewall of the first hole 101O1 is formed by the dielectric layer 101t in the conductive line structure 101, because the first hole 101O1 is formed by a pure dielectric region of the dielectric layer 101t. Figure 3A As can be seen in FIG. 1 , the bridge line 101m is embedded in the dielectric layer 101t.

[0053] Next, see Figure 3D and Figure 3E , Figure 3D and Figure 3E Shows Figure 3A A simplified top view of the package structure 100 is shown. For simplicity, only some of the numbers are shown and some structures are not visible. In addition, Figure 3A Shown along Figure 3D or Figure 3E The cross-sectional view of the line L1 in FIG. Figure 3A-2 Shown along Figure 3D or Figure 3E The cross-sectional view of the line L2 in Figure 3A-2 In the package structure 100 shown, the first hole 101O1 is not formed in the conductive line structure 101. Figure 3D , when viewed from above, the first hole 101O1, as shown above Figure 3B and Figure 3CAs shown, the first corner 103-1c1 of the first electronic component 103-1 and the adjacent corner 103-2c of the second electronic component 103-2 are arranged. Figure 3E In the embodiment, when viewed from above, the plurality of first holes 101O1 are disposed at the sides of the first electronic component 103-1 and the second electronic component 103-2, rather than at the corners. Figure 3E In the illustrated embodiment, since more smaller first holes 101O1 are formed, the stress on the wire structure 101 can be made more uniform, and the warping of the wire structure 101 can be reduced, thereby reducing the warping of the formed package structure 100.

[0054] from Figure 3D and Figure 3E It can be seen from the figure that, in a top view, the plurality of first holes 101O1 are evenly dispersed between the first electronic component 103-1 and the second electronic component 103-2, and are further evenly dispersed between other adjacent electronic components 103, and the plurality of first holes 101O1 are arranged in an array as shown in the figure. FIG. 3D to FIG. 3E In FIG. 1 , the structural characteristics of the first hole 101O1 at the conductive line structure 101 can be found, and other materials (such as the molding compound 102) are filled in the first hole 101O1. FIG. 3D to FIG. 3E It can also be seen from the top view that there are laser-burned openings (such as first holes 101O1) at the conductive line structure 101, with any shape, and the positions of the first holes 101O1 are evenly distributed on the conductive line structure 101. Figure 3A In the package structure 100 shown, after P-lapping from the top to the conductive line structure 101 , it can be more clearly seen that the first hole 101O1 is filled with other materials, such as the molding compound 102 .

[0055] Return to see Figure 3A The package structure 100 further includes a plurality of external components 104 disposed at the side of the conductor structure 101 opposite to the electronic component 103, such as first external components 104-1 to fourth external components 104-4, wherein the first external components 104-1 to the fourth external components 104-4 may be external connectors, and the second external components 104-2 to the third external components 104-3 may be voltage regulator modules (VRMs). Figure 3AAs shown, the external component 104 is connected to the conductive line structure 101 through the bumps 106, and the bottom filler 105 is disposed between the bumps 106 and between the external component 104 and the conductive line structure 101. Similarly, the electronic component 103 is connected to the conductive line structure 101 through the conductive pillars 107 or bumps 108 such as copper, and the bottom filler 109 is disposed between the conductive pillars 107 or bumps 108 and between the electronic component 103 and the conductive line structure 101. In some embodiments, the bumps 106 and the bumps 107 may include solder bumps.

[0056] See also Figure 3A Other embodiments of the present application further provide a packaging structure 100, which includes a conductive line structure 101, including a plurality of first holes 101O1 and a bridge line 101m; a plurality of electronic components 103 disposed above the conductive line structure 101; and a molding compound 102 that seals the plurality of electronic components 103 and extends into the plurality of first holes 101O1. In some embodiments, the first holes 101O1 are located between adjacent electronic components (such as the first electronic component 103-1 and the second electronic component 103-2) of the plurality of electronic components 103, and when viewed from above, the bridge line 101m surrounds the plurality of first holes 101O1 and extends between adjacent electronic components (such as the first electronic component 103-1 and the second electronic component 103-2). See further. Figure 3B and Figure 3C In a top view, the first hole 101O1 is closer to a corner of the electronic component 103 (such as a first corner 103-1c1 of the first electronic component 103-1) relative to the bridge line 101m, and in a top view, a plurality of first holes 101O1 are evenly dispersed between adjacent electronic components (such as the first electronic component 103-1 and the second electronic component 103-2).

[0057] See below Figures 4 to 6 To introduce Figure 3A The process of forming the package structure 100 is shown.

[0058] See also Figure 4 , a conductor structure 101 is formed on a substrate 1001 such as glass. As described above, the conductor structure 101 is a redistribution structure (RDL) of 8P7M, that is, it is composed of 8 dielectric layers 101t and 7 layers of bridge lines 101m. Specifically, a first dielectric layer 101t is formed on the carrier 1001. In some embodiments, the dielectric layer 101t is formed of a polymer such as polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB), etc. In the present embodiment, the dielectric layer 101t is formed of polyimide (PI), and the dielectric layer 101dd can be formed by any acceptable deposition process such as spin coating, chemical vapor deposition (CVD), lamination, etc., or a combination thereof.

[0059] A bridge line 101m is formed on the dielectric layer 101t. As an example of forming the bridge line 101m, a seed layer (not shown) is formed above the dielectric layer 101t. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer including a plurality of sublayers formed of different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer located above the titanium layer. The seed layer may be formed using, for example, PVD. Thereafter, a photoresist is formed on the seed layer and the photoresist is patterned. The photoresist may be formed by spin coating, etc., and may be exposed to light for patterning. The pattern of the photoresist corresponds to the bridge line 101m. Patterning forms an opening through the photoresist to expose the seed layer. A conductive material is formed in the opening of the photoresist and on the exposed portion of the seed layer. The conductive material may be formed by plating such as electroplating or chemical plating. The conductive material may include metals such as copper, titanium, tungsten, aluminum, etc. Thereafter, the photoresist and the portion of the seed layer on which the conductive material is not formed are removed. The photoresist may be removed by an acceptable ashing or stripping process (such as using oxygen plasma, etc.). Once the photoresist is removed, the exposed portion of the seed layer is removed, such as by using an acceptable etching process (such as wet or dry etching). The remaining portion of the seed layer and the conductive material form a bridge line 101m. The process of forming the dielectric layer 101t and the bridge line 101m is repeated until the conductor structure 101 of the redistribution structure of 8P7M is formed. In the above-mentioned conductor structure 101, there is a pure dielectric area of ​​the dielectric layer 101t, that is, an area without a bridge line 101m, for forming a plurality of first holes 101O1 and / or second holes 101O2.

[0060] Afterwards, see Figure 5 , laser is used to burn off the pure dielectric area of ​​the dielectric layer 101t, thereby forming a plurality of first holes 101O1 and / or second holes 101O2 in the wire structure 101, thereby disconnecting the effect of the warping between the wire structures 101. It can be seen that in the present application, the wire structure 101 is not completely cut into a block, but a pure dielectric area of ​​the dielectric layer 101t is deliberately wound to leave an empty area, and the pure dielectric area is burned off by laser to achieve the purpose of disconnecting the connection between the wire structures 101, thereby disconnecting the warping between the wire structures 101. Figure 5 The warpage of the structure shown is reduced to <-1 mm, which can ensure that the warpage of the package structure 100 formed later is within the specification of ±2000 μm.

[0061] Next, see Figure 6, attach the electronic component 103 to the side of the conductor structure 101 opposite to the carrier 1001, specifically, the electronic component 103 is connected to the conductor structure 101 through a conductive pillar 107 or a bump 108 such as copper, and an underfill 109 is provided between the conductive pillars 107 or the bumps 108 and between the electronic component 103 and the conductor structure 101. Afterwards, a molding compound 102 is formed over the electronic component 103 and the conductor structure 101, which is a molding compound in this embodiment. In some embodiments, the molding compound 102 can be formed by transfer molding, compression molding, and the like. Figure 6 As shown, the molding compound 102 is formed to seal the electronic component 103 therein and further extend into the plurality of first holes 101O1 and / or the second holes 101O2. In the present application, the molding compound 102 having a relatively low coefficient of thermal expansion (CTE) is flowed into the first holes 101O1, so that the molding compound 102 replaces the wire structure 101 at the first hole 101O1, thereby reducing the equivalent coefficient of thermal expansion of the wire structure 101, and further reducing the warpage of the package structure 100.

[0062] Finally, the carrier 1001 is removed by peeling or the like and an external component is attached to the side of the conductor structure 101 opposite to the electronic component 103, so that the Figure 3A The package structure 100 is shown.

[0063] The packaging structure 100 provided in the present application can be shipped as a panel-level fan-out package (PNL), and the warpage of the panel-level fan-out package (PNL) is processed to be within the standard specification of ±2000μm. In addition, compared with other packaging structures, the formation process of the packaging structure 100 of the present application is a post-chip (wafer) process (that is, the electronic component 103 is formed later), while other existing packaging structures are chip-first. Therefore, the packaging structure 100 provided in the present application is superior to the existing packaging structure in terms of cost and yield. In addition, the existing packaging structure is generally manufactured in a wafer-level manner, while the present application is manufactured in a panel-level fan-out package (PNL) manner, which has space advantages and functional advantages in increasing the number of chips (electronic components 103) and components.

[0064] In addition, for normal fan-out chip on substrate (FOCoS), chiplet integrated silicon bridge technology (FOCoS-B), fan-out panel level (FOP) devices or fan-out panel level packaging (FOPLP) devices, such as tablet computers, laptops, and 5G computer network server display cards, as long as the fan-out warpage of the conductive structure (such as the redistribution structure) exceeds the standard, the technology provided in this application can be adopted.

[0065] The features of several embodiments are summarized above so that those skilled in the art can better understand aspects of the present invention. Those skilled in the art should understand that they can easily use the present invention as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the present invention, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present invention.

Claims

1. A packaging structure, characterized in that: include: A conductor structure, comprising a first hole and a bridge circuit arranged around the first hole; A first electronic component is located above the conductive wire structure; as well as a second electronic component, located above the conductive wire structure and disposed adjacent to the first electronic component, Wherein, in a plan view, the bridge circuit and the first hole are located between the first electronic component and the second electronic component.

2. The packaging structure according to claim 1, characterized in that: In a plan view, the first hole is closer to a first corner of the first electronic component than to the bridge line.

3. The packaging structure according to claim 1, characterized in that: In a plan view, the first electronic component has a first edge and a second edge adjacent to the first edge, and the first hole extends along the first edge to the second edge.

4. The packaging structure according to claim 2, characterized in that: Also includes: The second hole is adjacent to a second corner of the first electronic component, wherein the second corner and the first corner are located on the same side of the first electronic component.

5. The packaging structure according to claim 4, characterized in that: The bridge line is located between the first hole and the second hole.

6. The packaging structure according to claim 1, characterized in that: Also includes: A molding compound is located over the conductive structure and extends into the first hole.

7. The packaging structure according to claim 6, characterized in that: The bottom surface of the molding compound is flush with the bottom surface of the first hole, wherein the bottom surface of the molding compound and the bottom surface of the first hole are surfaces away from the first electronic component.

8. The packaging structure according to claim 6, characterized in that: A portion of the molding compound extends beyond a bottom surface of the conductive structure away from the first electronic component.

9. The packaging structure according to claim 8, characterized in that: The portion of the molding compound extending beyond the bottom surface of the conductive structure includes a curved surface.

10. The packaging structure according to claim 6, characterized in that: The molding compound further seals the first electronic component and the second electronic component, and a top surface of the molding compound is flush with top surfaces of the first electronic component and the second electronic component, wherein the top surface of the molding compound and the top surfaces of the first electronic component and the second electronic component are surfaces away from the wire structure.

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