Power supply output circuit based on short circuit protection and double channels

Abstract

The utility model relates to the field of power supplies, and particularly discloses a power supply output circuit based on short-circuit protection and double channels, which comprises a short-circuit protection unit, a double-channel output unit, an input port IN, a first output port OUT1 and a second output port OUT2. The input port IN is used for being connected with a power supply, the input end of the short circuit protection unit is connected with the input port IN, the output end of the short circuit protection unit is connected with the input end of the double-channel output unit, and the double-channel output unit is connected with the first output port OUT1 and the second output port OUT2. And the first output port OUT1 and the second output port OUT2 supply power to the outside. According to the utility model, short-circuit protection can be effectively realized, and balance of output current can be ensured during dual-channel output.

Description

Technical Field

[0001] The utility model relates to the field of power supply, in particular to a power supply output circuit based on short circuit protection and dual channels. Background Art

[0002] Power supplies are indispensable devices in social work and life, and the protection of electrical devices has become an issue that must be considered. Generally speaking, the most likely cause of damage to electrical devices is a short circuit in the device or a large voltage fluctuation caused by external influences on the power supply. Under normal circumstances, a current limiting resistor can be connected in series, but even when the electrical device is working normally, the current limiting resistor is still in the circuit, which will cause power loss and cause waste of electric energy. In addition, in some scenarios, the power supply needs to have dual-channel output and require balanced drive loads, but due to differences in power supply paths or manufacturing processes of the same type of electrical devices themselves, the currents between different channels may be different, so current balance cannot be achieved in the dual channels. Utility Model Content

[0003] The purpose of the utility model is to overcome the deficiencies of the prior art and provide a power supply output circuit based on short-circuit protection and dual channels, which can effectively implement short-circuit protection and ensure the balance of output current during dual-channel output.

[0004] The purpose of the utility model is achieved through the following technical solutions: a power supply output circuit based on short-circuit protection and dual channels, comprising a short-circuit protection unit, a dual-channel output unit, an input port IN, a first output port OUT1 and a second output port OUT2;

[0005] The input port IN is used to connect to a power supply, the input end of the short-circuit protection unit is connected to the input port IN, the output end of the short-circuit protection unit is connected to the input end of the dual-channel output unit, the dual-channel output unit is respectively connected to the first output port OUT1 and the second output port OUT2, and power is supplied to the outside by the first output port OUT1 and the second output port OUT2.

[0006] The short-circuit protection unit includes a first MOS tube M1 and a first triode T1, wherein the source of the first MOS tube M1 is connected to the input port IN, and the drain of the first MOS tube M1 is connected to the input end of the dual-channel output unit as the output end of the short-circuit protection unit; the gate of the first MOS tube M1 is connected to the drain of the first MOS tube M1; a first resistor R1 is connected between the source and the drain of the first MOS tube M1, and the gate of the first MOS tube M1 is also grounded through a second resistor R2; and the drain of the first MOS tube M1 is also grounded through a first capacitor C1;

[0007] The emitter of the first transistor T1 is connected to the source of the first MOS transistor M1 , the base of the first transistor T1 is connected to the gate of the first MOS transistor M1 , and the collector of the first transistor T1 is connected to the base of the first transistor T1 .

[0008] The dual-channel output unit includes a second triode T2, a third triode T3, a second MOS tube M2, a third MOS tube M3 and a fully differential operational amplifier;

[0009] The bases of the second transistor T2 and the third transistor T3 are connected together as the input end of the dual-channel output unit, and connected to the drain of the first MOS transistor M1;

[0010] The emitter of the second transistor T2 is connected to the drain of the second MOS transistor M2, and the emitter of the third transistor T3 is connected to the drain of the third MOS transistor M3; the emitter of the second transistor T2 is also connected to the non-inverting input terminal of the full differential operational amplifier, and the emitter of the third transistor T3 is also connected to the inverting input terminal of the full differential operational amplifier; the collector of the second transistor T2 is connected to the first output port OUT1 of the dual-channel output unit; the collector of the third transistor T3 is connected to the second output port OUT2 of the dual-channel output unit;

[0011] The gate of the second MOS tube M2 is connected to the positive phase output terminal of the full differential operational amplifier; the gate of the third MOS tube M3 is also connected to the negative phase output terminal of the full differential operational amplifier; the source electrodes of the second MOS tube M2 and the third MOS tube M3 are connected together and grounded;

[0012] A second capacitor C2 is connected between the gate and drain of the second MOS transistor M2, and a third capacitor C3 is connected between the gate and drain of the third MOS transistor M3.

[0013] The beneficial effects of the utility model are as follows: the utility model can effectively realize short-circuit protection through the short-circuit protection current, and avoid the influence of large voltage fluctuations on electrical devices. Combined with the transient voltage suppression diode, it can further realize the suppression of large voltage, and can ensure the balance of output current when performing dual-channel output. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 It is a schematic diagram of the principle of the utility model. DETAILED DESCRIPTION

[0015] The technical solution of the present utility model is further described in detail below in conjunction with the accompanying drawings, but the protection scope of the present utility model is not limited to the following.

[0016] like Figure 1As shown, a power supply output circuit based on short-circuit protection and dual channels includes a short-circuit protection unit, a dual-channel output unit, an input port IN, a first output port OUT1 and a second output port OUT2;

[0017] The input port IN is used to connect to a power supply, the input end of the short-circuit protection unit is connected to the input port IN, the output end of the short-circuit protection unit is connected to the input end of the dual-channel output unit, the dual-channel output unit is respectively connected to the first output port OUT1 and the second output port OUT2, and power is supplied to the outside by the first output port OUT1 and the second output port OUT2.

[0018] In an embodiment of the present application, the short-circuit protection unit includes a first MOS tube M1 and a first triode T1, the source of the first MOS tube M1 is connected to the input port IN, and the drain of the first MOS tube M1 is connected to the input end of the dual-channel output unit as the output end of the short-circuit protection unit; the gate of the first MOS tube M1 is connected to the drain of the first MOS tube M1; a first resistor R1 is connected between the source and the drain of the first MOS tube M1, and the gate of the first MOS tube M1 is also grounded through a second resistor R2; the drain of the first MOS tube M1 is also grounded through a first capacitor C1;

[0019] The emitter of the first transistor T1 is connected to the source of the first MOS transistor M1 , the base of the first transistor T1 is connected to the gate of the first MOS transistor M1 , and the collector of the first transistor T1 is connected to the base of the first transistor T1 .

[0020] In the embodiment of the present application, the first MOS transistor M1 is an enhancement-mode NMOS transistor, and the first transistor T1 is a bipolar PNP transistor.

[0021] In an embodiment of the present application, the dual-channel output unit includes a second triode T2, a third triode T3, a second MOS tube M2, a third MOS tube M3 and a fully differential operational amplifier;

[0022] The bases of the second transistor T2 and the third transistor T3 are connected together as the input end of the dual-channel output unit, and connected to the drain of the first MOS transistor M1;

[0023] The emitter of the second transistor T2 is connected to the drain of the second MOS transistor M2, and the emitter of the third transistor T3 is connected to the drain of the third MOS transistor M3; the emitter of the second transistor T2 is also connected to the non-inverting input terminal of the full differential operational amplifier, and the emitter of the third transistor T3 is also connected to the inverting input terminal of the full differential operational amplifier; the collector of the second transistor T2 is connected to the first output port OUT1 of the dual-channel output unit; the collector of the third transistor T3 is connected to the second output port OUT2 of the dual-channel output unit;

[0024] The gate of the second MOS tube M2 is connected to the positive phase output terminal of the full differential operational amplifier; the gate of the third MOS tube M3 is also connected to the negative phase output terminal of the full differential operational amplifier; the source electrodes of the second MOS tube M2 and the third MOS tube M3 are connected together and grounded;

[0025] A second capacitor C2 is connected between the gate and drain of the second MOS transistor M2, and a third capacitor C3 is connected between the gate and drain of the third MOS transistor M3.

[0026] In the embodiment of the present application, the second transistor T2 and the third transistor T3 are both NPN transistors; the second MOS transistor M2 and the third MOS transistor M3 are both depletion-type NMOS transistors.

[0027] In an embodiment of the present application, the power output circuit further includes a transient voltage suppression diode TVS, one end of the transient voltage suppression diode TVS is connected to the input end of the dual-channel output unit, and the other end is grounded.

[0028] The working principle of the utility model is as follows:

[0029] After the input port IN of the utility model is connected to the power supply and the power supply is started, the first transistor T1 is turned on, so that the first MOS tube M1 is turned off, and the power supply supplies power to the dual-channel output unit through the input port and the first resistor R1, avoiding the impact caused by the power supply being turned on; until the voltage across the first capacitor C1 rises to a level sufficient to turn off the first transistor T1, the first transistor T1 is turned off, the first MOS tube M1 is turned on and provides a low-resistance transmission channel across the first resistor R1, and the power supply supplies power to the dual-channel output unit through the input port and the low-resistance transmission channel, and then enters the normal power supply state;

[0030] If a large voltage fluctuation occurs in the power supply (the voltage rises rapidly), the voltage between the emitters of the first transistor T1 rises rapidly, and after the conduction condition is met, the first transistor T1 is turned on again, thereby disconnecting the first MOS tube M1 again. During this period of time, the power supply supplies power to the dual-channel output unit through the input port and the first resistor R1, thereby reducing the current impact and suppressing the adverse effects of the large voltage. At the same time, since the transient voltage suppression diode TVS at the input end of the dual-channel output unit also has a suppressive effect on the transient high voltage, the dual-channel output unit and the electrical devices at the rear end of the dual-channel output unit can be effectively protected; since the voltage fluctuation is generally rapid, when the power supply returns to normal, it will also return to the normal power supply state; When a short circuit occurs in the electrical device at the rear end of the dual-channel output unit, the current flowing through the first MOS tube M1 will increase significantly, causing the voltage drop of the first MOS tube M1 to change, thereby enabling the first triode T1 to be turned on. At this time, the first MOS tube M1 will also be turned off. At this time, the power supply can still only supply power to the dual-channel output unit through the input port and the first resistor R1; after the short circuit is eliminated, it will return to the normal power supply state;

[0031] That is to say, through the circuit of the present application, when the voltage rises rapidly, or when the power supply is turned on, or when the back-end electrical device is short-circuited, power is supplied through the first resistor for protection, and when working normally, power is supplied by turning on the first MOS tube M1, which not only considers the voltage shock as protection for the back-end device, but also does not cause a large power waste under normal conditions;

[0032] For a dual-channel output unit, the input voltage will turn on the second transistor T2 and the third transistor T3, generating collector current. The collector current generates a voltage drop at the drain end of the depletion-type NMOS tube (the second MOS tube M2 and the third MOS tube M3). Ideally, when the current is equal, the base-to-emitter voltage drop of the two transistors (the second transistor T2 and the third transistor T3) should be equal, and the two input voltages of the fully differential operational amplifier are equal. When the current is not equal, the input voltage of the fully differential operational amplifier is different. For example, when the base current of the second transistor T2 is insufficient, the V BE The voltage drop is small, and the voltage at the positive input terminal of the fully differential operational amplifier is high, then the voltage at the positive output terminal increases, which increases the gate voltage of the second MOS tube M2, reduces the conduction voltage drop of M2, and increases the current, thereby compensating the output current of the second triode T2; the conduction voltage drop of M2 decreases, that is, the V DS The voltage of the positive input terminal of the fully differential operational amplifier is pulled down until the voltage of the two input terminals of the fully differential operational amplifier is equal, so that in the stable state, not only the V BE Equal, and at the same time the VDS The second MOS tube M2 and the third MOS tube M3 adopt the consumption type because they can still be turned on when the gate voltage is zero, avoiding the state that the output voltage of the fully differential operational amplifier is very low or zero when the power is turned on, which may occur when the enhanced MOS is used.

[0033] The above is a preferred embodiment of the utility model. It should be understood that the utility model is not limited to the form disclosed herein, and should not be regarded as excluding other embodiments, but can be used in other combinations, modifications and environments, and can be modified within the scope of the concept described herein through the above teachings or the technology or knowledge of the relevant field. The changes and modifications made by those skilled in the art do not deviate from the spirit and scope of the utility model, and should be within the scope of protection of the claims attached to the utility model.

Claims

1. A power output circuit based on short circuit protection and dual channels, characterized in that: It includes a short circuit protection unit, a dual-channel output unit, an input port IN, a first output port OUT1 and a second output port OUT2; The input port IN is used to connect to a power supply, the input end of the short-circuit protection unit is connected to the input port IN, the output end of the short-circuit protection unit is connected to the input end of the dual-channel output unit, the dual-channel output unit is connected to the first output port OUT1 and the second output port OUT2 respectively, and the first output port OUT1 and the second output port OUT2 are used to supply power to the outside; The short-circuit protection unit includes a first MOS tube M1 and a first triode T1, wherein the source of the first MOS tube M1 is connected to the input port IN, and the drain of the first MOS tube M1 is connected to the input end of the dual-channel output unit as the output end of the short-circuit protection unit; the gate of the first MOS tube M1 is connected to the drain of the first MOS tube M1; a first resistor R1 is connected between the source and the drain of the first MOS tube M1, and the gate of the first MOS tube M1 is also grounded through a second resistor R2; and the drain of the first MOS tube M1 is also grounded through a first capacitor C1; The emitter of the first transistor T1 is connected to the source of the first MOS transistor M1 , the base of the first transistor T1 is connected to the gate of the first MOS transistor M1 , and the collector of the first transistor T1 is connected to the base of the first transistor T1 .

2. A power output circuit based on short circuit protection and dual channels according to claim 1, characterized in that: The first MOS transistor M1 is an enhancement-mode NMOS transistor, and the first transistor T1 is a bipolar PNP transistor.

3. A power output circuit based on short circuit protection and dual channels according to claim 2, characterized in that: The dual-channel output unit includes a second triode T2, a third triode T3, a second MOS tube M2, a third MOS tube M3 and a fully differential operational amplifier; The bases of the second transistor T2 and the third transistor T3 are connected together as the input end of the dual-channel output unit, and connected to the drain of the first MOS transistor M1; The emitter of the second transistor T2 is connected to the drain of the second MOS transistor M2, and the emitter of the third transistor T3 is connected to the drain of the third MOS transistor M3; the emitter of the second transistor T2 is also connected to the non-inverting input terminal of the full differential operational amplifier, and the emitter of the third transistor T3 is also connected to the inverting input terminal of the full differential operational amplifier; the collector of the second transistor T2 is connected to the first output port OUT1 of the dual-channel output unit; the collector of the third transistor T3 is connected to the second output port OUT2 of the dual-channel output unit; The gate of the second MOS tube M2 is connected to the positive phase output terminal of the full differential operational amplifier; the gate of the third MOS tube M3 is also connected to the negative phase output terminal of the full differential operational amplifier; the source electrodes of the second MOS tube M2 and the third MOS tube M3 are connected together and grounded; A second capacitor C2 is connected between the gate and drain of the second MOS transistor M2, and a third capacitor C3 is connected between the gate and drain of the third MOS transistor M3.

4. A power output circuit based on short circuit protection and dual channels according to claim 3, characterized in that: The second transistor T2 and the third transistor T3 are both NPN transistors; the second MOS transistor M2 and the third MOS transistor M3 are both depletion-type NMOS transistors.

5. The power output circuit based on short circuit protection and dual channels according to claim 1, characterized in that: The power output circuit also includes a transient voltage suppression diode TVS, one end of the transient voltage suppression diode TVS is connected to the input end of the dual-channel output unit, and the other end is grounded.

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