Display device

Abstract

An embodiment of the present disclosure provides a display device including: a substrate including a display area and a pad portion outside the display area; and a plurality of pads in the pad portion. The plurality of pads are located in six rows, the six rows are arranged along a first direction, pads adjacent in the first direction among the plurality of pads are located in different layers, pads adjacent in a second direction among the plurality of pads are located in the same layer, and the second direction is perpendicular to the first direction and parallel to a direction in which the rows extend.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2023-0051505, filed on April 19, 2023, and all rights arising therefrom, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0002] The present disclosure relates to a display device. Background Art

[0003] Generally speaking, a display device includes a display area for displaying an image and a peripheral area located around the display area.

[0004] Electronic devices such as integrated circuits may be located in the peripheral region to generate or transmit electrical signals applied to the display region.

[0005] As the resolution of an image displayed in a display area increases, the number of wires transmitting electrical signals applied to the display area increases, and the number of pads corresponding to the wires and to which bumps of electronic components are coupled also increases. Utility Model Content

[0006] Embodiments have been made in an effort to provide a display device having an increased number of pads.

[0007] An embodiment of the present disclosure provides a display device, comprising: a substrate, comprising a display area and a pad portion outside the display area; and a plurality of pads located in the pad portion, wherein the plurality of pads are located in six rows arranged along a first direction, adjacent pads in the first direction among the plurality of pads are located in different layers, adjacent pads in a second direction among the plurality of pads are located in the same layer, and the second direction is perpendicular to the first direction and parallel to the direction in which the rows extend.

[0008] The plurality of pads may be connected to the plurality of wires, and 1 to 5 of the plurality of wires may be respectively located between two pads of the plurality of pads that are adjacent to each other in the second direction.

[0009] A distance between adjacent pads in the second direction may be in a range of about 25 micrometers (μm) to about 30 μm.

[0010] A width of each of the plurality of pads in the second direction may be in the range of about 5 μm to about 10 μm.

[0011] A width of each of the plurality of wires in the second direction may be in a range of about 2 μm to about 4 μm.

[0012] A distance between two wires adjacent in the second direction among the plurality of wires may be in the range of about 0.75 μm to about 4 μm.

[0013] Two wires adjacent to each other in the second direction among the plurality of wires may be located in different layers.

[0014] Some of the plurality of electrical wires may include one or more bends.

[0015] A total number of the plurality of pads located in the pad part may be in the range of 6,500 to 7,500.

[0016] The pad portion may include: a first pad, which is located in the same layer as the first gate conductive layer of the display area; and a second pad, which is located in the same layer as the second gate conductive layer of the display area, and the first pad and the second pad may be included in a plurality of pads and alternately positioned along the first direction and only the first pad or only the second pad may be located in the same row extending in the second direction.

[0017] The pad portion may include: a second pad located in the same layer as the second gate conductive layer of the display area; and a third pad located in the same layer as the third gate conductive layer of the display area, and the second pad and the third pad may be included in a plurality of pads and alternately positioned along the first direction and only the second pad or only the third pad may be located in the same row extending in the second direction.

[0018] The pad portion may include: a first pad, which is located in the same layer as the first gate conductive layer of the display area; and a third pad, which is located in the same layer as the third gate conductive layer of the display area, and the first pad and the third pad may be included in a plurality of pads and alternately positioned along the first direction and only the first pad or only the third pad may be located in the same row extending in the second direction.

[0019] The display device may further include: first wires, respectively connected to the first pads and located in the same layer as the first pads; and third wires, respectively connected to the third pads and located in the same layer as the third pads, and the first wires and the third wires may partially overlap in a direction perpendicular to the main surface of the substrate.

[0020] The display device may further include: a plurality of auxiliary pads located on the plurality of pads and electrically connected to the plurality of pads, and the plurality of auxiliary pads may be located in the same layer as the data conductive layer of the display area.

[0021] Another exemplary embodiment of the present disclosure provides a display device, including: a substrate, including a display area and a pad portion outside the display area; and a plurality of pads arranged in the pad portion along a first direction and a second direction perpendicular to the first direction, wherein the plurality of pads include a first pad, a second pad, and a third pad located in different layers, the plurality of pads are located in six rows arranged along the first direction, and the first pad, the second pad, and the third pad are alternately positioned along the first direction.

[0022] The first pad, the third pad, and the second pad may be alternately positioned along the second direction.

[0023] The pads located in the same layer among the plurality of pads may be arranged along a third direction which is an oblique direction between the first direction and the second direction.

[0024] Only the first pad, only the second pad, or only the third pad may be located in the same row extending in the second direction.

[0025] The plurality of pads may be connected to the plurality of wires, and 1 to 5 of the plurality of wires may be respectively located between two pads of the plurality of pads that are adjacent to each other in the second direction.

[0026] A distance between adjacent pads in the second direction among the plurality of pads may be in a range of about 25 μm to about 30 μm.

[0027] A width of each of the plurality of pads in the second direction may be in the range of about 5 μm to about 10 μm.

[0028] A width of each of the plurality of wires in the second direction may be in a range of about 2 μm to about 4 μm.

[0029] A distance between two wires adjacent in the second direction among the plurality of wires may be in the range of about 0.75 μm to about 4 μm.

[0030] Two wires adjacent to each other in the second direction among the plurality of wires may be located in different layers.

[0031] Some of the plurality of electrical wires may include one or more bends.

[0032] The first pad may be located in the same layer as the first gate conductive layer of the display area, the second pad may be located in the same layer as the second gate conductive layer of the display area, and the third pad may be located in the same layer as the third gate conductive layer of the display area.

[0033] The display device may further include: first wires, respectively connected to the first pads and located in the same layer as the first pads; second wires, respectively connected to the second pads and located in the same layer as the second pads; and third wires, respectively connected to the third pads and located in the same layer as the third pads, and the first wires and the third wires may partially overlap in a direction perpendicular to the main surface of the substrate.

[0034] A total number of the plurality of pads located in the pad part may be in the range of 6,500 to 7,500.

[0035] The display device may further include a plurality of auxiliary pads located on the plurality of pads and electrically connected to the plurality of pads, and the plurality of auxiliary pads may be located in the same layer as the data conductive layer of the display area.

[0036] According to the embodiments, it is possible to provide a display device having an increased number of pads. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 A display device according to an embodiment is schematically shown.

[0038] Figure 2 A pad portion in the display device according to the embodiment is separately shown.

[0039] Figure 3 Shown by Figure 1 An individual view of the portion indicated by "A".

[0040] Figure 4 Shows Figure 3 An enlarged view of portion "B" of FIG.

[0041] Figure 5 Pads and wires in another area are shown.

[0042] Figure 6 Shown along Figure 3 A cross-sectional view taken along line V-V'.

[0043] Figure 7 According to another embodiment, Figure 1 An individual view of the portion indicated by "A".

[0044] Figure 8 Shown along Figure 7 A cross-sectional view taken along line VIII-VIII'.

[0045] Fig. 9 According to yet another embodiment, Figure 1 An individual view of the portion indicated by "A".

[0046] Fig.10 Shown along Fig. 9 A cross-sectional view taken along line XX'.

[0047] Fig.11 According to yet another embodiment, Figure 1 An individual view of the portion indicated by "A".

[0048] Fig.12 Shows Fig.11 An enlarged view of portion "C".

[0049] Fig.13 Shown along Fig.11 A cross-sectional view taken along line XIII-XIII'.

[0050] Fig.14 According to another embodiment, Figure 1 An individual view of the portion indicated by "A".

[0051] Fig.15 Shown along Fig.14 A cross-sectional view taken along line XV-XV'.

[0052] Fig.16 Shown with Figure 8 A cross section corresponding to another embodiment of the present invention.

[0053] Fig.17 Shown with Fig.13 A cross section corresponding to another embodiment of the present invention.

[0054] Fig.18 A circuit diagram of a pixel of a display device according to an embodiment is shown.

[0055] Fig.19 shows a top view of a display device according to an embodiment, and Fig. 20 Shown along Fig.19 A cross-sectional view taken along line XX-XX'.

[0056] Figure 21 to Figure 26 1 and 2. Top views of display devices are sequentially shown depending on a manufacturing order of the display devices according to an embodiment. DETAILED DESCRIPTION

[0057] Hereinafter, the present invention will be described more fully with reference to the accompanying drawings, in which embodiments of the invention are shown.

[0058] As those skilled in the art would realize, the described embodiments may be modified in various ways, all without departing from the spirit or scope of the present invention.

[0059] In order to clearly describe the present invention, throughout the specification, parts irrelevant to the description are omitted, and the same reference numerals refer to the same or similar constituent elements.

[0060] In addition, since the sizes and thicknesses of constituent members shown in the drawings are arbitrarily given for better understanding and ease of description, the present invention is not limited to the sizes and thicknesses shown in the drawings.

[0061] In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity.

[0062] In the drawings, the thicknesses of some layers and regions are exaggerated for better understanding and ease of description.

[0063] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” another element, it can be directly on the other element or intervening elements may also be present.

[0064] In contrast, when an element is referred to as being “directly on” another element, there are no intervening elements present.

[0065] Furthermore, in the present specification, the wording “on” or “above” means being located on or below an object portion, and does not necessarily mean being located on the upper side of the object portion based on the direction of gravity.

[0066] In addition, unless explicitly described to the contrary, the word “comprise” and variations such as “comprising”, “including” or “having”, will be understood to imply the inclusion of stated elements but not the exclusion of any other elements.

[0067] Furthermore, throughout the specification, the phrase “in a plan view” means when an object portion is viewed from above, and the phrase “in a cross-sectional view” means when a cross section taken by vertically cutting the object portion is viewed from the side.

[0068] It will be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and / or portions, these elements, components, regions, layers and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or portion from another element, component, region, layer or portion. Therefore, the first element, component, region, layer or portion discussed below may be referred to as a second element, component, region, layer or portion without departing from the teachings herein.

[0069] As used herein, "about" or "approximately" includes the stated value and means within an acceptable range of deviation for that particular value as determined by one of ordinary skill in the art, taking into account the measurement in question and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations of the stated value, or within ±30%, ±20%, ±10%, or ±5% of the stated value.

[0070] Hereinafter, a display device according to an embodiment will be described in detail with reference to the accompanying drawings.

[0071] Figure 1 A display device according to an embodiment is schematically shown.

[0072] refer to Figure 1 , the display device according to the current embodiment includes a display area DA for displaying an image and a peripheral area NDA located around the display area DA.

[0073] The peripheral area NDA includes a pad portion PDA which is an area to which various electronic devices or a printed circuit board or the like are electrically attached.

[0074] A plurality of pads PD may be located in the pad portion PDA, and the pads PD are connected to pixels of the display area DA through wires W to transmit signals.

[0075] like Figure 1 As shown in , in the display device according to the current embodiment, the pads PD may be located in six rows arranged along the first direction DR1 , and the present disclosure relates to the arrangement of the pads PD.

[0076] That is, the display device according to the current embodiment is formed by arranging the pads PD in six rows and integrating the pads PD in the same space, thereby realizing a high-resolution display device.

[0077] In this case, it may be formed so that the distance between the pads PD and the wires W is minimized by positioning the pads PD adjacent in the second direction DR2 in the same layer and positioning the pads PD adjacent in the first direction DR1 in different layers.

[0078] In the following, reference will be made to Figure 3 The specific arrangement form and size of the pads PD and the wires W, the distance between the pads PD and the wires W, and the like are described in detail.

[0079] Figure 2 A pad portion PDA in the display device according to the embodiment is separately shown.

[0080] like Figure 2As shown in FIG. 1 , the pads PD are located in six rows arranged in the first direction DR1 in the pad portion PDA.

[0081] like Figure 2 As shown in , the pad PD may be formed in an inclined shape from the center to the edge, and the pad PD located at the center may be vertically positioned along the first direction DR1.

[0082] Therefore, if the pad PD is formed such that the tilt direction is different depending on the position thereof, alignment for contacting the pad PD can be easy, and the contact area of ​​the pad PD can be increased.

[0083] That is, the contact area of ​​the pad portion PDA may be increased by changing the position of the integrated circuit contacting the pad portion PDA in the first direction DR1.

[0084] In this case, the inclination angle θ of the pad PD located at the edge with respect to the first direction DR1 may be 15 to 20 degrees.

[0085] The inclination angle θ decreases toward the center and may become 0 degrees at the center.

[0086] In the current embodiment, the number of pads PD included in the pad portion PDA may be 6500 or more (eg, 6500 to 7500).

[0087] Although described separately later, the pads PD according to the current embodiment are arranged in six rows, and adjacent pads PD in the first direction DR1 are formed at different layers to minimize the distance between the pads PD and the wires W, thereby improving integration.

[0088] Accordingly, a plurality of pads PD may be formed in the same space, and a high-resolution display device may be realized.

[0089] As the number of pad PDs increases, health-related sensors such as multiple fingerprint implementations, body composition, blood pressure, and stress measurements can be added without separate drivers.

[0090] Figure 3 Shown by Figure 1 An individual view of the portion indicated by "A".

[0091] refer to Figure 3 , in the pad portion PDA according to the current embodiment, the pads PD are located in six rows.

[0092] That is to say, Figure 3 As shown in , six pads PD may be positioned side by side along the first direction DR1.

[0093] In this case, the pads PD adjacent to each other in the first direction DR1 may be located at different layers.

[0094] exist Figure 3 In the embodiment, the pads PD adjacent to each other in the second direction DR2 may be located in the same layer.

[0095] That is, some of the pads PD, which will be referred to as first pads PD1, may be connected to the first gate conductive layer of the display area DA (see Figure 6 GAT1 in is located in the same layer.

[0096] In this case, the wire W connected to the first pad PD1 and located in the same layer as the first gate conductive layer is referred to as a first wire W1.

[0097] In addition, some of the pads PD, which will be referred to as second pads PD2, may be connected to the second gate conductive layer of the display area DA (see Figure 6 GAT2 in is located in the same layer.

[0098] In this case, the wire W connected to the second pad PD2 and located in the same layer as the second gate conductive layer is referred to as a second wire W2.

[0099] That is, the first gate conductive layer GAT1 may exist in both the display area DA and the pad portion PDA, and in the pad portion PDA, the first gate conductive layer GAT1 may include the first pad PD1 and the first wire W1. The second gate conductive layer GAT2 may exist in both the display area DA and the pad portion PDA, and in the pad portion PDA, the second gate conductive layer GAT2 may include the second pad PD2 and the second wire W2.

[0100] Will refer to it later Figures 18 to 26 The first gate conductive layer GAT1 and the second gate conductive layer GAT2 of the display area DA are described separately.

[0101] refer to Figure 3 , the first pads PD1 and the second pads PD2 are alternately positioned along the first direction DR1.

[0102] In addition, only the first pads PD1 or only the second pads PD2 may be located in the same row along the second direction DR2.

[0103] That is, a row in which the first pads PD1 are located and a row in which the second pads PD2 are located may be alternately formed.

[0104] like Figure 3 As shown in FIG. 2 , in a first row in the second direction DR2 , three second wires W2 and two first wires W1 may be alternately positioned between adjacent first pads PD1 .

[0105] Next, in a second row in the second direction DR2 , two second wires W2 and two first wires W1 may be alternately positioned between adjacent second pads PD2 .

[0106] refer to Figure 3 , the first wire W1 connected to the first pad PD1 and the second wire W2 connected to the second pad PD2 may include a bent portion.

[0107] The wires W connected to each of the pads PD arranged in six rows arranged along the first direction DR1 should be located between two pads PD adjacent to each other in the second direction DR2, and therefore, some of the wires W may include a bent portion. In an embodiment, the bent portion may be located between the first pad PD1 and the second pad PD2.

[0108] exist Figure 3 , the first wire W1 connected to the first pad PD1 in the first row in the second direction DR2 (ie, the first pad PD1 located closest to the display area DA) may not include a bent portion.

[0109] However, the second wire W2 connected to the second pad PD2 in the second row in the second direction DR2 may include one bent portion.

[0110] Similarly, the first wire W1 connected to the first pad PD1 in the third row located in the second direction DR2 may include two bent portions.

[0111] Figure 4 Shows Figure 3 An enlarged view of portion "B" of FIG.

[0112] refer to Figure 4 A distance between the first pads PD1 adjacent to each other in the second direction DR2 (ie, a pitch H1 of the first pads PD1 in the second direction DR2) may be in the range of about 25 micrometers (μm) to about 30 μm.

[0113] In addition, a width H2 of each of the first pads PD1 in the second direction DR2 may be in the range of about 5 μm to about 10 μm.

[0114] In an embodiment, a width H3 of each of the first wires W1 in the second direction DR2 may be in a range of about 2 μm to about 4 μm.

[0115] In addition, in an embodiment, a width H4 of each of the second wires W2 in the second direction DR2 may be in a range of about 2 μm to about 4 μm.

[0116] The widths H3 of the first wires W1 may be the same or different.

[0117] Similarly, the width H4 of the second wires W2 may be the same or different.

[0118] The width H3 of the first wire W1 and the width H4 of the second wire W2 may be the same or different.

[0119] exist Figure 4 In an embodiment, each of a distance H5 between the first pad PD1 and the second wire W2 adjacent to each other in the second direction DR2 and a distance H5 between the second wire W2 and the first wire W1 adjacent to each other in the second direction DR2 may be in a range of about 0.75 μm to about 4 μm.

[0120] In another embodiment, the distance H5 between the corresponding wires may be the same or different.

[0121] In order to integrally form the pad in a high-resolution display device, it is desirable to minimize the distance between the pad and the wire.

[0122] However, if the distance between the pad and the wire becomes closer, a coupling problem may occur, and it is not easy to reduce the distance between the pad and the wire below a certain level.

[0123] In this case, a minimum distance between wires in the same layer may be about 3 μm or more, but a minimum distance between wires in different layers may be about 0.75 μm or more, which may be smaller than the minimum distance between wires in the same layer.

[0124] This is because when the wires are on different layers, insulation layers etc. are placed between the wires, thus reducing coupling problems.

[0125] Accordingly, in the display device according to the current embodiment, the wires W1 and W2 connected to the pads PD1 and PD2 in the pad portion PDA are alternately positioned at different layers.

[0126] Accordingly, the distance between the wires can be minimized without severe coupling problems, and a plurality of pads can be formed in the same space due to the integrated arrangement of the pads and the wires.

[0127] That is, in the current embodiment, the pitch H1 of the first pads PD1 in the second direction DR2 ranges from about 25 μm to about 30 μm, and one first pad PD1 and up to five wires W1 and W2 may be located within the pitch H1 without severe coupling problems.

[0128] The number of wires included in one pitch H1 decreases as the distance from the display area DA increases.

[0129] In this case, since the adjacent wires in the second direction DR2 are located at different layers, the distance between the wires can be minimized.

[0130] Figure 3 and Figure 4 The pad PD is not tilted, but as shown in the above reference Figure 2 As described, the pad PD may be inclined at an edge by a certain angle θ with respect to the first direction DR1.

[0131] Figure 5 The pad PD and the wires W1 and W2 in another area are shown.

[0132] refer to Figure 5 , the first pad PD1 , the first wire W1 , and the second wire W2 are each inclined at an angle θ with respect to the first direction DR1 .

[0133] In this case, the inclined angle θ may be greater than 0 degrees and less than 20 degrees.

[0134] Even in this case, a pitch H1 of the first pad PD1 in the second direction DR2 may be in the range of about 25 μm to about 30 μm, and a width H2 of the first pad PD1 in the second direction DR2 may be in the range of about 5 μm to about 10 μm.

[0135] In an embodiment, a width H3 of each of the first wires W1 in the second direction DR2 may be in a range of about 2 μm to about 4 μm.

[0136] In addition, in an embodiment, a width H4 of each of the second wires W2 in the second direction DR2 may be in a range of about 2 μm to about 4 μm. The widths H3 of the first wires W1 may be the same or different.

[0137] Similarly, the width H4 of the second wires W2 may be the same or different.

[0138] The width H3 of the first wire W1 and the width H4 of the second wire W2 may be the same or different.

[0139] Similarly, in an embodiment, each of the distance H5 between the first pad PD1 and the second wire W2 adjacent to each other in the second direction DR2 and the distance H5 between the second wire W2 and the first wire W1 adjacent to each other in the second direction DR2 (i.e., the distance parallel to the second direction DR2) can be in the range of about 0.75 μm to about 4 μm.

[0140] In this case, the orthogonal distance H5' may be shorter than the distance H5. The orthogonal distance H5' may be defined as a distance between the first and second wires W1 and W2 adjacent to each other in the second direction DR2 in a direction perpendicular to the tilt direction of the first wire W1.

[0141] The minimum distance for preventing coupling between the wires is based on the orthogonal distance H5 ′, and thus, the distance H5 near the pad located around the edge of the display device may be greater than the minimum distance.

[0142] That is, when the minimum distance for preventing coupling between the wires is about 0.75 μm, the distance H5 between the wires in the second direction DR2 may be greater than about 0.75 μm.

[0143] For example, the distance H5 near the pads located around the edge of the display device may have a greater value than the distance H5 between the pads located at the center in the second direction DR2.

[0144] In an embodiment, a pitch H1 of the first pad PD1 in the second direction DR2 may be about 28 μm, and a width H2 of the first pad PD1 in the second direction DR2 may be about 8 μm.

[0145] A width H3 of the first wire W1 in the second direction DR2 may be about 2.5 μm, and a width H4 of the second wire W2 in the second direction DR2 may be about 2.8 μm.

[0146] In addition, a distance H5 between the first pad PD1 and the second wire W2 adjacent to each other in the second direction DR2 and a distance H5 between the second wire W2 and the first wire W1 adjacent to each other in the second direction DR2 (ie, a distance parallel to the second direction DR2) may be about 1.1 μm.

[0147] Figure 6 Shown along Figure 3 A cross-sectional view taken along line V-V'.

[0148] refer to Figure 6 , the first gate conductive layer GAT1 is located on the substrate SUB, and the first gate conductive layer GAT1 includes a first pad PD1 and a first wire W1.

[0149] The first gate conductive layer GAT1 may include molybdenum (Mo), aluminum (Al), copper (Cu), and / or titanium (Ti), and may have a single-layer structure or a multi-layer structure of the above materials.

[0150] The first gate insulating layer GIL1 is located on the first gate conductive layer GAT1 and the substrate SUB, and the second gate conductive layer GAT2 is located on the first gate insulating layer GIL1.

[0151] The first gate insulating layer GIL1 may include silicon nitride (SiN x ), silicon oxide (SiO x ) and silicon oxynitride (SiO x N y ) of inorganic insulating materials.

[0152] The first gate insulating layer GIL1 may have a single-layer structure or a multi-layer structure of the above-mentioned materials.

[0153] The second gate conductive layer GAT2 may include molybdenum (Mo), aluminum (Al), copper (Cu), and / or titanium (Ti), and may have a single-layer structure or a multi-layer structure of the above materials.

[0154] The second gate conductive layer GAT2 includes a second pad PD2 and a second wire W2.

[0155] refer to Figure 6 , the first pad PD1 and the second wire W2 adjacent to each other are spaced apart by a predetermined distance H5 in the second direction DR2.

[0156] Similarly, the first electric wire W1 and the second electric wire W2 adjacent to each other are spaced apart by a predetermined distance H5 in the second direction DR2.

[0157] As described above, the distance H5 between the wires may be in the range of about 0.75 μm to about 4 μm.

[0158] In addition, a distance H6 between the second wires W2 and the second wires W2 in the same layer may be greater than or equal to about 3 μm.

[0159] That is, when all wires are located in the same layer, the minimum distance between two adjacent wires is about 3 μm or more, but in the current embodiment, the distance H5 between the adjacent wires in the second direction DR2 is effectively reduced by positioning the adjacent wires in the second direction DR2 in different layers.

[0160] Accordingly, the wires can be densely formed, and a large number of pads can be formed in the same space.

[0161] refer to Figure 6 , the second gate insulating layer GIL2 is located on the second gate conductive layer GAT2 and the first gate insulating layer GIL1.

[0162] The second gate insulating layer GIL2 may include silicon nitride (SiN x ), silicon oxide (SiO x ) and silicon oxynitride (SiO x N y ) of inorganic insulating materials.

[0163] The first and second gate insulating layers GIL1 and GIL2 define openings exposing the first and second pads PD1 and PD2, respectively.

[0164] The auxiliary pad APD may be located on the second gate insulating layer GIL2.

[0165] The auxiliary pad APD may contact the first pad PD1 and the second pad PD2 at the openings of the first and second gate insulating layers GIL1 and GIL2, respectively.

[0166] Such an auxiliary pad APD may be formed in the same layer as the data conductive layer of the display area DA, and may include the same material as that of the data conductive layer of the display area DA.

[0167] These auxiliary pads APD may have a single-layer structure or a multi-layer structure.

[0168] For example, the auxiliary pad APD may have a multi-layer structure including a first data conductive layer and a second data conductive layer.

[0169] The auxiliary pad APD may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W) and / or copper (Cu), etc., and may have a single-layer structure or a multi-layer structure of the above materials.

[0170] The integrated circuit IC may be positioned to overlap the pad portion PDA.

[0171] The integrated circuit IC may include a plurality of bumps BP.

[0172] The bumps BP may be electrically connected to the auxiliary pads APD.

[0173] To this end, an anisotropic conductive film ACF may be provided between the auxiliary pad APD and the bump BP.

[0174] The anisotropic conductive film ACF includes an adhesive member AD and conductive balls CB.

[0175] The adhesive member AD has adhesive force, and thus, the integrated circuit IC is adhered to the auxiliary pad APD on the substrate SUB.

[0176] In this case, the conductive balls CB may be provided between the bumps BP of the integrated circuit IC and the auxiliary pads APD, so that the bumps BP may be electrically connected to the corresponding auxiliary pads APD through the conductive balls CB.

[0177] exist Figures 3 to 6In the embodiment, the first pad PD1 and the first gate conductive layer GAT1 of the display area DA are located in the same layer, and the second pad PD2 and the second gate conductive layer GAT2 of the display area DA are located in the same layer have been described, but the present disclosure is not limited thereto.

[0178] In another embodiment, the first pad PD1 may be located in the same layer as the second gate conductive layer GAT2 of the display area DA, and the second pad PD2 may be located in the same layer as the first gate conductive layer GAT1 of the display area DA.

[0179] In addition, the first pad PD1 may be located in the same layer as the first gate conductive layer GAT1 of the display area DA and may be located in the same layer as the third gate conductive layer (see FIG. 1 ) of the display area DA. Figure 8 GAT3 in the third pad on the same layer (see Figure 8 PD3) in may be included to replace the second pad PD2.

[0180] Figure 7 According to another embodiment, Figure 1 An individual view of the portion indicated by "A".

[0181] In addition to the first pad PD1 being located in the same layer as the first gate conductive layer GAT1 of the display area DA and the third pad PD3 being located in the same layer as the third gate conductive layer GAT3 of the display area DA, Figure 7 Examples and Figure 3 That is, the third gate conductive layer GAT3 may exist in both the display area DA and the pad portion PDA, and in the pad portion PDA, the third gate conductive layer GAT3 may include a third pad PD3 and a third wire W3.

[0182] Detailed description of the same constituent elements will be omitted.

[0183] Will refer to it later Figures 18 to 26 The first gate conductive layer GAT1 , the second gate conductive layer GAT2 , and the third gate conductive layer GAT3 of the display area DA are described separately.

[0184] Figure 8 Shown along Figure 7 , and except that the first pad PD1 is located in the same layer as the first gate conductive layer GAT1 of the display area DA and the third pad PD3 is located in the same layer as the third gate conductive layer GAT3 of the display area DA, Figure 8 Examples and Figure 6 The same as the embodiment.

[0185] Detailed description of the same constituent elements will be omitted.

[0186] refer to Figure 8 The first gate conductive layer GAT1 is located on the substrate SUB, and the first gate conductive layer GAT1 includes a first pad PD1 and a first wire W1. The first gate insulating layer GIL1 and the second gate insulating layer GIL2 are sequentially located on the first gate conductive layer GAT1 and the substrate SUB.

[0187] The third gate conductive layer GAT3 is located on the second gate insulating layer GIL2, and the third gate conductive layer GAT3 includes a third pad PD3 and a third wire W3.

[0188] A width H7 of the third wire W3 in the second direction DR2 may be about 2 μm to about 4 μm.

[0189] The third gate conductive layer GAT3 may include molybdenum (Mo), aluminum (Al), copper (Cu) and / or titanium (Ti), and may have a single layer structure or a multilayer structure of the above materials. The third gate insulating layer GIL3 is located on the third gate conductive layer GAT3 and the second gate insulating layer GIL2.

[0190] The third gate insulating layer GIL3 may include silicon nitride (SiN x ), silicon oxide (SiO x ) and silicon oxynitride (SiO x N y ) of inorganic insulating materials.

[0191] The third gate insulating layer GIL3 may have a single-layer structure or a multi-layer structure of the above materials.

[0192] The first, second, and third gate insulating layers GIL1, GIL2, and GIL3 each have an opening exposing the first and third pads PD1 and PD3.

[0193] The auxiliary pad APD may be located on the third gate insulating layer GIL3.

[0194] The auxiliary pad APD may contact the first pad PD1 and the third pad PD3 at the openings of the first, second, and third gate insulating layers GIL1, GIL2, and GIL3, respectively.

[0195] In another embodiment, the second pad PD2 may be located in the same layer as the second gate conductive layer GAT2 of the display area DA, and the third pad PD3 may be located in the same layer as the third gate conductive layer GAT3 of the display area DA.

[0196] Fig. 9 According to yet another embodiment, Figure 1 An individual view of the portion indicated by "A".

[0197] In addition to the second pad PD2 being located in the same layer as the second gate conductive layer GAT2 of the display area DA and the third pad PD3 being located in the same layer as the third gate conductive layer GAT3 of the display area DA, Fig. 9 Examples and Figure 7 The same as the embodiment.

[0198] Detailed description of the same constituent elements will be omitted.

[0199] Fig.10 Shown along Fig. 9 , and except that the second pad PD2 is located in the same layer as the second gate conductive layer GAT2 of the display area DA and the third pad PD3 is located in the same layer as the third gate conductive layer GAT3 of the display area DA, Fig.10 Examples and Figure 8 The same as the embodiment.

[0200] Detailed description of the same constituent elements will be omitted.

[0201] refer to Fig.10 , the first gate insulating layer GIL1 is located on the substrate SUB, and the second gate conductive layer GAT2 is located on the first gate insulating layer GIL1.

[0202] The second gate conductive layer GAT2 includes a second pad PD2 and a second wire W2 , and a second gate insulating layer GIL2 is located on the second gate conductive layer GAT2 and the first gate insulating layer GIL1 .

[0203] The third gate conductive layer GAT3 is located on the second gate insulating layer GIL2, and the third gate conductive layer GAT3 includes a third pad PD3 and a third wire W3.

[0204] The third gate insulating layer GIL3 is located on the third gate conductive layer GAT3 and the second gate insulating layer GIL2.

[0205] The second and third gate insulating layers GIL2 and GIL3 have openings exposing the second and third pads PD2 and PD3 , respectively.

[0206] The auxiliary pad APD may be located on the third gate insulating layer GIL3.

[0207] The auxiliary pad APD may contact the second pad PD2 and the third pad PD3 at the openings of the second and third gate insulating layers GIL2 and GIL3 , respectively.

[0208] Previously, the pads were divided into two types of pads located at different layers, but according to another embodiment, the pads may include three types of pads located at different layers.

[0209] Fig.11 According to yet another embodiment, Figure 1 An individual view of the portion indicated by "A".

[0210] In addition to the first pad PD1 being located in the same layer as the first gate conductive layer GAT1 of the display area DA, the second pad PD2 being located in the same layer as the second gate conductive layer GAT2 of the display area DA, and the third pad PD3 being located in the same layer as the third gate conductive layer GAT3 of the display area DA, Fig.11 Examples and Figure 3 The same as the embodiment.

[0211] Detailed description of the same constituent elements will be omitted.

[0212] In this case, reference Fig.11 , pads of the same type are positioned in the second direction DR2.

[0213] In addition, the first pads PD1 , the second pads PD2 , and the third pads PD3 are alternately positioned in the first direction DR1 .

[0214] Fig.12 Shows Fig.11 An enlarged view of portion "C".

[0215] refer to Fig.12 , a width H2 of the first pad PD1 in the second direction DR2 may be in the range of about 5 μm to about 10 μm.

[0216] A width H3 of each of the first wires W1 in the second direction DR2 may be in the range of about 2 μm to about 4 μm.

[0217] In addition, a width H4 of each of the second wires W2 in the second direction DR2 may be in the range of about 2 μm to about 4 μm.

[0218] A width H7 of each of the third wires W3 in the second direction DR2 may be in the range of about 2 μm to about 4 μm.

[0219] The widths H3 of the first wires W1 may be the same or different.

[0220] Similarly, the width H4 of the second wires W2 may be the same or different.

[0221] Similarly, the width H7 of the third wires W3 may be the same or different.

[0222] The width H3 of the first wire W1 , the width H4 of the second wire W2 , and the width H7 of the third wire W3 may be the same or different.

[0223] exist Fig.12 In an embodiment, each of a distance H5 between the first pad PD1 and the third wire W3 adjacent to each other in the second direction DR2, a distance H5 between the third wire W3 and the second wire W2 adjacent to each other in the second direction DR2, and a distance H5 between the second wire W2 and the first wire W1 adjacent to each other in the second direction DR2 may be in the range of about 0.75 μm to about 4 μm.

[0224] In this case, the distance H5 between the respective electric wires may be the same or different.

[0225] Fig.13 Shown along Fig.11 , except that the first pad PD1 is located in the same layer as the first gate conductive layer GAT1 of the display area DA, the second pad PD2 is located in the same layer as the second gate conductive layer GAT2 of the display area DA, and the third pad PD3 is located in the same layer as the third gate conductive layer GAT3 of the display area DA, Fig.13 Examples and Figure 8 The same as the embodiment.

[0226] Detailed description of the same constituent elements will be omitted.

[0227] The first gate conductive layer GAT1 is located on the substrate SUB, and the first gate conductive layer GAT1 includes a first pad PD1 and a first wire W1.

[0228] The first gate insulating layer GIL1 is located on the first gate conductive layer GAT1 and the substrate SUB, and the second gate conductive layer GAT2 is located on the first gate insulating layer GIL1.

[0229] The second gate conductive layer GAT2 includes a second pad PD2 and a second wire W2.

[0230] The second gate insulating layer GIL2 is located on the second gate conductive layer GAT2 and the first gate insulating layer GIL1.

[0231] The third gate conductive layer GAT3 is located on the second gate insulating layer GIL2, and the third gate conductive layer GAT3 includes a third pad PD3 and a third wire W3.

[0232] The third gate insulating layer GIL3 is located on the third gate conductive layer GAT3 and the second gate insulating layer GIL2.

[0233] The first, second, and third gate insulating layers GIL1, GIL2, and GIL3 each have an opening exposing the first, second, and third pads PD1, PD2, and PD3.

[0234] The auxiliary pad APD may be located on the third gate insulating layer GIL3.

[0235] The auxiliary pad APD may contact the first pad PD1 , the second pad PD2 , and the third pad PD3 at the openings of the first, second, and third gate insulating layers GIL1 , GIL2 , and GIL3 , respectively.

[0236] Fig.14 According to another embodiment, Figure 1 An individual view of the portion indicated by "A".

[0237] according to Fig.14 In an embodiment, the first pad PD1 is located in the same layer as the first gate conductive layer GAT1 of the display area DA, the second pad PD2 is located in the same layer as the second gate conductive layer GAT2 of the display area DA, and the third pad PD3 is located in the same layer as the third gate conductive layer GAT3 of the display area DA.

[0238] In this case, in addition to the first pads PD1, the second pads PD2, and the third pads PD3 being alternately positioned in the first direction DR1 and the first pads PD1, the third pads PD3, and the second pads PD2 being alternately positioned in the second direction DR2, Fig.14 Examples and Fig.11 The same as the embodiment.

[0239] That is to say, Fig.14 Examples and Fig.11 The difference is that different pads are alternately positioned in the first direction DR1 and the second direction DR2.

[0240] like Fig.14 As shown in FIG. 1 , pads located in the same layer are arranged along a third direction DR3 between the first direction DR1 and the second direction DR2 .

[0241] That is to say, Fig.14 As shown in FIG. 1 , pads located in the same layer are positioned along a third direction DR3 which is an oblique direction between the first direction DR1 and the second direction DR2 .

[0242] Detailed description of the same constituent elements will be omitted.

[0243] Fig.15 Shown along Fig.14 , and except that it includes the first wire W1, the second wire W2, and the third wire W3 located between the first pad PD1 and the third pad PD3, Fig.15 Examples and Fig.13 The same as the embodiment.

[0244] Detailed description of the same constituent elements will be omitted.

[0245] Fig.14 A configuration is shown in which the first pad PD1, the second pad PD2 and the third pad PD3 are alternately positioned in the first direction DR1 and the first pad PD1, the third pad PD3 and the second pad PD2 are alternately positioned in the second direction DR2, but in another embodiment, the first pad PD1, the second pad PD2 and the third pad PD3 may be alternately positioned in the first direction DR1 and the second direction DR2, respectively.

[0246] In addition, in the previous embodiment, a configuration has been disclosed in which the first wire W1, the second wire W2, and the third wire W3 located in different layers do not overlap each other in the direction perpendicular to the main surface of the substrate SUB, but in some embodiments, the first wire W1 and the third wire W3 may partially overlap in the direction perpendicular to the main surface of the substrate SUB. Here, the "main surface" of the substrate SUB is parallel to the plane defined by the first direction DR1 and the second direction DR2.

[0247] Fig.16 Shown with Figure 8 A cross section corresponding to another embodiment of the present invention.

[0248] according to Fig.16 In the embodiment of the present invention, the first pad PD1 is located in the same layer as the first gate conductive layer GAT1 of the display area DA, and the third pad PD3 is located in the same layer as the third gate conductive layer GAT3 of the display area DA. In addition to the first wire W1 and the third wire W3 partially overlapping in a plan view (i.e., in a direction perpendicular to the main surface of the substrate SUB), Fig.16 Examples and Figure 8 The same as the embodiment.

[0249] Detailed description of the same constituent elements will be omitted.

[0250] exist Fig.16 In this case, the first gate insulating layer GIL1 and the second gate insulating layer GIL2 are located between the first wire W1 and the third wire W3, and therefore, even if the first wire W1 and the third wire W3 partially overlap in a direction perpendicular to the main surface of the substrate SUB, coupling can be effectively prevented by the first gate insulating layer GIL1 and the second gate insulating layer GIL2.

[0251] If the first wire W1 and the third wire W3 partially overlap in a plan view, the pitch between adjacent pads can be effectively reduced and the pads can be more integrated, which is advantageous for realizing a high-resolution display device.

[0252] Fig.17 Shown with Fig.13 A cross section corresponding to another embodiment of the present invention.

[0253] Except that the first wire W1 and the third wire W3 partially overlap in a plan view, Fig.17 Examples and Fig.13 The same as the embodiment.

[0254] Detailed description of the same constituent elements will be omitted.

[0255] refer to Fig.17 The first gate insulating layer GIL1 and the second gate insulating layer GIL2 are located between the first wire W1 and the third wire W3, and therefore, even if the first wire W1 and the third wire W3 partially overlap in a direction perpendicular to the main surface of the substrate SUB, coupling can be effectively prevented by the first gate insulating layer GIL1 and the second gate insulating layer GIL2.

[0256] If the first wire W1 and the third wire W3 partially overlap in a plan view, the pitch between adjacent pads can be effectively reduced and the pads can be more integrated, which is advantageous for realizing a high-resolution display device.

[0257] Next, a stack structure of a display region of the display device according to the current embodiment will be described.

[0258] However, the following description is only an example, and the structure of the display area is not limited to the following description.

[0259] The first gate conductive layer, the second gate conductive layer, and the third gate conductive layer of the above-mentioned display region may be described as follows.

[0260] Fig.18 A circuit diagram of a pixel PX of a display device according to an embodiment is shown.

[0261] like Fig.18 As shown in , according to the current embodiment, one pixel PX of the display device includes a plurality of transistors T1, T2, T3, T4, T5, T6, T7, and T8 connected to various signal lines, a storage capacitor Cst, and a light emitting diode LED.

[0262] A plurality of signal lines 127 , 128 , 151 , 152 , 153 , 154 , 155 , 156 , 171 , 172 , and 741 are connected to one pixel PX.

[0263] The signal lines 127, 128, 151, 152, 153, 154, 155, 156, 171, 172 and 741 include a first initialization voltage line 127, a second initialization voltage line 128, a first scan line 151, a second scan line 152, an initialization control line 153, a bypass control line 154, an emission control line 155, a reference voltage line 156, a data line 171, a driving voltage line 172 and a common voltage line 741.

[0264] The first scan line 151 is connected to a gate driver (not shown) to transmit the first scan signal GW to the second transistor T2.

[0265] A voltage having a polarity opposite to that of a voltage applied to the first scan line 151 may be applied to the second scan line 152 at the same timing as that of a signal of the first scan line 151 .

[0266] In an embodiment, for example, when a high voltage is applied to the first scan line 151 , a low voltage may be applied to the second scan line 152 .

[0267] The second scan line 152 transmits the second scan signal GC to the third transistor T3.

[0268] The initialization control line 153 transmits the initialization control signal GI to the fourth transistor T4.

[0269] The bypass control line 154 transmits the bypass signal GB to the seventh transistor T7 and the eighth transistor T8.

[0270] The bypass control line 154 may be formed by the next-stage first scan line 151 .

[0271] The emission control line 155 transmits the emission control signal EM to the fifth transistor T5 and the sixth transistor T6 .

[0272] The data line 171 is a wire for transmitting a data voltage DATA generated by a data driver (not shown), and the brightness of the light emitting diode LED emitting light is changed depending on the data voltage DATA applied to the pixel PX.

[0273] The driving voltage line 172 applies a driving voltage ELVDD, and the reference voltage line 156 applies a reference voltage VEH.

[0274] The first initialization voltage line 127 transmits a first initialization voltage VINT1 , and the second initialization voltage line 128 transmits a second initialization voltage VINT2 .

[0275] The common voltage line 741 applies the common voltage ELVSS to the cathode of the light emitting diode LED.

[0276] In the current embodiment, the voltage applied to the driving voltage line 172 , the reference voltage line 156 , the first and second initialization voltage lines 127 and 128 , and the common voltage line 741 may be a constant voltage.

[0277] Hereinafter, structures and connection relationships of the transistors T1 , T2 , T3 , T4 , T5 , T6 , T7 , and T8 will be described in detail.

[0278] The driving transistor T1 may have p-type transistor characteristics, and may include a polysilicon semiconductor.

[0279] The driving transistor T1 may receive the data voltage DATA depending on the switching operation of the second transistor T2 and may supply a driving current to the anode of the light emitting diode LED.

[0280] The brightness of the light emitting diode LED may be adjusted depending on the size of the driving current output to the anode of the light emitting diode LED, and thus, the brightness of the light emitting diode LED may be adjusted depending on the data voltage DATA applied to the pixel PX.

[0281] To this end, the first region of the driving transistor T1 is connected to the driving voltage line 172 via the fifth transistor T5 positioned to receive the driving voltage ELVDD.

[0282] In addition, the first region of the driving transistor T1 is connected to the second region of the second transistor T2 to receive the data voltage DATA.

[0283] Meanwhile, the second region of the driving transistor T1 is positioned to output a driving current toward the light emitting diode LED, and is connected to the anode of the light emitting diode LED via the sixth transistor T6.

[0284] In addition, the second region of the driving transistor T1 transfers the data voltage DATA applied to the first region of the driving transistor T1 to the third transistor T3 .

[0285] Meanwhile, the gate electrode of the driving transistor T1 is connected to a first electrode (hereinafter, referred to as a 'second storage electrode') of the storage capacitor Cst.

[0286] Accordingly, the voltage of the gate electrode of the driving transistor T1 changes depending on the voltage stored in the storage capacitor Cst, and the driving current output by the driving transistor T1 changes accordingly.

[0287] In addition, the storage capacitor Cst serves to keep the voltage of the gate electrode of the driving transistor T1 constant during one frame.

[0288] The second transistor T2 may have p-type transistor characteristics, and may include a polysilicon semiconductor.

[0289] The second transistor T2 is a transistor that receives the data voltage DATA into the pixel PX.

[0290] A gate electrode of the second transistor T2 may be connected to the first scan line 151 .

[0291] A first region of the second transistor T2 is connected to the data line 171 .

[0292] The second region of the second transistor T2 is connected to the first region of the driving transistor T1.

[0293] When the second transistor T2 is turned on by the first scan signal GW of a low voltage transmitted through the first scan line 151 , the data voltage DATA transmitted through the data line 171 is transmitted to the first region of the driving transistor T1 .

[0294] The third transistor T3 may have n-type transistor characteristics, and may include an oxide semiconductor.

[0295] The third transistor T3 electrically connects the second region of the driving transistor T1 and the gate electrode of the driving transistor T1 .

[0296] As a result, the third transistor T3 is a transistor in which a compensation voltage obtained by changing the data voltage DATA by means of the driving transistor T1 is transferred to the second storage electrode of the storage capacitor Cst.

[0297] A gate electrode of the third transistor T3 is connected to the second scan line 152, and a first region of the third transistor T3 is connected to a second region of the driving transistor T1.

[0298] A second region of the third transistor T3 is connected to the second storage electrode of the storage capacitor Cst and the gate electrode of the driving transistor T1.

[0299] The third transistor T3 is turned on by the second scan signal GC of a high voltage received through the second scan line 152 to connect the gate electrode of the driving transistor T1 and the second region of the driving transistor T1, and the voltage applied to the gate electrode of the driving transistor T1 is transmitted to the second storage electrode of the storage capacitor Cst and stored in the storage capacitor Cst.

[0300] The fourth transistor T4 may have n-type transistor characteristics, and may include an oxide semiconductor.

[0301] The fourth transistor T4 is used to initialize the gate electrode of the driving transistor T1 and the second storage electrode of the storage capacitor Cst.

[0302] A gate electrode of the fourth transistor T4 is connected to the initialization control line 153 , and a first region of the fourth transistor T4 is connected to the first initialization voltage line 127 .

[0303] The second region of the fourth transistor T4 is connected to the second storage electrode of the storage capacitor Cst, the gate electrode of the driving transistor T1, and the second region of the third transistor T3.

[0304] The fourth transistor T4 is turned on by the initialization control signal GI of a high voltage transmitted through the initialization control line 153 , and in this case, the first initialization voltage VINT1 is transmitted to the gate electrode of the driving transistor T1 and the second storage electrode of the storage capacitor Cst.

[0305] Accordingly, the voltage of the gate electrode of the driving transistor T1 and the voltage of the second storage electrode of the storage capacitor Cst are initialized.

[0306] The fifth transistor T5 may have p-type transistor characteristics, and may include a polysilicon semiconductor.

[0307] The fifth transistor T5 is used to transmit the driving voltage ELVDD to the driving transistor T1 .

[0308] A gate electrode of the fifth transistor T5 is connected to the emission control line 155 , a first region of the fifth transistor T5 is connected to the driving voltage line 172 , and a second region of the fifth transistor T5 is connected to the first region of the driving transistor T1 .

[0309] The sixth transistor T6 may have p-type transistor characteristics, and may include a polysilicon semiconductor.

[0310] The sixth transistor T6 is used to transmit the driving current output from the driving transistor T1 to the light emitting diode LED.

[0311] A gate electrode of the sixth transistor T6 is connected to the emission control line 155 , a first region of the sixth transistor T6 is connected to the second region of the driving transistor T1 , and a second region of the sixth transistor T6 is connected to the anode of the light emitting diode LED.

[0312] The seventh transistor T7 may have p-type transistor characteristics, and may include a polysilicon semiconductor.

[0313] The seventh transistor T7 is used to initialize the anode of the light emitting diode LED.

[0314] A gate electrode of the seventh transistor T7 is connected to the bypass control line 154 , a first region of the seventh transistor T7 is connected to the anode of the light emitting diode LED, and a second region of the seventh transistor T7 is connected to the second initialization voltage line 128 .

[0315] When the seventh transistor T7 is turned on by the bypass signal GB of the low voltage, the second initialization voltage VINT2 is applied to the anode of the light emitting diode LED to be initialized.

[0316] The eighth transistor T8 may have p-type transistor characteristics, and may include a polysilicon semiconductor.

[0317] A gate electrode of the eighth transistor T8 is connected to the bypass control line 154 , a first region of the eighth transistor T8 is connected to the reference voltage line 156 , and a second region of the eighth transistor T8 is connected to the first region of the driving transistor T1 .

[0318] When the eighth transistor T8 is turned on by the bypass signal GB of the low voltage, the reference voltage VEH is applied to the first region of the driving transistor T1.

[0319] It has been explained above that one pixel PX includes eight transistors T1 to T8 and one storage capacitor Cst, but the present invention is not limited thereto, and the number of transistors, the number of capacitors, and their connection relationship may be variously changed.

[0320] In the current embodiment, the driving transistor T1 may include a polysilicon semiconductor.

[0321] In addition, the third transistor T3 and the fourth transistor T4 may each include an oxide semiconductor.

[0322] The second transistor T2 , the fifth transistor T5 , the sixth transistor T6 , the seventh transistor T7 , and the eighth transistor T8 may each include a polysilicon semiconductor.

[0323] However, the present invention is not limited thereto, and in another embodiment, at least one of the second transistor T2 , the fifth transistor T5 , the sixth transistor T6 , the seventh transistor T7 , and the eighth transistor T8 may include an oxide semiconductor.

[0324] In the current embodiment, more stable driving and improved reliability may be achieved by allowing the third transistor T3 and the fourth transistor T4 to include a semiconductor material different from that of the driving transistor T1 .

[0325] In the following, reference will be made to Figures 19 to 26 The planar structures and cross-sectional structures of the driving transistor T1 , the third transistor T3 , and the fourth transistor T4 are further described.

[0326] Fig.19 shows a top view of a display device according to an embodiment, Fig. 20 Shown along Fig.19 A cross-sectional view taken along line XX-XX', and Figure 21 to Figure 261 and 2. Top views of display devices are sequentially shown depending on a manufacturing order of the display devices according to an embodiment. Figure 21 to Figure 26 Two adjacent pixels are shown, and the two pixels may have shapes symmetrical to each other. Hereinafter, the pixel located on the left side will be mainly described.

[0327] like Figures 19 to 26 As shown in , a polycrystalline silicon semiconductor layer including a channel 1132 of a driving transistor T1 , a first region 1131 , and a second region 1133 may be disposed on a substrate SUB.

[0328] Fig.21 A polysilicon semiconductor layer is shown.

[0329] The polycrystalline silicon semiconductor layer may further include a channel, a first region, and a second region of not only the driving transistor T1 but also each of the second transistor T2 , the fifth transistor T5 , the sixth transistor T6 , the seventh transistor T7 , and the eighth transistor T8 .

[0330] In a plan view, the channel 1132 of the driving transistor T1 may have a meander shape.

[0331] However, the shape of the channel 1132 of the driving transistor T1 is not limited thereto and may be variously changed.

[0332] In an embodiment, for example, the channel 1132 of the driving transistor T1 may be bent in various shapes, or may be formed in a stripe shape.

[0333] The first region 1131 and the second region 1133 of the driving transistor T1 may be located at opposite sides of the channel 1132 of the driving transistor T1 .

[0334] The first region 1131 of the driving transistor T1 extends upward and downward in a plan view, the upwardly extending portion of the first region 1131 may be connected to the second region of the second transistor T2 , and the downwardly extending portion of the first region 1131 may be connected to the second region of the fifth transistor T5 .

[0335] The second region 1133 of the driving transistor T1 may extend downward in a plan view to be connected to the first region of the sixth transistor T6 .

[0336] A first gate insulating layer 141 may be disposed on the polycrystalline silicon semiconductor layer including the channel 1132 of the driving transistor T1 , the first region 1131 and the second region 1133 , and the substrate SUB.

[0337] The first gate insulating layer 141 may include silicon nitride (SiN x ), silicon oxide (SiO x ) or silicon oxynitride (SiO x Ny ), and may have a x ), silicon oxide (SiO x ) or silicon oxynitride (SiO x N y ) single-layer or multi-layer structure.

[0338] A first gate conductive layer including a gate electrode 1151 of the driving transistor T1 may be positioned on the first gate insulating layer 141 .

[0339] Fig. 22 The polysilicon semiconductor layer and the first gate conductive layer are shown together.

[0340] The first gate conductive layer may include molybdenum (Mo), aluminum (Al), copper (Cu) and / or titanium (Ti), and may have a single-layer or multi-layer structure including molybdenum (Mo), aluminum (Al), copper (Cu) and / or titanium (Ti).

[0341] In a plan view, the gate electrode 1151 of the driving transistor T1 may overlap the channel 1132 of the driving transistor T1 .

[0342] The first gate conductive layer may further include a first initialization voltage line 127 , a first scan line 151 , an emission control line 155 , and a bypass control line 154 .

[0343] The first initialization voltage line 127 , the first scan line 151 , the emission control line 155 , and the bypass control line 154 may extend substantially in a horizontal direction.

[0344] The first initialization voltage line 127 may be connected to the first region 4136 of the fourth transistor T4.

[0345] The first scan line 151 may be connected to a gate electrode of the second transistor T2 .

[0346] A gate electrode of the fifth transistor T5 and a gate electrode of the sixth transistor T6 may be connected to the emission control line 155 .

[0347] A gate electrode of the seventh transistor T7 and a gate electrode of the eighth transistor T8 may be connected to a bypass control line 154 .

[0348] As described above, some of the pads PD of the pad portion PDA may be located in the same layer as the first gate conductive layer.

[0349] After forming the first gate conductive layer including the gate electrode 1151 of the driving transistor T1 , a doping process may be performed.

[0350] A portion of the polycrystalline silicon semiconductor layer covered by the first gate conductive layer may not be doped, and a portion of the polycrystalline silicon semiconductor layer not covered by the first gate conductive layer may be doped to have the same characteristics as those of a conductor.

[0351] In this case, the doping process may be performed with a p-type dopant, and the driving transistor T1 , the second transistor T2 , the fifth transistor T5 , the sixth transistor T6 , the seventh transistor T7 , and the eighth transistor T8 including the polysilicon semiconductor may have p-type transistor characteristics.

[0352] The second gate insulating layer 142 may be disposed on the first gate insulating layer 141 and the first gate conductive layer including the gate electrode 1151 of the driving transistor T1 .

[0353] The second gate insulating layer 142 may include silicon oxide (SiO x ), Silicon Nitride (SiN x ) or silicon oxynitride (SiO x N y ), and may have a x ), Silicon Nitride (SiN x ) or silicon oxynitride (SiO x N y ) single-layer or multi-layer structure.

[0354] A second gate conductive layer including a first storage electrode 1153 of the storage capacitor Cst may be positioned on the second gate insulating layer 142 .

[0355] Fig.23 A polysilicon semiconductor layer, a first gate conductive layer, and a second gate conductive layer are shown together.

[0356] The second gate conductive layer includes molybdenum (Mo), aluminum (Al), copper (Cu), silver (Ag), chromium (Cr), tantalum (Ta) and / or titanium (Ti), etc., and can have a single-layer or multi-layer structure including molybdenum (Mo), aluminum (Al), copper (Cu), silver (Ag), chromium (Cr), tantalum (Ta) and / or titanium (Ti), etc.

[0357] In a plan view, the first storage electrode 1153 overlaps the gate electrode 1151 of the driving transistor T1 to constitute a storage capacitor Cst.

[0358] An opening 1152 is formed in the first storage electrode 1153 of the storage capacitor Cst.

[0359] In a plan view, the opening 1152 of the first storage electrode 1153 of the storage capacitor Cst may overlap the gate electrode 1151 of the driving transistor T1 .

[0360] As described above, some of the pads PD of the pad portion PDA may be located in the same layer as the second gate conductive layer.

[0361] A first interlayer insulating layer 161 may be disposed on the second gate insulating layer 142 and the second gate conductive layer including the first storage electrode 1153 of the storage capacitor Cst.

[0362] The first interlayer insulating layer 161 may include silicon oxide (SiO x ), Silicon Nitride (SiN x ) or silicon oxynitride (SiO x N y ), and may have a x ), Silicon Nitride (SiN x ) or silicon oxynitride (SiO x N y ) single-layer or multi-layer structure.

[0363] An oxide semiconductor layer including the channel 3137 , the first region 3136 , and the second region 3138 of the third transistor T3 and the channel 4137 , the first region 4136 , and the second region 4138 of the fourth transistor T4 may be located on the first interlayer insulating layer 161 .

[0364] Fig.24 The polycrystalline silicon semiconductor layer, the first gate conductive layer, the second gate conductive layer, and the oxide semiconductor layer are shown together.

[0365] The oxide semiconductor layer may include indium gallium zinc oxide (IGZO) among indium gallium zinc-based oxides.

[0366] The channel 3137, the first area 3136, and the second area 3138 of the third transistor T3 and the channel 4137, the first area 4136, and the second area 4138 of the fourth transistor T4 may be connected to each other to be integrally formed. The first area 3136 and the second area 3138 of the third transistor T3 may be located on opposite sides of the channel 3137 of the third transistor T3. The first area 4136 and the second area 4138 of the fourth transistor T4 may be located on opposite sides of the channel 4137 of the fourth transistor T4. The second area 3138 of the third transistor T3 may be connected to the second area 4138 of the fourth transistor T4.

[0367] The third gate insulating layer 143 may be located on the first interlayer insulating layer 161 and the oxide semiconductor layer including the channel 3137, the first region 3136 and the second region 3138 of the third transistor T3 and the channel 4137, the first region 4136 and the second region 4138 of the fourth transistor T4. The third gate insulating layer 143 may include silicon oxide (SiO x ), Silicon Nitride (SiN x ) or silicon oxynitride (SiOx N y ), and may have a x ), Silicon Nitride (SiN x ) or silicon oxynitride (SiO x N y ) single-layer or multi-layer structure.

[0368] The third gate insulating layer 143 may be located on the entire surface of the oxide semiconductor layer and the first interlayer insulating layer 161. The third gate insulating layer 143 may cover the upper surface and side surface of the channel 3137, the first area 3136 and the second area 3138 of the third transistor T3 and the channel 4137, the first area 4136 and the second area 4138 of the fourth transistor T4. However, the present invention is not limited thereto, and in another embodiment, the third gate insulating layer 143 may not be located on the entire surface of the oxide semiconductor layer and the first interlayer insulating layer 161. In an embodiment, for example, the third gate insulating layer 143 may overlap with the channel 3137 of the third transistor T3 in a plan view, and may not overlap with the first area 3136 or the second area 3138 in a plan view. In addition, the third gate insulating layer 143 may overlap with the channel 4137 of the fourth transistor T4 in a plan view, and may not overlap with the first area 4136 or the second area 4138 in a plan view.

[0369] A third gate conductive layer including a gate electrode 3151 of the third transistor T3 and a gate electrode 4151 of the fourth transistor T4 may be positioned on the third gate insulating layer 143 . Fig.25 A polysilicon semiconductor layer, a first gate conductive layer, a second gate conductive layer, an oxide semiconductor layer, and a third gate conductive layer are shown together. The third gate conductive layer may include molybdenum (Mo), aluminum (Al), copper (Cu), and / or titanium (Ti), and may have a single layer or multilayer structure including molybdenum (Mo), aluminum (Al), copper (Cu), and / or titanium (Ti). In an embodiment, for example, the third gate conductive layer may include a lower layer including titanium and an upper layer including molybdenum.

[0370] In a plan view, the gate electrode 3151 of the third transistor T3 may overlap with the channel 3137 of the third transistor T3. In a plan view, the gate electrode 4151 of the fourth transistor T4 may overlap with the channel 4137 of the fourth transistor T4.

[0371] The third gate conductive layer may further include an initialization control line 153, a second scan line 152, and a reference voltage line 156. The initialization control line 153, the second scan line 152, and the reference voltage line 156 may extend substantially in a horizontal direction. The initialization control line 153 may be connected to the gate electrode 4151 of the fourth transistor T4. The second scan line 152 may be connected to the gate electrode 3151 of the third transistor T3. The reference voltage line 156 may be connected to the first region of the eighth transistor T8.

[0372] As described above, some of the pads PD of the pad portion PDA may be located in the same layer as the third gate conductive layer.

[0373] After forming the third gate conductive layer including the gate electrode 3151 of the third transistor T3 and the gate electrode 4151 of the fourth transistor T4, a doping process may be performed. The portion of the oxide semiconductor layer covered by the third gate conductive layer may not be doped, and the portion of the oxide semiconductor layer not covered by the third gate conductive layer may be doped to have the same characteristics as the characteristics of the conductor. The channel 3137 of the third transistor T3 may be located under the gate electrode 3151 to overlap with the gate electrode 3151 in a plan view. In a plan view, the first region 3136 and the second region 3138 of the third transistor T3 may not overlap with the gate electrode 3151. The channel 4137 of the fourth transistor T4 may be located under the gate electrode 4151 to overlap with the gate electrode 4151 in a plan view. In a plan view, the first region 4136 and the second region 4138 of the fourth transistor T4 may not overlap with the gate electrode 4151. The doping process of the oxide semiconductor layer may be performed with an n-type dopant, and the third transistor T3 and the fourth transistor T4 including the oxide semiconductor may have n-type transistor characteristics.

[0374] The second interlayer insulating layer 162 may be located on the third gate conductive layer including the gate electrode 3151 of the third transistor T3 and the gate electrode 4151 of the fourth transistor T4. The second interlayer insulating layer 162 may include silicon nitride (SiN x ), silicon oxide (SiO x ) or silicon oxynitride (SiO x N y ), and may have a single-layer or multi-layer structure including the material. The second interlayer insulating layer 162 may include a first opening 1165, a second opening 1166, a third opening 3165, a fourth opening 3166, a fifth opening 4165, and a sixth opening 4166.

[0375] In a plan view, the first opening 1165 may overlap at least a portion of the gate electrode 1151 of the driving transistor T1. The first opening 1165 may be further formed in the third gate insulating layer 143, the first interlayer insulating layer 161, and the second gate insulating layer 142. In a plan view, the first opening 1165 may overlap with the opening 1152 of the first storage electrode 1153. The first opening 1165 may be located inside the opening 1152 of the first storage electrode 1153. In a plan view, the second opening 1166 may overlap with at least a portion of the second region 3138 of the third transistor T3. The second opening 1166 may be further formed in the third gate insulating layer 143.

[0376] In a plan view, the third opening 3165 may overlap at least a portion of the second region 1133 of the driving transistor T1. The third opening 3165 may be further formed in the third gate insulating layer 143, the first interlayer insulating layer 161, the second gate insulating layer 142, and the first gate insulating layer 141. In a plan view, the fourth opening 3166 may overlap at least a portion of the first region 3136 of the third transistor T3. The fourth opening 3166 may be further formed in the third gate insulating layer 143.

[0377] In a plan view, the fifth opening 4165 may overlap at least a portion of the first region 4136 of the fourth transistor T4. The fifth opening 4165 may be further formed in the third gate insulating layer 143. In a plan view, the sixth opening 4166 may overlap at least a portion of the first initialization voltage line 127. The sixth opening 4166 may be further formed in the third gate insulating layer 143, the first interlayer insulating layer 161, and the second gate insulating layer 142.

[0378] A first data conductive layer including the first connection electrode 1175 , the second connection electrode 3175 , and the third connection electrode 4175 may be positioned on the second interlayer insulating layer 162 . Fig.26 A polysilicon semiconductor layer, a first gate conductive layer, a second gate conductive layer, an oxide semiconductor layer, a third gate conductive layer, and a first data conductive layer are shown together. The first data conductive layer may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), molybdenum (Mo), tantalum (Ta), titanium (Ti), tungsten (W), and / or copper (Cu), etc., and may have a single-layer structure or a multi-layer structure including the above materials. In an embodiment, for example, the first data conductive layer may have a three-layer structure of a lower film including a refractory metal such as molybdenum, chromium, tantalum, or titanium or an alloy thereof, an intermediate film including an aluminum-based metal, a silver-based metal, or a copper-based metal having low resistivity, and an upper film including a refractory metal such as molybdenum, chromium, tantalum, or titanium.

[0379] In a plan view, the first connection electrode 1175 may overlap with the gate electrode 1151 of the driving transistor T1. The first connection electrode 1175 may be connected to the gate electrode 1151 of the driving transistor T1 through the first opening 1165 and the opening 1152 of the first storage electrode 1153. In a plan view, the first connection electrode 1175 may overlap with the second region 3138 of the third transistor T3. The first connection electrode 1175 may be connected to the second region 3138 of the third transistor T3 through the second opening 1166. Accordingly, the gate electrode 1151 of the driving transistor T1 and the second region 3138 of the third transistor T3 may be connected through the first connection electrode 1175.

[0380] In a plan view, the second connection electrode 3175 may overlap with the second area 1133 of the driving transistor T1. The second connection electrode 3175 may be connected to the second area 1133 of the driving transistor T1 through the third opening 3165. In a plan view, the second connection electrode 3175 may overlap with the first area 3136 of the third transistor T3. The second connection electrode 3175 may be connected to the first area 3136 of the third transistor T3 through the fourth opening 3166. Accordingly, the second area 1133 of the driving transistor T1 and the first area 3136 of the third transistor T3 may be connected through the second connection electrode 3175.

[0381] In a plan view, the third connection electrode 4175 may overlap with the first region 4136 of the fourth transistor T4. The third connection electrode 4175 may be connected to the first region 4136 of the fourth transistor T4 through the fifth opening 4165. In a plan view, the third connection electrode 4175 may overlap with the first initialization voltage line 127. The third connection electrode 4175 may be connected to the first initialization voltage line 127 through the sixth opening 4166. Accordingly, the first region 4136 of the fourth transistor T4 and the first initialization voltage line 127 may be connected through the third connection electrode 4175.

[0382] The first data conductive layer may further include a second initialization voltage line 128. The second initialization voltage line 128 may extend substantially in a horizontal direction. The second initialization voltage line 128 may be connected to the second region of the seventh transistor T7.

[0383] As described above, the first data conductive layer of the auxiliary pad APD may be disposed in the same layer as the first data conductive layer of the display region. Accordingly, the first data conductive layer of the auxiliary pad APD may be disposed in the same layer as the first connection electrode 1175, the second connection electrode 3175, and the third connection electrode 4175. The first data conductive layer of the auxiliary pad APD may be disposed in the same layer as the second initialization voltage line 128.

[0384] The third interlayer insulating layer 180 may be positioned on the second interlayer insulating layer 162 and the first data conductive layer including the first connection electrode 1175 , the second connection electrode 3175 , and the third connection electrode 4175 .

[0385] The third interlayer insulating layer 180 may include an organic insulating material such as a general polymer (eg, polymethyl methacrylate (PMMA) or polystyrene (PS)), a polymer derivative having a phenol-based group, an acrylic polymer, polyimide, or a siloxane-based polymer.

[0386] A second data conductive layer including the data line 171 and the driving voltage line 172 may be disposed on the third interlayer insulating layer 180. The second data conductive layer may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), molybdenum (Mo), tantalum (Ta), titanium (Ti), tungsten (W), and / or copper (Cu), etc., and may have a single-layer structure or a multi-layer structure including the above materials.

[0387] The data line 171 and the driving voltage line 172 may extend substantially in a vertical direction. The data line 171 may be connected to the second transistor T2. The data line 171 may be connected to the first region of the second transistor T2. The driving voltage line 172 may be connected to the fifth transistor T5. The driving voltage line 172 may be connected to the first region of the fifth transistor T5. The driving voltage line 172 may be connected to the storage capacitor Cst. The driving voltage line 172 may be connected to the first storage electrode 1153 of the storage capacitor Cst. The first storage electrodes 1153 of the storage capacitors Cst of adjacent pixels may be connected to each other and may extend substantially in a horizontal direction.

[0388] As described above, the second data conductive layer of the auxiliary pad APD may be disposed in the same layer as the second data conductive layer of the display area. Accordingly, the second data conductive layer of the auxiliary pad APD may be disposed in the same layer as the data line 171 and the driving voltage line 172.

[0389] Although not shown, a passivation layer may be located on the third interlayer insulating layer 180 and the second data conductive layer including the data line 171 and the driving voltage line 172, and an anode may be located on the passivation layer. The anode may be connected to the sixth transistor T6 and may receive a driving current output from the driving transistor T1. A partition wall may be located on the anode. An opening is formed in the partition wall, and the opening of the partition wall may overlap with the anode in a plan view. A light emitting diode layer may be disposed in the opening of the partition wall. A cathode may be located on the light emitting element layer and the partition wall. The anode, the light emitting diode layer, and the cathode may constitute a light emitting diode LED.

[0390] As described above, in the display device according to the current embodiment, the pads are located in six rows, and the distance between the pads and the wires is minimized by positioning adjacent pads and wires in different layers. Accordingly, a plurality of pads can be located in the same space, it is possible to realize a high-resolution display device, and therefore, health-related sensors such as multiple fingerprint realization, body composition, blood pressure, and pressure measurement can be integrated.

[0391] While the disclosure has been described in connection with what are presently considered to be practical embodiments, it should be understood that the invention is not limited to the disclosed embodiments, but on the contrary, the invention is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the claims.

Claims

1. A display device, comprising: A substrate, comprising a display area and a pad portion outside the display area; as well as A plurality of pads located in the pad portion, wherein the plurality of pads are located in six rows, The six rows are arranged along a first direction, The pads adjacent to each other in the first direction among the plurality of pads are located in different layers, The pads adjacent to each other in the second direction among the plurality of pads are located in the same layer, and The second direction is perpendicular to the first direction and parallel to the direction in which the rows extend.

2. The display device according to claim 1, wherein The plurality of pads are connected to a plurality of wires, and One to five of the plurality of wires are respectively located between two of the plurality of pads that are adjacent to each other in the second direction.

3. The display device according to claim 1, wherein The distance between the adjacent pads in the second direction is in the range of 25 micrometers to 30 micrometers, and / or The width of each of the plurality of pads in the second direction is in a range of 5 micrometers to 10 micrometers, and / or A total number of the plurality of pads located in the pad portion is in the range of 6,500 to 7,500.

4. The display device according to claim 2, wherein The width of each of the plurality of wires in the second direction is in the range of 2 μm to 4 μm, and / or A distance between two adjacent wires in the second direction among the plurality of wires is in a range of 0.75 μm to 4 μm, and / or Two wires adjacent to each other in the second direction among the plurality of wires are located in different layers from each other, and / or Some of the plurality of wires include one or more bends.

5. The display device according to claim 1, wherein The pad portion comprises: A first pad is located in the same layer as the first gate conductive layer of the display area; and a second pad located in the same layer as the second gate conductive layer of the display area, wherein the first pad and the second pad are included in the plurality of pads and are alternately positioned along the first direction, and only the first pad or only the second pad is located in the same row extending in the second direction, or The pad portion includes: a second pad located in the same layer as the second gate conductive layer of the display area; and a third pad located in the same layer as the third gate conductive layer of the display area, wherein the second pad and the third pad are included in the plurality of pads and are alternately positioned along the first direction, and only the second pad or only the third pad is located in the same row extending in the second direction.

6. The display device according to claim 1, wherein The pad portion comprises: A first pad is located in the same layer as the first gate conductive layer of the display area; as well as The third pad is located in the same layer as the third gate conductive layer of the display area, and The display device further comprises: first wires connected to the first pads, respectively, and located in the same layer as the first pads; and third electric wires, respectively connected to the third pads and located in the same layer as the third pads, wherein the first pad and the third pad are included in the plurality of pads and are alternately positioned along the first direction, Only the first pads or only the third pads are located in the same row extending in the second direction, and The first electric wire and the third electric wire partially overlap in a direction perpendicular to the main surface of the substrate.

7. The display device according to any one of claims 1 to 6, further comprising: a plurality of auxiliary pads located on the plurality of pads and electrically connected to the plurality of pads, Wherein, the plurality of auxiliary pads and the data conductive layer of the display area are located in the same layer.

8. A display device, comprising: A substrate, comprising a display area and a pad portion outside the display area; as well as a plurality of pads arranged in the pad portion along a first direction and a second direction perpendicular to the first direction, The plurality of pads include a first pad, a second pad and a third pad located in different layers. The plurality of pads are located in six rows arranged along the first direction, and The first pads, the second pads, and the third pads are alternately positioned along the first direction.

9. The display device according to claim 8, wherein The first pad, the third pad and the second pad are alternately positioned along the second direction, and The pads located in the same layer among the plurality of pads are arranged along a third direction which is an oblique direction between the first direction and the second direction.

10. The display device according to claim 8, wherein Only the first pad, only the second pad, or only the third pad is located in the same row extending in the second direction, and / or The display device further comprises: first wires, respectively connected to the first pads and located in the same layer as the first pads; second wires, respectively connected to the second pads and located in the same layer as the second pads; and a third wire, respectively connected to the third pads and located in the same layer as the third pads, wherein the first pads are located in the same layer as the first gate conductive layer of the display area, the second pads are located in the same layer as the second gate conductive layer of the display area, the third pads are located in the same layer as the third gate conductive layer of the display area, and the first wire and the third wire partially overlap in a direction perpendicular to the main surface of the substrate.

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