Novel small-size multilayer chip type power divider
By adopting LTCC technology and upper and lower structure design of capacitive inductors, combined with high dielectric constant ceramic material and three-dimensional spiral inductors, the problem of large volume of existing power dividers is solved, and low loss and high isolation of miniaturized power dividers are achieved , high balance performance.
Patent Information
- Application Number
- CN202420861382.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-04-24
- Publication Date
- 2025-02-14
- Estimated Expiration
- 2034-04-24
AI Technical Summary
The existing power divider is large in size and is difficult to miniaturize in the circuit.
Low-temperature co-fired ceramic (LTCC) technology is used to manufacture small-size multi-layer chip power dividers. Through the upper and lower structure design of capacitors and inductors, combined with high dielectric constant ceramic materials and three-dimensional spiral inductors, miniaturization and high performance requirements are achieved.
The miniaturization of the power splitter is achieved, with the advantages of low loss, high isolation, high amplitude balance, high phase balance, high reliability, low cost and suitable for large-scale production.
Smart Images
Figure CN222483667U_ABST
Abstract
Description
Technical Field
[0001] The utility model discloses a power divider, in particular to a novel small-size multi-layer chip power divider, which can be applied to mobile communication facilities and various other communication equipments, and belongs to the technical field of electronic parts of communication equipments. Background Art
[0002] As a high-density packaging technology with a wide range of applications, Low Temperature Co-fired Ceramic (LTCC) has become the preferred way for the integration and modularization of electronic components in the future due to its excellent electronic, mechanical and thermal properties. It is widely used in the modular design of multi-layer chip circuits. The RF microwave components and modules designed and produced based on LTCC technology include balun filters, filters, multiplexers, duplexers, antennas, couplers, bridges, baluns, power dividers, receiving front-end modules, antenna switch modules, etc. In addition to its advantages in cost and integrated packaging, it has many advantages in wiring line width and line spacing, low impedance metallization, design diversity and high-frequency performance. As modern electronic equipment continues to develop towards miniaturization and high frequency, they have been widely used in miniaturized electronic equipment.
[0003] In the field of mobile communications, power distribution problems are often encountered, such as feeding the power of the transmitted signal to two or more antenna radiating units in proportion. At this time, a device that can feed the power of the signal source to several branch paths is needed - a power divider. The power divider in the prior art is limited by its own structure and is generally large in size. It is used in circuits without miniaturization. Summary of the invention
[0004] In view of the above-mentioned disadvantage of the large size of the power divider in the prior art, the utility model provides a new type of small-size multi-layer chip power divider, which adopts the miniaturized multi-layer chip structure made by LTCC technology, has the advantages of high reliability, low insertion loss, high isolation, small size, light weight, easy integration, low cost, etc., and is suitable for large-scale production. Therefore, it is widely used and can reduce the size to 0.65mm*0.50mm*0.35mm.
[0005] The utility model solves the technical problem by adopting a technical solution: a novel small-size multi-layer chip power divider, the power divider includes a ceramic substrate and an internal circuit structure layer arranged in the ceramic substrate, the internal circuit structure layer is as follows from bottom to top:
[0006] The first layer has four mutually insulated metal plane conductors printed on a ceramic dielectric substrate, which are respectively a first metal plane conductor, a second metal plane conductor, a third metal plane conductor and a fourth metal plane conductor. The first metal plane conductor is connected to the first point column, the second metal plane conductor is connected to the second point column, the third metal plane conductor is connected to the third point column, and the fourth metal plane conductor is connected to the fourth point column;
[0007] The second layer has a metal plane conductor printed on the ceramic dielectric substrate, which is the fifth metal plane conductor. The fifth metal plane conductor is connected to the fiftieth metal plane conductor. The fifth metal plane conductor and the fiftieth metal plane conductor are integrally arranged. The fiftieth metal plane conductor is connected to the fourth metal plane conductor in the first layer through a fourth point column.
[0008] The third layer has three mutually independent metal plane conductors printed on the ceramic dielectric substrate, which are a sixth metal plane conductor, a seventh metal plane conductor and an eighth metal plane conductor. The sixth metal plane conductor is connected to the ninth metal plane conductor, the sixth metal plane conductor and the ninth metal plane conductor are integrally arranged, the ninth metal plane conductor is connected to the first metal plane conductor in the first layer through a first point column, the seventh metal plane conductor is connected to the tenth metal plane conductor, the seventh metal plane conductor and the tenth metal plane conductor are integrally arranged, the tenth metal plane conductor is connected to the second metal plane conductor in the first layer through a second point column, the eighth metal plane conductor is connected to the eleventh metal plane conductor, the eighth metal plane conductor and the eleventh metal plane conductor are integrally arranged, and the eleventh metal plane conductor is connected to the third metal plane conductor in the first layer through a third point column;
[0009] The fourth layer has a metal plane conductor printed on the ceramic dielectric substrate, which is the twelfth metal plane conductor. The twelfth metal plane conductor is connected to the fifth metal plane conductor in the second layer through the fourth point column.
[0010] The fifth layer is a metal plane conductor printed on the ceramic dielectric substrate, which is the thirteenth metal plane conductor. The thirteenth metal plane conductor includes the fourteenth metal plane conductor, the fifteenth metal plane conductor and the sixteenth metal plane conductor. The fourteenth metal plane conductor, the fifteenth metal plane conductor and the sixteenth metal plane conductor intersect at the middle position of the thirteenth metal plane conductor. The fourteenth metal plane conductor is connected to the seventeenth metal plane conductor, the fifteenth metal plane conductor is connected to the eighteenth metal plane conductor, the sixteenth metal plane conductor is connected to the nineteenth metal plane conductor, the seventeenth metal plane conductor is connected to the ninth metal plane conductor in the second layer through the first point column, the eighteenth metal plane conductor is connected to the fifth point column, and the nineteenth metal plane conductor is connected to the sixth point column.
[0011] The sixth layer is printed with two mutually insulated metal plane conductors on the ceramic dielectric substrate, which are the 20th metal plane conductor and the 21st metal plane conductor. The 20th metal plane conductor and the 21st metal plane conductor are respectively in a "C" shape. One end of the 20th metal plane conductor is connected to the 22nd metal plane conductor, and the other end is connected to the 23rd metal plane conductor. The 22nd metal plane conductor is connected to the 18th metal plane conductor in the fifth layer through the fifth point column. The 23rd metal plane conductor is connected to the seventh point column. One end of the 21st metal plane conductor is connected to the 24th metal plane conductor, and the other end is connected to the 25th metal plane conductor. The 24th metal plane conductor is connected to the 19th metal plane conductor in the fifth layer through the sixth point column. The 25th metal plane conductor is connected to the eighth point column.
[0012] The seventh layer is printed with two mutually insulated metal plane conductors on the ceramic dielectric substrate, which are the twenty-sixth metal plane conductor and the twenty-seventh metal plane conductor. The twenty-sixth metal plane conductor and the twenty-seventh metal plane conductor are respectively in a "C" shape. One end of the twenty-sixth metal plane conductor is connected to the twenty-eighth metal plane conductor, and the other end is connected to the twenty-ninth metal plane conductor. The twenty-eighth metal plane conductor is connected to the twenty-third metal plane conductor in the sixth layer through the seventh dot column, and the twenty-ninth metal plane conductor is connected to the ninth dot column. One end of the twenty-seventh metal plane conductor is connected to the thirtieth metal plane conductor, and the other end is connected to the thirty-first metal plane conductor. The thirtieth metal plane conductor is connected to the twenty-fifth metal plane conductor in the sixth layer through the eighth dot column, and the thirty-first metal plane conductor is connected to the tenth dot column.
[0013] The eighth layer is printed with two mutually insulated metal plane conductors on the ceramic dielectric substrate, which are a thirty-second metal plane conductor and a thirty-third metal plane conductor. The thirty-second metal plane conductor and the thirty-third metal plane conductor are respectively in a "C" shape. One end of the thirty-second metal plane conductor is connected to the thirty-fourth metal plane conductor, and the other end is connected to the thirty-fifth metal plane conductor. The thirty-fourth metal plane conductor is connected to the twenty-ninth metal plane conductor in the seventh layer through the ninth dot column, and the thirty-fifth metal plane conductor is connected to the eleventh dot column. One end of the thirty-third metal plane conductor is connected to the thirty-sixth metal plane conductor, and the other end is connected to the thirty-seventh metal plane conductor. The thirty-sixth metal plane conductor is connected to the thirty-first metal plane conductor in the seventh layer through the tenth dot column, and the thirty-seventh metal plane conductor is connected to the twelfth dot column.
[0014] The ninth layer, two mutually insulated metal plane conductors are printed on the ceramic dielectric substrate, which are the thirty-eighth metal plane conductor and the thirty-ninth metal plane conductor. The thirty-eighth metal plane conductor and the thirty-ninth metal plane conductor are respectively in the shape of a letter "C". One end of the thirty-eighth metal plane conductor is connected to the fortieth metal plane conductor, and the other end is connected to the forty-first metal plane conductor. The fortieth metal plane conductor is connected to the thirty-fifth metal plane conductor in the eighth layer through the eleventh point column, and the forty-first metal plane conductor is connected to the thirteenth point column. One end of the thirty-ninth metal plane conductor is connected to the forty-second metal plane conductor, and the other end is connected to the forty-third metal plane conductor. The forty-second metal plane conductor is connected to the thirty-seventh metal plane conductor in the eighth layer through the twelfth point column, and the forty-third metal plane conductor is connected to the fourteenth point column.
[0015] The tenth layer has two mutually insulated metal plane conductors printed on the ceramic dielectric substrate, which are the forty-fourth metal plane conductor and the forty-fifth metal plane conductor. The forty-fourth metal plane conductor and the forty-fifth metal plane conductor are respectively in the shape of a letter "C". One end of the forty-fourth metal plane conductor is connected to the forty-sixth metal plane conductor, and the other end is connected to the forty-seventh metal plane conductor. The forty-sixth metal plane conductor is connected to the forty-first metal plane conductor in the ninth layer through the thirteenth point column. The forty-seventh metal plane conductor is connected to the tenth metal plane conductor in the third layer through the second point column. One end of the forty-fifth metal plane conductor is connected to the forty-eighth metal plane conductor, and the other end is connected to the forty-ninth metal plane conductor. The forty-eighth metal plane conductor is connected to the forty-third metal plane conductor in the ninth layer through the fourteenth point column. The forty-ninth metal plane conductor is connected to the eleventh metal plane conductor in the third layer through the third point column.
[0016] The technical solution adopted by the utility model to solve its technical problems further includes:
[0017] A Mark direction mark is arranged on the top of the ceramic substrate.
[0018] The first metal plane conductor, the second metal plane conductor, the third metal plane conductor and the fourth metal plane conductor are respectively arranged at four corners.
[0019] The fifth metal plane conductor is arranged in the middle position.
[0020] The twelfth metal plane conductor has the same shape as the fifth metal plane conductor in the second layer, and is stacked up and down.
[0021] The beneficial effects of the utility model are as follows: the utility model is based on LTCC (low temperature co-fired ceramic) technology, adopts the traditional Wilkinson power divider lumped parameter model design, and the capacitor and inductor adopt an upper and lower structure, wherein the capacitor is placed in the lower layer, which is convenient for forming a grounding capacitor with GND and reducing the parasitic inductance introduced by the connecting wire, and the inductor is placed in the upper layer to reduce the parasitic effect between the inductor and the capacitor, and the middle is connected by a point column. The lumped capacitor realizes a small volume and a large capacity through a high dielectric constant ceramic material, and the lumped inductor adopts a three-dimensional spiral inductor. At the same time, the two inductors are wound in opposite directions to reduce the mutual inductance between the inductors, improve the inductor Q value, and realize the high performance requirements of low insertion loss, high isolation, high amplitude balance, and high phase balance of a small multilayer ceramic chip power divider. The utility model effectively realizes the miniaturization of the power divider, and has the advantages of low loss, high isolation, high amplitude balance, high phase balance, high reliability, low cost, and suitability for large-scale production. The miniaturized multilayer chip power divider manufactured by the utility model using LTCC technology has the advantages of high reliability, low insertion loss, high isolation, small size, light weight, easy integration, low cost, etc. It is suitable for large-scale production and therefore has a wide range of applications.
[0022] The utility model will be further described below in conjunction with the accompanying drawings and specific implementation methods. BRIEF DESCRIPTION OF THE DRAWINGS
[0023] Figure 1 This is the equivalent circuit diagram of the utility model.
[0024] Figure 2 It is a schematic diagram of the three-dimensional structure of the utility model.
[0025] Figure 3 This is a schematic diagram of the three-dimensional structure of the utility model from another viewing angle.
[0026] Figure 4 It is a schematic diagram of the internal structure of the utility model.
[0027] Figure 5 This is a schematic diagram of the first-layer planar structure of the utility model.
[0028] Figure 6 It is a schematic diagram of the plane structure of the connection point column between the first layer and the second layer of the utility model.
[0029] Figure 7 This is a schematic diagram of the second-layer planar structure of the utility model.
[0030] Figure 8 This is a schematic diagram of the planar structure of the connection point column between the second and third floors of the utility model.
[0031] Fig. 9 This is a schematic diagram of the third-layer planar structure of the utility model.
[0032] Fig.10 It is a schematic diagram of the plane structure of the connection point column between the third and fourth floors of the utility model.
[0033] Fig.11 This is a schematic diagram of the fourth-layer plan structure of the utility model.
[0034] Fig.12 This is a schematic diagram of the planar structure of the connection point column between the fourth and fifth floors of the utility model.
[0035] Fig.13 This is a schematic diagram of the fifth-floor plan structure of the utility model.
[0036] Fig.14 This is a schematic diagram of the planar structure of the connection point column between the fifth and sixth floors of the utility model.
[0037] Fig.15 This is a schematic diagram of the sixth-floor plan structure of the utility model.
[0038] Fig.16 This is a schematic diagram of the planar structure of the connection point column between the sixth and seventh floors of the utility model.
[0039] Fig.17 This is a schematic diagram of the seventh-floor plan structure of the utility model.
[0040] Fig.18 This is a schematic diagram of the planar structure of the column layer at the connection point between the seventh and eighth floors of the utility model.
[0041] Fig.19 This is a schematic diagram of the eighth-floor plan structure of the utility model.
[0042] Fig. 20 This is a schematic diagram of the planar structure of the connection point column between the eighth and ninth floors of the utility model.
[0043] Fig.21 This is a schematic diagram of the ninth floor plan structure of the utility model.
[0044] Fig. 22 This is a schematic diagram of the planar structure of the connection point columns between the ninth and tenth floors of the utility model.
[0045] Fig.23 This is a schematic diagram of the tenth-floor plan structure of the utility model.
[0046] Fig.24 It is a schematic diagram of the planar structure of the top mark of the utility model.
[0047] Fig.25 This is the first electrical characteristic curve diagram of the utility model.
[0048] Fig.26 This is the second electrical characteristic curve diagram of the present utility model. DETAILED DESCRIPTION
[0049] This embodiment is a preferred implementation mode of the utility model. Other embodiments whose principles and basic structures are the same or similar to those of this embodiment are within the protection scope of the utility model.
[0050] The utility model provides a novel small-size multilayer chip-type two-equal power divider. In this embodiment, the product size can be reduced to 0.65mm*0.50mm*0.35mm, and the passband frequency is 2.4~2.5GHz WiFi frequency band. The power divider adopts a special structure designed by a traditional Wilkinson power divider lumped parameter model, that is, one input port and two output ports. After the signal enters the two-equal power divider through the input port, the power is evenly distributed to the two output ports. The power divider of the utility model has the advantages of low insertion loss, high isolation, and highly consistent amplitude and phase.
[0051] Please see attached Figure 1 , Figure 1 This is a schematic diagram of the equivalent circuit of a small-size multilayer chip power divider of the utility model, including capacitor C1, capacitor C2, capacitor C3, inductor L1 and inductor L2. The equivalent circuit has an input port, namely port 1, and two output ports, namely port 2 and port 3. In the utility model, port 2 is defined as the first output port, and port 3 is defined as the second output port. Capacitor C1 is connected between the input port and the ground, capacitor C2 is connected between the first output port and the ground, capacitor C3 is connected between the second output port and the ground, inductor L1 is connected in series between the input port and the first output port, and inductor L2 is connected in series between the input port and the second output port. The equivalent circuit of the utility model is two equally divided paths of a two-equal power divider, which is a symmetrical structure, and the first output port and the second output port are two equally divided power output ports. When in use, an external isolation resistor with a resistance of 100Ω is connected across the first output port and the second output port.
[0052] Please refer to the attached Figure 2 To Attachment Fig.24The utility model includes a ceramic substrate and an internal circuit structure layer arranged in the ceramic substrate. In the present embodiment, the ceramic substrate is the main body of the utility model, and a circular pattern is provided on the top of the ceramic substrate, which is the Mark direction mark 10. The bottom of the ceramic substrate is the terminal electrode, that is, the welding pad. In the present embodiment, there are four terminal electrodes, which are respectively arranged at the four corners of the ceramic substrate. Since the terminal electrodes of the utility model are not symmetrical, it is necessary to set the Mark direction mark 10 on the top of the ceramic substrate. The ceramic substrate adopts a rectangular structure, which is mainly composed of aluminum oxide (Al2O3), calcium oxide (CaO), magnesium oxide (MgO) and silicon oxide (SiO2). The internal circuit structure layer is distributed inside the ceramic substrate. There are ten internal circuit structure layers in total. The internal circuit structure layers are from bottom to top (with the direction in the attached figure as the direction):
[0053] The first layer has four mutually insulated metal plane conductors printed on a ceramic dielectric substrate, which are the first metal plane conductor P1, the second metal plane conductor P2, the third metal plane conductor P3 and the fourth metal plane conductor P4. The first metal plane conductor P1, the second metal plane conductor P2, the third metal plane conductor P3 and the fourth metal plane conductor P4 are respectively arranged at four corners, corresponding to the four end electrodes of the utility model, that is, the pads, wherein the first metal plane conductor P1 is the input port of the power divider of the utility model, the second metal plane conductor P2 is the first equally divided power output port of the utility model, the third metal plane conductor P3 is the second equally divided power output port of the utility model, and the fourth metal plane conductor P4 is the internal RF grounding port of the power divider of the utility model. In this embodiment, the first metal plane conductor P1 is connected to the first point column 11, the second metal plane conductor P2 is connected to the second point column 12, the third metal plane conductor P3 is connected to the third point column 13, and the fourth metal plane conductor P4 is connected to the fourth point column 14;
[0054] The second layer is a metal plane conductor printed on a ceramic dielectric substrate, which is the fifth metal plane conductor 1. The fifth metal plane conductor 1 is connected to the fiftieth metal plane conductor 1a. The fifth metal plane conductor 1 and the fiftieth metal plane conductor 1a are integrally arranged. The fifth metal plane conductor 1 is a GND capacitor substrate of capacitors C1, C2 and C3 in the equivalent circuit. The fifth metal plane conductor 1 is arranged in the middle position. The fiftieth metal plane conductor 1a is connected to the fourth metal plane conductor P4 in the first layer through a fourth point column 14.
[0055] The third layer has three independent metal plane conductors printed on the ceramic dielectric substrate, which are the sixth metal plane conductor 2-1, the seventh metal plane conductor 2-2 and the eighth metal plane conductor 2-3. The sixth metal plane conductor 2-1 is the C1 capacitor substrate for grounding the input end of the power divider in the equivalent circuit, the seventh metal plane conductor 2-2 is the C2 capacitor substrate for grounding the equally divided output port of the power divider in the equivalent circuit, and the eighth metal plane conductor 2-3 is the C3 capacitor substrate for grounding the equally divided output port of the power divider in the equivalent circuit. The ninth metal plane conductor 2-1a is connected to the sixth metal plane conductor 2-1, and the sixth metal plane conductor 2-1 and the ninth metal plane conductor The body 2-1a is integrally arranged, and the overall shape is "cleaver", the ninth metal plane conductor 2-1a is connected to the first metal plane conductor P1 in the first layer through the first point column 11, the seventh metal plane conductor 2-2 is connected to the tenth metal plane conductor 2-2a, the seventh metal plane conductor 2-2 and the tenth metal plane conductor 2-2a are integrally arranged, and the overall shape is "L", the tenth metal plane conductor 2-2a is connected to the second metal plane conductor P2 in the first layer through the second point column 12, the eighth metal plane conductor 2-3 is connected to the eleventh metal plane conductor 2-3a, the eighth metal plane conductor 2-3 and the eleventh metal plane conductor 2-3a are integrally arranged, and the overall shape is "L", and the eleventh metal plane conductor 2-3a is connected to the third metal plane conductor P3 in the first layer through the third point column 13;
[0056] The fourth layer is a metal plane conductor printed on the ceramic dielectric substrate, which is the twelfth metal plane conductor 3. The twelfth metal plane conductor 3 is arranged in the middle position. The twelfth metal plane conductor 3 is connected to the fifth metal plane conductor 1 in the second layer through the fourth point column 14. In this embodiment, the twelfth metal plane conductor 3 has the same shape as the fifth metal plane conductor 1 in the second layer, and is stacked up and down. The twelfth metal plane conductor 3 is the GND capacitor substrate of the capacitor C1, the capacitor C2 and the capacitor C3 in the equivalent circuit;
[0057] The fifth layer is a metal plane conductor printed on the ceramic dielectric substrate, which is the thirteenth metal plane conductor 4. The thirteenth metal plane conductor 4 divides the input signal into two. The thirteenth metal plane conductor 4 includes a fourteenth metal plane conductor 4-1, a fifteenth metal plane conductor 4-2 and a sixteenth metal plane conductor 4-3. The fourteenth metal plane conductor 4-1, the fifteenth metal plane conductor 4-2 and the sixteenth metal plane conductor 4-3 intersect at the middle position of the thirteenth metal plane conductor 4. The fourteenth metal plane conductor 4-1 is connected to the first metal plane conductor 4-2. The seventeenth metal plane conductor 4-1a, the fifteenth metal plane conductor 4-2 is connected to the eighteenth metal plane conductor 4-1b, the sixteenth metal plane conductor 4-3 is connected to the nineteenth metal plane conductor 4-1c, the seventeenth metal plane conductor 4-1a is connected to the ninth metal plane conductor 2-1a in the second layer through the first point column 11, the eighteenth metal plane conductor 4-1b is connected to the fifth point column 15, the nineteenth metal plane conductor 4-1c is connected to the sixth point column 16, and the thirteenth metal plane conductor 4 is a metal coil conductor;
[0058] The sixth layer is printed with two mutually insulated metal plane conductors on the ceramic dielectric substrate, which are the twentieth metal plane conductor 5-1 and the twenty-first metal plane conductor 5-2. The twentieth metal plane conductor 5-1 and the twenty-first metal plane conductor 5-2 are respectively called "C" shapes. One end of the twentieth metal plane conductor 5-1 is connected to the twenty-second metal plane conductor 5-1a, and the other end is connected to the twenty-third metal plane conductor 5-1b. The twenty-second metal plane conductor 5-1a is connected to the eighteenth metal plane conductor 4-1b in the fifth layer through the fifth point column 15. The twenty-third metal plane conductor 5-1b is connected to the seventh point column 17. One end of the twenty-first metal plane conductor 5-2 is connected to the twenty-fourth metal plane conductor 5-2a, and the other end is connected to the twenty-fifth metal plane conductor 5-2b. The twenty-fourth metal plane conductor 5-2a is connected to the nineteenth metal plane conductor 4-1c in the fifth layer through the sixth point column 16. The twenty-fifth metal plane conductor 5-2b is connected to the eighth point column 18.
[0059] The seventh layer is printed with two mutually insulated metal plane conductors on the ceramic dielectric substrate, which are the twenty-sixth metal plane conductor 6-1 and the twenty-seventh metal plane conductor 6-2. The twenty-sixth metal plane conductor 6-1 and the twenty-seventh metal plane conductor 6-2 are respectively called "C" shapes. One end of the twenty-sixth metal plane conductor 6-1 is connected to the twenty-eighth metal plane conductor 6-1a, and the other end is connected to the twenty-ninth metal plane conductor 6-1b. The twenty-eighth metal plane conductor 6-1a is connected to the twenty-third metal plane conductor 5-1b in the sixth layer through the seventh point column 17, and the twenty-ninth metal plane conductor 6-1b is connected to the ninth point column 19. One end of the twenty-seventh metal plane conductor 6-2 is connected to the thirtieth metal plane conductor 6-2a, and the other end is connected to the thirty-first metal plane conductor 6-2b. The thirtieth metal plane conductor 6-2a is connected to the twenty-fifth metal plane conductor 5-2b in the sixth layer through the eighth point column 18, and the thirty-first metal plane conductor 6-2b is connected to the tenth point column 20.
[0060] The eighth layer is printed with two mutually insulated metal plane conductors on the ceramic dielectric substrate, which are the thirty-second metal plane conductor 7-1 and the thirty-third metal plane conductor 7-2. The thirty-second metal plane conductor 7-1 and the thirty-third metal plane conductor 7-2 are respectively called "C" shapes. One end of the thirty-second metal plane conductor 7-1 is connected to the thirty-fourth metal plane conductor 7-1a, and the other end is connected to the thirty-fifth metal plane conductor 7-1b. The thirty-fourth metal plane conductor 7-1a is connected to the twenty-ninth metal plane conductor 6-1b in the seventh layer through the ninth point column 19, and the thirty-fifth metal plane conductor 7-1b is connected to the eleventh point column 21. One end of the thirty-third metal plane conductor 7-2 is connected to the thirty-sixth metal plane conductor 7-2a, and the other end is connected to the thirty-seventh metal plane conductor 7-2b. The thirty-sixth metal plane conductor 7-2a is connected to the thirty-first metal plane conductor 6-2b in the seventh layer through the tenth point column 20, and the thirty-seventh metal plane conductor 7-2b is connected to the twelfth point column 22.
[0061] The ninth layer, two mutually insulated metal plane conductors are printed on the ceramic dielectric substrate, which are the thirty-eighth metal plane conductor 8-1 and the thirty-ninth metal plane conductor 8-2. The thirty-eighth metal plane conductor 8-1 and the thirty-ninth metal plane conductor 8-2 are respectively called "C" shapes. One end of the thirty-eighth metal plane conductor 8-1 is connected to the fortieth metal plane conductor 8-1a, and the other end is connected to the forty-first metal plane conductor 8-1b. The fortieth metal plane conductor 8-1a is connected to the thirty-fifth metal plane conductor 7-1b in the eighth layer through the eleventh point column 21, and the forty-first metal plane conductor 8-1b is connected to the thirteenth point column 23. The thirty-ninth metal plane conductor 8-2 is connected to the forty-second metal plane conductor 8-2a at one end, and the other end is connected to the forty-third metal plane conductor 8-2b. The forty-second metal plane conductor 8-2a is connected to the thirty-seventh metal plane conductor 7-2b in the eighth layer through the twelfth point column 22, and the forty-third metal plane conductor 8-2b is connected to the fourteenth point column 24.
[0062] In the tenth layer, two mutually insulated metal plane conductors are printed on the ceramic dielectric substrate, namely the forty-fourth metal plane conductor 9-1 and the forty-fifth metal plane conductor 9-2. The forty-fourth metal plane conductor 9-1 and the forty-fifth metal plane conductor 9-2 are respectively in the shape of a letter "C". One end of the forty-fourth metal plane conductor 9-1 is connected to the forty-sixth metal plane conductor 9-1a, and the other end is connected to the forty-seventh metal plane conductor 9-1b. The forty-sixth metal plane conductor 9-1a is connected to the forty-first metal plane conductor 8-1 in the ninth layer through the thirteenth point column 23. b is connected, the forty-seventh metal plane conductor 9-1b is connected to the tenth metal plane conductor 2-2a in the third layer through the second point column 12, one end of the forty-fifth metal plane conductor 9-2 is connected to the forty-eighth metal plane conductor 9-2a, and the other end is connected to the forty-ninth metal plane conductor 9-2b, the forty-eighth metal plane conductor 9-2a is connected to the forty-third metal plane conductor 8-2b in the ninth layer through the fourteenth point column 24, and the forty-ninth metal plane conductor 9-2b is connected to the eleventh metal plane conductor 2-3a in the third layer through the third point column 13;
[0063] Among them, the inductance L1 in the equivalent circuit is composed of the fifteenth metal planar conductor 4-2, the twentieth metal planar conductor 5-1, the twenty-sixth metal planar conductor 6-1, the thirty-second metal planar conductor 7-1, the thirty-eighth metal planar conductor 8-1, the forty-fourth metal planar conductor 9-1 and the fifth point column 15, the seventh point column 17, the ninth point column 19, the eleventh point column 21, and the thirteenth point column 23; the inductance L2 in the equivalent circuit is composed of the sixteenth metal planar conductor 4-3, the twenty-first metal planar conductor 5-2, the twenty-seventh metal planar conductor 6-2, the thirty-third metal planar conductor 7-2, the thirty-ninth metal planar conductor 8-2, the forty-fifth metal planar conductor 9-2 and the sixth point column 16, the eighth point column 18, the tenth point column 20, the twelfth point column 22, and the fourteenth point column 24.
[0064] Please see attached Fig.25 , where P1 is port 1, P2 is port 2, and P3 is port 3. dB(S(2,1)) and dB(S(3,1)) are the two equally divided power output curves of the power divider, dB(S(3,2)) is the mutual isolation curve of the two equally divided power ports, and VSWR, VSWR(2), and VSWR are the standing wave ratio curves of the three ports P1, P2, and P3, respectively.
[0065] Please see attached Fig.26 , where the solid line divides the amplitude difference between port P2 and port P3 into two equal parts, and the dotted line divides the phase difference between port P2 and port P3 into two equal parts.
[0066] The utility model is based on LTCC (low temperature co-fired ceramic) technology and adopts the traditional Wilkinson power divider lumped parameter model design. The capacitor and inductor adopt an upper and lower structure, in which the capacitor is placed in the lower layer to form a grounding capacitor with GND and reduce the parasitic inductance introduced by the connecting line. The inductor is placed in the upper layer to reduce the parasitic effect between the inductor and the capacitor, and the middle is connected by a point column. The lumped capacitor uses a high dielectric constant ceramic material to achieve a small volume and large capacity. The lumped inductor adopts a three-dimensional spiral inductor. At the same time, the two inductors are wound in opposite directions to reduce the mutual inductance between the inductors and improve the inductor Q value, so as to achieve the high performance requirements of low insertion loss, high isolation, high amplitude balance, and high phase balance of a small multilayer ceramic chip power divider. The utility model effectively realizes the miniaturization of the power divider, and has the advantages of low loss, high isolation, high amplitude balance, high phase balance, high reliability, low cost and suitability for large-scale production. The miniaturized multilayer chip power divider manufactured by the utility model using LTCC technology has the advantages of high reliability, low insertion loss, high isolation, small size, light weight, easy integration, low cost, etc. It is suitable for large-scale production and therefore has a wide range of applications.
Claims
1. A new type of small-size multi-layer chip power divider, characterized by: The power divider comprises a ceramic substrate and an internal circuit structure layer arranged in the ceramic substrate, and the internal circuit structure layer is as follows from bottom to top: The first layer has four mutually insulated metal plane conductors printed on a ceramic dielectric substrate, namely a first metal plane conductor (P1), a second metal plane conductor (P2), a third metal plane conductor (P3) and a fourth metal plane conductor (P4); the first metal plane conductor (P1) is connected to a first point column (11), the second metal plane conductor (P2) is connected to a second point column (12), the third metal plane conductor (P3) is connected to a third point column (13), and the fourth metal plane conductor (P4) is connected to a fourth point column (14); The second layer has a metal plane conductor printed on a ceramic dielectric substrate, which is a fifth metal plane conductor (1). The fifth metal plane conductor (1) is connected to a fiftieth metal plane conductor (1a). The fifth metal plane conductor (1) and the fiftieth metal plane conductor (1a) are integrally arranged. The fiftieth metal plane conductor (1a) is connected to the fourth metal plane conductor (P4) in the first layer via a fourth point column (14). The third layer has three mutually independent metal plane conductors printed on a ceramic dielectric substrate, namely a sixth metal plane conductor (2-1), a seventh metal plane conductor (2-2) and an eighth metal plane conductor (2-3); the sixth metal plane conductor (2-1) is connected to a ninth metal plane conductor (2-1a); the sixth metal plane conductor (2-1) and the ninth metal plane conductor (2-1a) are integrally arranged; the ninth metal plane conductor (2-1a) is connected to the first metal plane conductor (P1) in the first layer via a first point column (11); the seventh metal plane conductor (2-2) is connected to a tenth metal plane conductor (2-3); The seventh metal plane conductor (2-2) and the tenth metal plane conductor (2-2a) are integrally arranged, the tenth metal plane conductor (2-2a) is connected to the second metal plane conductor (P2) in the first layer via a second point column (12), the eighth metal plane conductor (2-3) is connected to the eleventh metal plane conductor (2-3a), the eighth metal plane conductor (2-3) and the eleventh metal plane conductor (2-3a) are integrally arranged, and the eleventh metal plane conductor (2-3a) is connected to the third metal plane conductor (P3) in the first layer via a third point column (13); The fourth layer has a metal plane conductor printed on the ceramic dielectric substrate, which is the twelfth metal plane conductor (3). The twelfth metal plane conductor (3) is connected to the fifth metal plane conductor (1) in the second layer via a fourth point column (14); The fifth layer is a metal plane conductor printed on the ceramic dielectric substrate, which is a thirteenth metal plane conductor (4). The thirteenth metal plane conductor (4) includes a fourteenth metal plane conductor (4-1), a fifteenth metal plane conductor (4-2) and a sixteenth metal plane conductor (4-3). The fourteenth metal plane conductor (4-1), the fifteenth metal plane conductor (4-2) and the sixteenth metal plane conductor (4-3) intersect at the middle position of the thirteenth metal plane conductor (4). The fourteenth metal plane conductor (4-1) is connected to the seventeenth metal plane conductor (4-3). The first metal plane conductor (4-1a) is connected to the first metal plane conductor (4-2), the second metal plane conductor (4-3) is connected to the first metal plane conductor (4-1c), the first metal plane conductor (4-1a) is connected to the first metal plane conductor (2-1a) in the second layer through the first point column (11), the first metal plane conductor (4-1b) is connected to the fifth point column (15), and the first metal plane conductor (4-1c) is connected to the sixth point column (16); The sixth layer has two mutually insulated metal plane conductors printed on the ceramic dielectric substrate, which are a twentieth metal plane conductor (5-1) and a twenty-first metal plane conductor (5-2). The twentieth metal plane conductor (5-1) and the twenty-first metal plane conductor (5-2) are respectively in a "C" shape. One end of the twentieth metal plane conductor (5-1) is connected to the twenty-second metal plane conductor (5-1a), and the other end is connected to the twenty-third metal plane conductor (5-1b). The twenty-second metal plane conductor (5-1a) is connected to the twenty-third metal plane conductor (5-1b) through a fifth dot column (15). The eighteenth metal plane conductor (4-1b) in the fifth layer is connected, the twenty-third metal plane conductor (5-1b) is connected to the seventh point column (17), one end of the twenty-first metal plane conductor (5-2) is connected to the twenty-fourth metal plane conductor (5-2a), and the other end is connected to the twenty-fifth metal plane conductor (5-2b), the twenty-fourth metal plane conductor (5-2a) is connected to the nineteenth metal plane conductor (4-1c) in the fifth layer through the sixth point column (16), and the twenty-fifth metal plane conductor (5-2b) is connected to the eighth point column (18); The seventh layer has two mutually insulated metal plane conductors printed on the ceramic dielectric substrate, which are the twenty-sixth metal plane conductor (6-1) and the twenty-seventh metal plane conductor (6-2). The twenty-sixth metal plane conductor (6-1) and the twenty-seventh metal plane conductor (6-2) are respectively in a "C" shape. One end of the twenty-sixth metal plane conductor (6-1) is connected to the twenty-eighth metal plane conductor (6-1a), and the other end is connected to the twenty-ninth metal plane conductor (6-1b). The twenty-eighth metal plane conductor (6-1a) is connected to the seventh point column (17). The twenty-third metal plane conductor (5-1b) in the sixth layer is connected, the twenty-ninth metal plane conductor (6-1b) is connected to the ninth point column (19), one end of the twenty-seventh metal plane conductor (6-2) is connected to the thirtieth metal plane conductor (6-2a), and the other end is connected to the thirty-first metal plane conductor (6-2b), the thirtieth metal plane conductor (6-2a) is connected to the twenty-fifth metal plane conductor (5-2b) in the sixth layer through the eighth point column (18), and the thirty-first metal plane conductor (6-2b) is connected to the tenth point column (20); The eighth layer has two mutually insulated metal plane conductors printed on the ceramic dielectric substrate, which are the thirty-second metal plane conductor (7-1) and the thirty-third metal plane conductor (7-2). The thirty-second metal plane conductor (7-1) and the thirty-third metal plane conductor (7-2) are respectively in the shape of a letter "C". One end of the thirty-second metal plane conductor (7-1) is connected to the thirty-fourth metal plane conductor (7-1a), and the other end is connected to the thirty-fifth metal plane conductor (7-1b). The thirty-fourth metal plane conductor (7-1a) is connected to the seventh metal plane conductor (7-1b) through the ninth point column (19). The 39th metal plane conductor (6-1b) in the seventh layer is connected, the 35th metal plane conductor (7-1b) is connected to the 11th point column (21), one end of the 33rd metal plane conductor (7-2) is connected to the 36th metal plane conductor (7-2a), and the other end is connected to the 37th metal plane conductor (7-2b), the 36th metal plane conductor (7-2a) is connected to the 31st metal plane conductor (6-2b) in the seventh layer through the 10th point column (20), and the 37th metal plane conductor (7-2b) is connected to the 12th point column (22); The ninth layer has two mutually insulated metal plane conductors printed on a ceramic dielectric substrate, which are a thirty-eighth metal plane conductor (8-1) and a thirty-ninth metal plane conductor (8-2). The thirty-eighth metal plane conductor (8-1) and the thirty-ninth metal plane conductor (8-2) are respectively in a "C" shape. One end of the thirty-eighth metal plane conductor (8-1) is connected to the fortieth metal plane conductor (8-1a), and the other end is connected to the forty-first metal plane conductor (8-1b). The fortieth metal plane conductor (8-1a) is connected to the eighth layer through an eleventh point column (21). The thirty-fifth metal plane conductor (7-1b) is connected to the eighth layer, the forty-first metal plane conductor (8-1b) is connected to the thirteenth point column (23), one end of the thirty-ninth metal plane conductor (8-2) is connected to the forty-second metal plane conductor (8-2a), and the other end is connected to the forty-third metal plane conductor (8-2b), the forty-second metal plane conductor (8-2a) is connected to the thirty-seventh metal plane conductor (7-2b) in the eighth layer through the twelfth point column (22), and the forty-third metal plane conductor (8-2b) is connected to the fourteenth point column (24); The tenth layer has two mutually insulated metal plane conductors printed on a ceramic dielectric substrate, which are respectively a forty-fourth metal plane conductor (9-1) and a forty-fifth metal plane conductor (9-2). The forty-fourth metal plane conductor (9-1) and the forty-fifth metal plane conductor (9-2) are respectively in a "C" shape. One end of the forty-fourth metal plane conductor (9-1) is connected to a forty-sixth metal plane conductor (9-1a), and the other end is connected to a forty-seventh metal plane conductor (9-1b). The forty-sixth metal plane conductor (9-1a) is connected to the forty-first metal plane conductor (8-1b) in the ninth layer through a thirteenth point column (23). The forty-seventh metal plane conductor (9-1b) is connected to the tenth metal plane conductor (2-2a) in the third layer through the second point column (12), one end of the forty-fifth metal plane conductor (9-2) is connected to the forty-eighth metal plane conductor (9-2a), and the other end is connected to the forty-ninth metal plane conductor (9-2b), the forty-eighth metal plane conductor (9-2a) is connected to the forty-third metal plane conductor (8-2b) in the ninth layer through the fourteenth point column (24), and the forty-ninth metal plane conductor (9-2b) is connected to the eleventh metal plane conductor (2-3a) in the third layer through the third point column (13).
2. The novel small-size multi-layer chip power divider according to claim 1 is characterized in that: A Mark direction mark (10) is provided on the top of the ceramic substrate.
3. The novel small-size multi-layer chip power divider according to claim 1 is characterized in that: The first metal plane conductor (P1), the second metal plane conductor (P2), the third metal plane conductor (P3) and the fourth metal plane conductor (P4) are respectively arranged at four corners.
4. The novel small-size multi-layer chip power divider according to claim 1 is characterized in that: The fifth metal plane conductor (1) is arranged in the middle position.
5. The novel small-size multi-layer chip power divider according to claim 1 is characterized in that: The twelfth metal plane conductor (3) has the same shape as the fifth metal plane conductor (1) in the second layer, and is stacked up and down.