Power-on instant impact current suppression circuit

Abstract

A power-on instant impact current suppression circuit comprises a power supply input end Vin, a power supply output end Vout, a first switching circuit, a second switching circuit, a voltage division circuit, a control circuit, a constant current source circuit and a capacitor C2. A power supply input end Vin is respectively connected with first conduction ends of the first and second switching circuits and an input end of the voltage division circuit; the input end of the constant current source circuit is connected with the second conduction end of the second switch circuit, the output end of the constant current source circuit, the second conduction end of the first switch circuit and the power supply output end Vout are respectively connected with the first end of the capacitor C2, and the second end of the capacitor C2 is grounded; the first input end and the second input end of the control circuit are connected with the output end of the voltage division circuit and the power output end Vout, and the first output end and the second output end of the control circuit are connected with the controlled end of the first switching circuit and the controlled end of the second switching circuit respectively. The circuit can restrain the impact current at the power-on moment, and is low in power consumption and high in working efficiency.

Description

Technical Field

[0001] The utility model relates to a protection circuit technology, in particular to a power-on instantaneous surge current suppression circuit. Background Art

[0002] Due to the existence of capacitors in the circuit, at the moment of power-on, the capacitors are equivalent to a short circuit, so the capacitors will be charged first. At this time, the transient current (i.e., impact current) will be very large. On the one hand, it will affect the fuse at the input power supply end. The large current may cause the fuse to blow. On the other hand, the large impact current will also have a great impact on the components in the power supply circuit, and there is even the possibility of burning out the components.

[0003] Figure 1 The circuit schematic diagram of an existing power-on instantaneous surge current suppression circuit is shown. Capacitor C21 (capacitance value is 1000uF) is a load capacitor. If no measures are taken against the surge current, the surge current will be very large when charging the 1000uF capacitor. Figure 1 In the technical solution, PMOS tube Q21 and PMOS tube Q22 are used as the conduction path, the capacitance value of capacitor C21 is large, and the Vgs of PMOS tube Q21 and PMOS tube Q22 rises slowly. At this time, the voltage rise at the load end will also become slow. At the same time, the amplification area time of PMOS tube Q21 and PMOS tube Q22 is extended, and the impedance in the amplification area is large, which will limit the current, thereby achieving the effect of suppressing the impact current.

[0004] The above technical solution suppresses the surge current by controlling the Vgs voltage rise rate of the field effect tube, which will cause the field effect tube to consume a lot of power and generate a lot of heat, and even burn out the field effect tube. In addition, the instantaneous surge current suppression circuit will continue to work after power is turned on, which will cause the efficiency of the entire circuit to decrease and the standby power consumption to increase. Summary of the invention

[0005] The technical problem to be solved by the utility model is to provide a circuit capable of suppressing instantaneous surge current at power-on, which has low power consumption, small heat generation and high working efficiency.

[0006] The instantaneous surge current suppression circuit of the power-on embodiment of the utility model comprises a power input terminal Vin, a power output terminal Vout, a first switch circuit, a second switch circuit, a voltage divider circuit, a control circuit, a constant current source circuit and a capacitor C2; the power input terminal Vin is respectively connected to the first conduction terminal of the first switch circuit, the first conduction terminal of the second switch circuit and the input terminal of the voltage divider circuit; the input terminal of the constant current source circuit is connected to the second conduction terminal of the second switch circuit, the output terminal of the constant current source circuit, the second conduction terminal of the first switch circuit and the power output terminal Vout are respectively connected to the first terminal of the capacitor C2, and the second terminal of the capacitor C2 is grounded; the first input terminal of the control circuit is connected to the output terminal of the voltage divider circuit, the second input terminal of the control circuit is connected to the power output terminal Vout, the first output terminal of the control circuit is connected to the controlled terminal of the first switch circuit, and the second output terminal of the control circuit is connected to the controlled terminal of the second switch circuit, and the control circuit is used to control the first switch circuit to be turned off and the second switch circuit to be turned on when the voltage at the first input terminal is greater than the voltage at the second input terminal, and to control the first switch circuit to be turned on and the second switch circuit to be turned off when the voltage at the first input terminal is less than the voltage at the second input terminal.

[0007] The utility model has at least the following technical effects:

[0008] 1. The instantaneous surge current suppression circuit of the power-on embodiment of the utility model does not generate large power consumption when the overall circuit is working. Compared with the existing scheme, there is no situation where the power components generate large power consumption and cause serious heating or even burn the components, and the overall thermal performance is better;

[0009] 2. Compared with the existing solutions, the power-on instantaneous surge current suppression circuit of the embodiment of the utility model will not work continuously. When the circuit output voltage reaches a certain value (the voltage value can be adjusted according to actual needs), the power-on instantaneous surge current suppression circuit will be turned off, thereby improving the overall working efficiency of the circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 A circuit schematic diagram of an existing power-on instantaneous surge current suppression circuit is shown.

[0011] Figure 2 The circuit schematic diagram of the power-on instantaneous surge current suppression circuit according to the embodiment of the utility model is shown. DETAILED DESCRIPTION

[0012] The utility model is described in detail below with reference to the accompanying drawings and specific embodiments.

[0013] Please refer to Figure 2The power-on instantaneous surge current suppression circuit according to an embodiment of the utility model comprises a power input terminal Vin, a power output terminal Vout, a first switch circuit 1, a second switch circuit 2, a voltage divider circuit 3, a control circuit 4, a constant current source circuit 5 and a capacitor C2.

[0014] The power input terminal Vin is connected to the first conduction terminal of the first switch circuit 1 , the first conduction terminal of the second switch circuit 2 , and the input terminal of the voltage divider circuit 3 , respectively.

[0015] The input end of the constant current source circuit 5 is connected to the second conduction end of the second switch circuit 2, the output end of the constant current source circuit 5, the second conduction end of the first switch circuit 1 and the power supply output end Vout are respectively connected to the first end of the capacitor C2, and the second end of the capacitor C2 is grounded.

[0016] The first input terminal of the control circuit 4 is connected to the output terminal of the voltage divider circuit 3, the second input terminal of the control circuit 4 is connected to the power supply output terminal Vout, the first output terminal of the control circuit 4 is connected to the controlled terminal of the first switch circuit 1, and the second output terminal of the control circuit 4 is connected to the controlled terminal of the second switch circuit 2. The control circuit 4 is used to control the first switch circuit 1 to be turned off and the second switch circuit 2 to be turned on when the voltage at the first input terminal is greater than the voltage at the second input terminal, and to control the first switch circuit 1 to be turned on and the second switch circuit 2 to be turned off when the voltage at the first input terminal is less than the voltage at the second input terminal.

[0017] In this embodiment, the control circuit 4 includes a comparison circuit 40 , a first switch control circuit 41 and a second switch control circuit 42 .

[0018] The first input terminal and the second input terminal of the comparison circuit 40 constitute the first input terminal and the second input terminal of the control circuit 4 respectively, and the output terminal of the comparison circuit 40 is connected to the input terminal of the first switch control circuit 41 and the input terminal of the second switch control circuit 42 respectively; the comparison circuit 40 is used to generate a first control signal when the voltage of the first input terminal of the comparison circuit is greater than the voltage of the second input terminal of the comparison circuit, and to generate a second control signal when the voltage of the first input terminal of the comparison circuit is less than the voltage of the second input terminal of the comparison circuit.

[0019] exist Figure 2 In the specific implementation shown, the comparison circuit 40 is an operational amplifier comparison circuit, the inverting input terminal and the non-inverting input terminal of the operational amplifier comparison circuit respectively constitute the first input terminal and the second input terminal of the comparison circuit 4, the first control signal is a low level signal, and the second control signal is a high level signal. The operational amplifier comparison circuit includes an operational amplifier U1 and a resistor R7, the first end of the resistor R7 is connected to the output terminal of the operational amplifier U1, and the second end of the resistor R7 constitutes the output terminal of the comparison circuit 40. Vdd is a DC power supply, which needs to be selected according to the actual application. Figure 2The voltage at point A is the output voltage of the output terminal of the comparison circuit 40, which is also equal to the input voltage of the first switch control circuit 41. The voltage at point B is the input voltage of the inverting input terminal of the operational amplifier comparison circuit (i.e., the inverting input terminal of the operational amplifier U1), which is also the output voltage of the voltage divider circuit 3. The voltage at point C is the input voltage of the non-inverting input terminal of the operational amplifier comparison circuit (i.e., the non-inverting input terminal of the operational amplifier U1), which is also equal to the output voltage of the power supply output terminal Vout.

[0020] The output end of the first switch control circuit 41 is connected to the controlled end of the first switch circuit 1. The first switch control circuit 41 is used to control the first switch circuit 1 to be turned off when receiving a first control signal, and to control the first switch circuit 1 to be turned on when receiving a second control signal.

[0021] exist Figure 2 In the specific embodiment shown, the first switch circuit 1 includes a PNP transistor Q1 and a resistor R1, and the two ends of the resistor R1 are respectively connected to the emitter and base of the PNP transistor Q1; the base, emitter and collector of the PNP transistor Q1 respectively constitute the controlled end, the first conduction end and the second conduction end of the first switch circuit 1. The first switch control circuit 41 includes an NPN transistor Q3, a resistor R2 and a resistor R10, and the two ends of the resistor R2 are respectively connected to the controlled end of the first switch circuit 1 and the collector of the NPN transistor Q3, and the two ends of the resistor R10 are respectively connected to the base and emitter of the NPN transistor Q3, and the base of the NPN transistor Q3 is connected to the output end of the comparison circuit 40, and the emitter of the NPN transistor Q3 is grounded.

[0022] The output end of the second switch control circuit 42 is connected to the controlled end of the second switch circuit 2. The second switch control circuit 42 is used to control the second switch circuit to be turned on when receiving the first control signal, and to control the second switch circuit 2 to be turned off when receiving the second control signal.

[0023] exist Figure 2 In the specific embodiment shown, the second switch circuit 2 includes a PNP transistor Q2 and a resistor R4, and the two ends of the resistor R4 are respectively connected to the emitter and base of the PNP transistor Q2; the base, emitter and collector of the PNP transistor Q2 respectively constitute the controlled end, the first conduction end and the second conduction end of the second switch circuit. The second switch control circuit 42 includes an NPN transistor Q6, an NPN transistor Q7, a resistor R6, a resistor R8, a resistor R11 and a resistor R13.

[0024] The first end of the resistor R6 is connected to the power input terminal Vin and the first conduction terminal of the second switch circuit 2 respectively; the base of the NPN transistor Q7 is connected to the output terminal of the comparison circuit 40, the collector of the NPN transistor Q7 is connected to the second end of the resistor R6 and the base of the NPN transistor Q6 respectively, the emitter of the NPN transistor Q7 is grounded, and the two ends of the resistor R13 are connected to the base and emitter of the NPN transistor Q7 respectively. The two ends of the resistor R8 are connected to the controlled end of the second switch circuit 2 and the collector of the NPN transistor Q6 respectively, the emitter of the NPN transistor Q6 is grounded, and the two ends of the resistor R11 are connected to the base and emitter of the NPN transistor Q6 respectively. Figure 2 The voltage at point D is the voltage at the first end of the resistor R6, which is equal to the input voltage of the power input terminal Vin. The voltage at point E is the voltage at the second end of the resistor R6, which is also the collector voltage of the NPN transistor Q7 and the base voltage of the NPN transistor Q6. The voltage at point F is the base voltage of the NPN transistor Q7, which is equal to the voltage at point A. In other embodiments, the first end of the resistor R6 is not connected to the power input terminal Vin, but is connected to another power supply, the output voltage of which satisfies that when the NPN transistor Q7 is turned off, the voltage divided by the resistor R11 and the resistor R6 is greater than the turn-on voltage of the NPN transistor Q6.

[0025] In this embodiment, the voltage divider circuit 3 includes a resistor R3 and a resistor R9, and the resistor R3 is connected in series with the resistor R9; the first end of the resistor R3 constitutes the input end of the voltage divider circuit, the common point of the second end of the resistor R3 and the first end of the resistor R9 constitutes the output end of the voltage divider circuit, and the second end of the resistor R9 is grounded.

[0026] In this embodiment, the constant current source circuit 5 is a mirror image constant current source circuit. Figure 2 In the specific implementation shown, the mirror image constant current source circuit includes a PNP transistor Q4, a PNP transistor Q5, a resistor R5, a resistor R12, and a resistor R14. The common point of the first end of the resistor R5 and the first end of the resistor R14 constitutes the input end of the constant current source circuit, the second end of the resistor R5 is connected to the emitter of the PNP transistor Q4, the second end of the resistor R14 is connected to the emitter of the PNP transistor Q5, the collector of the PNP transistor Q5 constitutes the output end of the constant current source circuit, the PNP transistor Q4 and the PNP transistor Q5 have a common base, the base of the PNP transistor Q4 is short-circuited with the collector, the first end of the resistor R12 is connected to the collector of the PNP transistor Q4, and the second end of the resistor R12 is grounded. Figure 2 The voltage at point G is the common point voltage of the first end of the resistor R5 and the first end of the resistor R14, and is also the collector voltage of the PNP transistor Q2. The voltage at point H is the output voltage of the power output terminal Vout.

[0027] Furthermore, the power-on instantaneous surge current suppression circuit of this embodiment further includes a filter capacitor C1 , a first end of the filter capacitor C1 is connected to a common point of the power input terminal Vin and the first conducting end of the first switch circuit 1 .

[0028] The following combination Figure 2 The working principle of the power-on instantaneous surge current suppression circuit of this embodiment is described.

[0029] When the power input terminal Vin is powered on and starts to supply power, the voltage at point B is greater than the voltage at point C, and the comparison circuit 40 outputs a low level, so the voltage at point A is a low level, and the voltage at point A is less than the turn-on voltage value of the NPN transistor Q3, and the NPN transistor Q3 is turned off, thereby causing the PNP transistor Q1 to be turned off, and the input voltage at the power input terminal Vin cannot be transmitted to the power output terminal Vout through the PNP transistor Q1. At the same time, since the voltage at point F is a low level, the voltage at point F is less than the turn-on voltage value of the NPN transistor Q7, so the NPN transistor Q7 is also in a cut-off state. The voltage at point D is at a high level, and the selection of resistors R6 and R11 satisfies that when point D is at a high level, the voltage at point E is greater than the turn-on voltage value of NPN transistor Q6, so NPN transistor Q6 is in the on state, so that the emitter voltage of PNP transistor Q2 is higher than its base voltage, so PNP transistor Q2 is also in the on state, so point G is at a high level, that is, the input voltage of the transistor mirror constant current source circuit is at a high level, the constant current source circuit 5 works, the input voltage of the power input terminal Vin charges the capacitor C2 through the constant current source circuit 5, and the output voltage value of the power output terminal Vout gradually increases. The constant current source circuit 5 enables the power input terminal to charge the electrolytic capacitor C2 with a stable current, so that a large impact current will not be generated.

[0030] When the voltage at the power output terminal Vout rises to a certain voltage value (the voltage value can be set according to actual needs by the resistance ratio of the resistor R3 and the resistor R9), the voltage at point B is less than the voltage at point C (i.e., the voltage value at the power output terminal Vout), and the comparison circuit 40 outputs a high level, so the voltages at points A and F are high levels, and the voltage at point F is greater than the turn-on voltage value of the NPN transistor Q7, and the NPN transistor Q7 is turned on, and the voltage at point E is low level, and the voltage at point E is less than the turn-on voltage value of the NPN transistor Q6, so the NPN transistor Q6 is turned off, and the PNP transistor Q2 is also turned off. At this time, the power input terminal Vin cannot continue to charge the capacitor C2 through the constant current source circuit 5. At the same time, since the voltage at point A is at a high level, it is greater than the turn-on voltage value of the NPN transistor Q3, and the NPN transistor Q3 is turned on, making the emitter voltage of the PNP transistor Q1 greater than the base voltage, and the PNP transistor Q1 is turned on, so the power input terminal Vin can continue to supply power to the capacitor C2 through the PNP transistor Q1. Since the power input terminal Vin has just been powered on, the power input terminal has slowly charged the capacitor C2 through the transistor mirror current, so at this time there will be no large voltage difference between the power input terminal Vin and the capacitor C2, and no large inrush current will be generated. At this time, the circuit can work normally, and the inrush current suppression circuit does not work.

[0031] In some specific applications, the power input terminal Vin serves as the input power of the entire circuit, the power output terminal Vout serves as the input power of the DCDC / LDO chip, and the output voltage of the DCDC / LDO chip serves as the power supply voltage of the load.

[0032] The power-on instantaneous surge current suppression circuit of the embodiment of the utility model does not generate large power consumption when the overall circuit is working. Compared with the existing scheme, there is no situation where serious heating or even burning of components due to large power consumption of power components, and the working efficiency is also higher.

Claims

1. A power-on instantaneous surge current suppression circuit, characterized in that: It includes a power input terminal Vin, a power output terminal Vout, a first switch circuit, a second switch circuit, a voltage divider circuit, a control circuit, a constant current source circuit and a capacitor C2; The power input terminal Vin is respectively connected to the first conduction terminal of the first switch circuit, the first conduction terminal of the second switch circuit and the input terminal of the voltage divider circuit; The input end of the constant current source circuit is connected to the second conduction end of the second switch circuit, the output end of the constant current source circuit, the second conduction end of the first switch circuit and the power supply output end Vout are respectively connected to the first end of the capacitor C2, and the second end of the capacitor C2 is grounded; The first input end of the control circuit is connected to the output end of the voltage divider circuit, the second input end of the control circuit is connected to the power supply output end Vout, the first output end of the control circuit is connected to the controlled end of the first switch circuit, and the second output end of the control circuit is connected to the controlled end of the second switch circuit. The control circuit is used to control the first switch circuit to be turned off and the second switch circuit to be turned on when the voltage at the first input end is greater than the voltage at the second input end, and to control the first switch circuit to be turned on and the second switch circuit to be turned off when the voltage at the first input end is less than the voltage at the second input end.

2. The power-on instantaneous surge current suppression circuit according to claim 1, characterized in that: The control circuit includes a comparison circuit, a first switch control circuit and a second switch control circuit; The first input terminal and the second input terminal of the comparison circuit constitute the first input terminal and the second input terminal of the control circuit respectively, and the output terminal of the comparison circuit is connected to the input terminal of the first switch control circuit and the input terminal of the second switch control circuit respectively; the comparison circuit is used to generate a first control signal when the voltage of the first input terminal of the comparison circuit is greater than the voltage of the second input terminal of the comparison circuit, and generate a second control signal when the voltage of the first input terminal of the comparison circuit is less than the voltage of the second input terminal of the comparison circuit; The output end of the first switch control circuit is connected to the controlled end of the first switch circuit, and the first switch control circuit is used to control the first switch circuit to be turned off when receiving the first control signal, and to control the first switch circuit to be turned on when receiving the second control signal; The output end of the second switch control circuit is connected to the controlled end of the second switch circuit, and the second switch control circuit is used to control the second switch circuit to be turned on when receiving the first control signal, and to control the second switch circuit to be turned off when receiving the second control signal.

3. The power-on instantaneous surge current suppression circuit according to claim 2, characterized in that: The first switch circuit includes a PNP transistor Q1 and a resistor R1, wherein the two ends of the resistor R1 are respectively connected to the emitter and base of the PNP transistor Q1; the base, emitter and collector of the PNP transistor Q1 respectively constitute the controlled end, the first conduction end and the second conduction end of the first switch circuit.

4. The power-on instantaneous surge current suppression circuit according to claim 2, characterized in that: The first switch control circuit includes an NPN transistor Q3, a resistor R2 and a resistor R10, the two ends of the resistor R2 are respectively connected to the controlled end of the first switch circuit and the collector of the NPN transistor Q3, the two ends of the resistor R10 are respectively connected to the base and emitter of the NPN transistor Q3, the base of the NPN transistor Q3 is connected to the output end of the comparison circuit, and the emitter of the NPN transistor Q3 is grounded.

5. The power-on instantaneous surge current suppression circuit according to claim 2, characterized in that: The second switch circuit includes a PNP transistor Q2 and a resistor R4, wherein the two ends of the resistor R4 are respectively connected to the emitter and base of the PNP transistor Q2; the base, emitter and collector of the PNP transistor Q2 respectively constitute the controlled end, the first conduction end and the second conduction end of the second switch circuit.

6. The power-on instantaneous surge current suppression circuit according to claim 2, characterized in that: The second switch control circuit includes an NPN transistor Q6, an NPN transistor Q7, a resistor R6, a resistor R8, a resistor R11 and a resistor R13; The first end of the resistor R6 is respectively connected to the power input terminal Vin and the first conduction end of the second switch circuit; the base of the NPN transistor Q7 is connected to the output end of the comparison circuit, the collector of the NPN transistor Q7 is respectively connected to the second end of the resistor R6 and the base of the NPN transistor Q6, the emitter of the NPN transistor Q7 is grounded, and the two ends of the resistor R13 are respectively connected to the base and emitter of the NPN transistor Q7; Both ends of the resistor R8 are connected to the controlled end of the second switch circuit and the collector of the NPN transistor Q6 respectively. The emitter of the NPN transistor Q6 is grounded. Both ends of the resistor R11 are connected to the base and emitter of the NPN transistor Q6 respectively.

7. The power-on instantaneous surge current suppression circuit according to claim 2, characterized in that: The comparison circuit is an operational amplifier comparison circuit, the inverting input terminal and the non-inverting input terminal of the operational amplifier comparison circuit respectively constitute the first input terminal and the second input terminal of the comparison circuit, the first control signal is a low level signal, and the second control signal is a high level signal.

8. The power-on instantaneous surge current suppression circuit according to claim 1, characterized in that: The voltage divider circuit includes a resistor R3 and a resistor R9, and the resistor R3 is connected in series with the resistor R9; the first end of the resistor R3 constitutes the input end of the voltage divider circuit, the common point of the second end of the resistor R3 and the first end of the resistor R9 constitutes the output end of the voltage divider circuit, and the second end of the resistor R9 is grounded.

9. The power-on instantaneous surge current suppression circuit according to claim 1, characterized in that: The constant current source circuit is a mirror image constant current source circuit.

10. The power-on instantaneous surge current suppression circuit according to claim 9, characterized in that: The mirror image constant current source circuit includes a PNP transistor Q4, a PNP transistor Q5, a resistor R5, a resistor R12 and a resistor R14; The common connection point of the first end of the resistor R5 and the first end of the resistor R14 constitutes the input end of the constant current source circuit, the second end of the resistor R5 is connected to the emitter of the PNP transistor Q4, the second end of the resistor R14 is connected to the emitter of the PNP transistor Q5, the collector of the PNP transistor Q5 constitutes the output end of the constant current source circuit, the PNP transistor Q4 and the PNP transistor Q5 have a common base, the base and collector of the PNP transistor Q4 are short-circuited, the first end of the resistor R12 is connected to the collector of the PNP transistor Q4, and the second end of the resistor R12 is grounded.

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