Concentrator clock synchronization circuit
By designing a clock synchronization circuit in the concentrator, using the connection circuit between the management module and the metering module to realize the mutual exclusion operation of the clock state pins, the problem of clock synchronization delay of the management module and the metering module is solved, and the meter reading accuracy is improved. Accuracy of event logging.
Patent Information
- Application Number
- CN202323157571.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2023-11-22
- Publication Date
- 2025-02-14
- Estimated Expiration
- 2033-11-22
AI Technical Summary
In the prior art, the clock synchronization delay between the management module and the metering module is relatively large, which affects the accuracy of meter reading.
A concentrator clock synchronization circuit is designed, and the mutually exclusive set and reset of the clock state pin is realized through the first connection circuit between the management module and the metering module, and the clock information provided by the clock module is read and used as a Soft clock reference.
Reduces clock synchronization delays of management modules and metering modules, reduces clock synchronization delays of concentrators, reduces power data deviations, and improves the accuracy of event recording and occurrence clocks.
Smart Images
Figure CN222484840U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of concentrators, in particular to a concentrator clock synchronization circuit. Background Art
[0002] The concentrator is the central management device and control device of the remote centralized meter reading system. It generally has the functions of regularly reading meter data, system command transmission, data communication, network management, event recording, data transmission, etc. The concentrator can generally use the Linux system. The system startup generally takes about 1 minute. When more functions are added, the system startup will be more time-consuming. If the concentrator MCU (Microcontroller Unit) is used to complete metering-related work, the system startup time will be too long to meet the metering requirements. Then it is necessary to add a separate MCU with metering function, such as a metering module MCU. The MCU can start quickly and independently complete metering-related work to meet the metering requirements. Both the management module MCU and the metering module MCU of the concentrator need a reference clock as the reference of their software system clock. In order to ensure the accuracy of the clock and control the hardware cost at the same time, generally only one RTC clock chip is used as the reference clock. Here, it involves the clock synchronization problem of the management module clock, the metering module clock and the RTC (Real_Time Clock) clock chip. In the existing solution, due to the involvement of clock requests and time data requests, the clock synchronization delay of the management module and the metering module will be increased, thereby affecting meter reading. Utility Model Content
[0003] The utility model aims to provide a concentrator clock synchronization circuit to solve the technical problem of large clock synchronization delay between a management module and a metering module in the prior art.
[0004] The technical solution of the utility model is as follows: a concentrator clock synchronization circuit is provided, comprising a management module, a metering module, a clock module and a first connection circuit, wherein the clock module is connected to the management module and the metering module respectively, and the management module is also connected to the metering module through the first connection circuit;
[0005] The metering module is used to obtain the first level state of the operation clock state pin of the management module through the first connection circuit after the concentrator is powered on; when the first level state is in an unset state, set the operation clock state pin of the metering module, read the first clock information provided by the clock module, and use the first clock information as a first soft clock reference to reset the operation clock state pin of the metering module;
[0006] The management module is used to obtain the second level state of the operation clock state pin of the metering module through the first connection circuit after the concentrator is powered on; when the second level state is in an unset state, set the operation clock state pin of the management module, read the second clock information provided by the clock module, and use the second clock information as a second soft clock reference to reset the operation clock state pin of the management module.
[0007] Further, the management module is further used to obtain the third level state of the operation clock state pin of the metering module through the first connection circuit after receiving the first clock synchronization instruction containing the reference clock information; when the third level state is an unset state, the operation clock state pin of the management module is set, and the reference clock information is written into the clock module, the clock module is used to use the reference clock information as a clock reference, and the management module is also used to reset the operation clock state pin of the management module;
[0008] The management module is further configured to send a second clock synchronization instruction to the metering module after resetting the operation clock state pin of the management module;
[0009] The metering module is further configured to, after receiving the second clock synchronization instruction, obtain a fourth level state of the operation clock state pin of the management module through the first connection circuit; when the fourth level state is an unset state, set the operation clock state pin of the metering module; read third clock information provided by the clock module; and use the third clock information as a third soft clock reference to reset the operation clock state pin of the metering module.
[0010] Furthermore, the management module includes a management chip U1, the metering module includes a metering chip U2, the first connection circuit includes a resistor R405, a resistor R411 and a resistor R415, the first end of the resistor R405 is connected to the PA.10 pin of the metering chip U2, the first end of the resistor R405 is also connected to the first power supply through the resistor R411, and the second end of the resistor R405 is connected to the PG11 pin of the management chip U1; the first end of the resistor R415 is connected to the second power supply, and the second end of the resistor R415 is respectively connected to the PA.9 pin of the metering chip U2 and the PG12 pin of the management chip U1.
[0011] Furthermore, the concentrator clock synchronization circuit also includes a second connection circuit, and the metering module is connected to the clock module via the second connection circuit.
[0012] Further, the clock module includes a clock chip RTC, and the second connection circuit includes a resistor R402 and a resistor R403, the first end of the resistor R402 is connected to the SDA pin of the clock chip RTC, the second end of the resistor R402 is connected to the PD.10 pin of the metering chip U2, the first end of the resistor R403 is connected to the SCL pin of the clock chip RTC, and the second end of the resistor R403 is connected to the PD.11 pin of the metering chip U2.
[0013] Furthermore, the SDA pin of the clock chip RTC is connected to the PG3 pin of the management chip U1, and the SCL pin of the clock chip RTC is connected to the PG2 pin of the management chip U1.
[0014] Furthermore, the clock module also includes a capacitor C147 and a capacitor C8U, the first end of the capacitor C147 is connected to the VDD pin of the clock chip RTC, the second end of the capacitor C147 is connected to the FOE pin of the clock chip RTC, and the capacitor C8U is connected in parallel with the capacitor C147.
[0015] Furthermore, a first end of the capacitor C147 is also connected to a third power supply, and a second end of the capacitor C147 is grounded.
[0016] Furthermore, the clock module also includes resistor R59, resistor R61 and resistor R65. The SDA pin of the clock chip RTC is also connected to the first end of the resistor R59, the second end of the resistor R59 is connected to the first end of the resistor R61, the second end of the resistor R61 is connected to the SCL pin of the clock chip RTC, the first end of the resistor R65 is connected to the INTA pin of the clock chip RTC, and the second end of the resistor R65 is connected to the second end of the resistor R59.
[0017] Furthermore, the first end of the resistor R61 is also connected to a fourth power supply, and the GND pin of the clock chip RTC is grounded.
[0018] The beneficial effects of the utility model are as follows: the clock module is connected to the management module and the metering module respectively, and the management module is connected to the metering module through the first connection circuit; after the concentrator is powered on, the metering module obtains the first level state of the operation clock state pin of the management module through the first connection circuit; when the first level state is in an unset state, the operation clock state pin of the metering module is set, the first clock information provided by the clock module is read, and the first clock information is used as a first soft clock reference to reset the operation clock state pin of the metering module; after the concentrator is powered on, the management module obtains the second level state of the operation clock state pin of the metering module through the first connection circuit; when the second level state is in an unset state, the operation clock state pin of the management module is set, the second clock information provided by the clock module is read, and the second clock information is used as a second soft clock reference to reset the operation clock state pin of the management module; the clock synchronization delay of the management module and the metering module can be reduced, the clock synchronization delay of the concentrator can be reduced, the power data deviation can be reduced, and the accuracy of the event record occurrence clock can be improved. BRIEF DESCRIPTION OF THE DRAWINGS
[0019] Figure 1 A first structural schematic diagram of a concentrator clock synchronization circuit provided by the utility model;
[0020] Figure 2 A pin diagram of the management module provided by the utility model;
[0021] Figure 3 This is a pin diagram of the metering module provided by the utility model;
[0022] Figure 4 A circuit schematic diagram of a first connection circuit provided by the utility model;
[0023] Figure 5 A second structural schematic diagram of the concentrator clock synchronization circuit provided by the utility model;
[0024] Figure 6 A circuit schematic diagram of a clock module provided by the utility model;
[0025] Figure 7 This is a circuit schematic diagram of the second connection circuit provided by the utility model. DETAILED DESCRIPTION
[0026] The following will be combined with the drawings in the embodiments of the utility model to clearly and completely describe the technical solutions in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments of the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.
[0027] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present invention. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.
[0028] It should be noted that the terms "first", "second", etc. in the specification and claims of the present utility model and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the utility model described herein can be implemented in an order other than those illustrated or described herein.
[0029] Figure 1 1 is a schematic diagram of the first structure of the concentrator clock synchronization circuit of the embodiment of the utility model. It should be noted that if there is substantially the same result, the utility model is not based on Figure 1 The structure shown is limited. Figure 1 As shown, the concentrator clock synchronization circuit includes a management module 10, a metering module 20, a clock module 30 and a first connection circuit 40, wherein the clock module 30 is connected to the management module 10 and the metering module 20 respectively, and the management module 10 is also connected to the metering module 20 through the first connection circuit 40;
[0030] The metering module 20 is used to obtain the first level state of the operation clock state pin of the management module 10 through the first connection circuit 40 after the concentrator is powered on; when the first level state is in an unset state, set the operation clock state pin of the metering module 20, read the first clock information provided by the clock module 30, and use the first clock information as a first soft clock reference to reset the operation clock state pin of the metering module 20;
[0031] The management module 10 is used to obtain the second level state of the operation clock state pin of the metering module 20 through the first connection circuit 40 after the concentrator is powered on; when the second level state is in an unset state, set the operation clock state pin of the management module 10, read the second clock information provided by the clock module 30, and use the second clock information as a second soft clock reference to reset the operation clock state pin of the management module 10.
[0032] Among them, if the first level state is a set state, it means that the management module 10 is performing clock synchronization, and the first level state of the operation clock state pin of the management module 10 can be re-acquired after a first preset time is delayed; if the second level state is a set state, it means that the metering module 20 is performing clock synchronization, and the first level state of the operation clock state pin of the management module 10 can be re-acquired after a second preset time is delayed. The operation clock state pin of the management module 10 can be referred to as a first pin (pin), and the operation clock state pin of the metering module 20 can be referred to as a second pin.
[0033] In the embodiment of the utility model, the clock module 30 is connected to the management module 10 and the metering module 20 respectively, and the management module 10 is connected to the metering module 20 through the first connection circuit 40; after the concentrator is powered on, the metering module 20 obtains the first level state of the operation clock state pin of the management module 10 through the first connection circuit 40; when the first level state is an unset state, the operation clock state pin of the metering module 20 is set, the first clock information provided by the clock module 30 is read, and the first clock information is used as the first soft clock reference of the metering module 20, and the operation clock state pin of the metering module 20 is set. The management module 10, after the concentrator is powered on, obtains the second level state of the operation clock state pin of the metering module 20 through the first connection circuit 40; when the second level state is in an unset state, the operation clock state pin of the management module 10 is set, the second clock information provided by the clock module 30 is read, and the second clock information is used as the second soft clock reference of the management module 10 to reset the operation clock state pin of the management module 10; the clock synchronization delay of the management module 10 and the metering module 20 can be reduced, the clock synchronization delay of the concentrator can be reduced, the power data deviation can be reduced, and the accuracy of the event record occurrence clock can be improved.
[0034] In a specific embodiment, both the metering module 20 and the management module 10 can be integrated in the concentrator. After the concentrator is powered on, since the metering module 20 can be an STM32 module with a faster boot speed, and the management module 10 can be an ARM chip module with a slower boot speed, the metering module 20 can perform clock synchronization before the management module 10. The first level state of the operation clock state pin of the management module 10 can be obtained by querying the operation clock state pin GPIO (general purpose I / O port) of the management module 10, wherein the clock state pin can be a pin for operating (reading or writing) the clock state of the clock chip; the first level state of the operation clock state pin of the metering module 20 can be obtained by querying the operation clock state pin GPIO of the metering module 20.
[0035] In some embodiments, the management module 10 is further used to obtain the third level state of the operation clock state pin of the metering module 20 through the first connection circuit 40 after receiving the first clock synchronization instruction containing the reference clock information; when the third level state is an unset state, the operation clock state pin of the management module 10 is set, and the reference clock information is written into the clock module 30, the clock module 30 is used to use the reference clock information as a clock reference, and the management module 30 is also used to reset the operation clock state pin of the management module 10;
[0036] The management module 10 is further configured to send a second clock synchronization instruction to the metering module 20 after resetting the operation clock state pin of the management module 10;
[0037] The metering module 20 is further configured to, after receiving the second clock synchronization instruction, obtain a fourth level state of the operation clock state pin of the management module 10 through the first connection circuit 40, and when the fourth level state is an unset state, set the operation clock state pin of the metering module 20, read the third clock information provided by the clock module 30, and use the third clock information as a third soft clock reference to reset the operation clock state pin of the metering module 20.
[0038] In a specific implementation, the first clock synchronization instruction can be issued by a host device (host computer, host device provided by the power supply bureau), and the first clock synchronization instruction is issued by the host device to synchronize the clocks of the management module 10 and the metering module 20, so that the soft clock of the management module 10 and the soft clock of the metering module 20 are respectively consistent with the corresponding clocks in the reference clock information, and the operation clock status pin of the management module 10 can realize the reading and writing functions.
[0039] In the embodiment of the utility model, the management module 10 first receives a first clock synchronization instruction including reference clock information. After receiving the first clock synchronization instruction, the management module 10 synchronizes its own soft clock with the clock in the reference clock information, that is, the clock of the reference clock information is used as the fourth soft clock reference of the management module 10 to achieve clock synchronization of the management module 10. If the third level state is an unset state, the operation clock state pin of the management module 10 is set, and the reference clock information is written into the clock module 30. The clock module 30 uses the reference clock information as the clock reference.
[0040] After resetting the operation clock state pin of the management module 10, the management module 10 sends a second clock synchronization instruction to the metering module 20. After the metering module 20 receives the second clock synchronization instruction, if the fourth level state is in an unset state, the operation clock state pin of the metering module 20 is set, so that the metering module 20 reads the third clock information, and uses the third clock information as the third soft clock reference of the metering module 20 to achieve clock synchronization of the metering module 20; the operation clock state pin of the metering module 20 is reset so that the management module 10 can be clock synchronized next time; the clock synchronization delay of the management module 10 and the metering module 20 can be reduced, the clock synchronization delay of the concentrator can be reduced, the power data deviation can be reduced, and the accuracy of the event record occurrence clock can be improved.
[0041] In a specific embodiment, if the third level state is a set state, it means that the metering module 20 is performing clock synchronization, and after a delay of a third preset time (e.g., 0.1s), the third level state of the operation clock state pin of the metering module 20 is reacquired, wherein the third preset time is set to be relatively short, such as 1s or less, to reduce clock synchronization delay. If the fourth level state is a set state, it means that the management module 10 is performing clock synchronization, and after a delay of a fourth preset time (e.g., 0.01s), the fourth level state of the operation clock state pin of the management module 10 is reacquired.
[0042] The above-mentioned set state can be a state in which the level state is 1, and the unset state can be a state in which the level state is 0. The operation clock state pin of the management module 10 or the metering module 20 is set, and the level state of the corresponding operation clock state pin is set to 1, that is, the operation clock state pin of the management module 10 or the metering module 20 is turned on to read the corresponding clock information; the operation clock state pin of the management module 10 or the metering module 20 is reset, that is, the level state of the corresponding operation clock state pin is reset (reset) to 0, even if the operation clock state pin of the management module 10 or the metering module 20 is not turned on.
[0043] In some embodiments, the management module 10 includes a management chip U1, the metering module 20 includes a metering chip U2, the first connection circuit 40 includes a resistor R405, a resistor R411 and a resistor R415, the first end of the resistor R405 is connected to the PA.10 pin of the metering chip U2, the first end of the resistor R405 is also connected to the first power supply through the resistor R411, and the second end of the resistor R405 is connected to the PG11 pin of the management chip U1; the first end of the resistor R415 is connected to the second power supply, and the second end of the resistor R415 is respectively connected to the PA.9 pin of the metering chip U2 and the PG12 pin of the management chip U1.
[0044] In a specific embodiment, the pin diagram of the management module 10 is as follows: Figure 2 As shown, Figure 2 The model of the management chip U1 can be NUC972; the pin diagram of the metering module 20 is as follows: Figure 3 As shown, Figure 3 The model of the metering chip U2 can be HT6027; the circuit schematic diagram of the first connection circuit 40 is as follows: Figure 4 The metering chip U2 can obtain the first level state of the operation clock state pin of the management chip U1 through the first connection circuit 40, such as Figure 2 As shown, the operation clock state pin of the management chip U1 may be a PG11 or PG12 pin (pin), and the management chip U1 may obtain the second level state of the operation clock state pin of the metering chip U2 through the first connection circuit 40, such as Figure 3 As shown, the operation clock state pin of the metering chip U2 can be the PA.9 or PA.10 pin (pin).
[0045] In some embodiments, the concentrator clock synchronization circuit further includes a second connection circuit 50 , and the metering module 20 is connected to the clock module 30 via the second connection circuit 50 .
[0046] In a specific embodiment, a second structural diagram of the concentrator clock synchronization circuit is shown as follows: Figure 5 As shown, Figure 5 In the embodiment, the metering module 20 is connected to the clock module 30 via the second connecting circuit 50 .
[0047] In some embodiments, the clock module 30 includes a clock chip RTC, the second connection circuit 50 includes a resistor R402 and a resistor R403, the first end of the resistor R402 is connected to the SDA pin of the clock chip RTC, the second end of the resistor R402 is connected to the PD.10 pin of the metering chip U2, the first end of the resistor R403 is connected to the SCL pin of the clock chip RTC, and the second end of the resistor R403 is connected to the PD.11 pin of the metering chip U2.
[0048] In a specific embodiment, the circuit schematic diagram of the clock module 30 is as follows: Figure 5 As shown, Figure 5 The model of the clock chip RTC can be 8025; the circuit schematic diagram of the second connection circuit 50 is as follows: Figure 6 As shown; the metering module 20 can read the first clock information provided by the clock module 30 through the second connection circuit 50.
[0049] In some embodiments, the SDA pin of the clock chip RTC is connected to the PG3 pin of the management chip U1, and the SCL pin of the clock chip RTC is connected to the PG2 pin of the management chip U1.
[0050] In a specific embodiment, the management chip U1 can directly read the second clock information provided by the clock module 30 (to perform clock synchronization).
[0051] In some embodiments, the clock module 30 also includes capacitor C147 and capacitor C8U, the first end of the capacitor C147 is connected to the VDD pin of the clock chip RTC, the second end of the capacitor C147 is connected to the FOE pin of the clock chip RTC, and the capacitor C8U is connected in parallel with the capacitor C147.
[0052] In some embodiments, a first end of the capacitor C147 is also connected to a third power supply, and a second end of the capacitor C147 is grounded.
[0053] In a specific embodiment, the third power supply is used to power the clock chip RTC.
[0054] In some embodiments, the clock module 30 also includes resistor R59, resistor R61 and resistor R65, the SDA pin of the clock chip RTC is also connected to the first end of the resistor R59, the second end of the resistor R59 is connected to the first end of the resistor R61, the second end of the resistor R61 is connected to the SCL pin of the clock chip RTC, the first end of the resistor R65 is connected to the INTA pin of the clock chip RTC, and the second end of the resistor R65 is connected to the second end of the resistor R59.
[0055] In some embodiments, the first end of the resistor R61 is also connected to a fourth power supply, and the GND pin of the clock chip RTC is grounded.
[0056] It should be noted that the first power supply, the second power supply, the third power supply, and the fourth power supply may be the same power supply or different power supplies, and may all be voltage sources.
[0057] The concentrator clock synchronization circuit provided by the embodiment of the utility model can reduce the clock synchronization delay of the management module 10 and the metering module 20, reduce the clock synchronization delay of the concentrator, reduce the deviation of the power data, and improve the accuracy of the event record occurrence clock. The concentrator clock synchronization circuit provided by the embodiment of the utility model uses the mutual exclusion of the pin (operation clock state pin) state to avoid conflicts caused by the management module 10 and the metering module 20 when reading the hardware clock at the same time, thereby avoiding the problem of clock reading or writing failure, or abnormal clock reading or writing, and ensuring that the soft clock in the management module 10 and the soft clock in the metering module 20 are synchronized with the hard clock respectively.
[0058] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0059] The above is only an implementation method of the present invention. It should be pointed out that a person skilled in the art can make improvements without departing from the inventive concept of the present invention, but these improvements are all within the protection scope of the present invention.
Claims
1. A concentrator clock synchronization circuit, characterized in that: It includes a management module, a metering module, a clock module, a first connection circuit and a second connection circuit, wherein the clock module is connected to the management module and the metering module respectively, the management module is also connected to the metering module through the first connection circuit, and the metering module is connected to the clock module through the second connection circuit; The management module includes a management chip U1, the metering module includes a metering chip U2, the first connection circuit includes a resistor R405, a resistor R411 and a resistor R415, the first end of the resistor R405 is connected to the PA.10 pin of the metering chip U2, the first end of the resistor R405 is also connected to the first power supply through the resistor R411, and the second end of the resistor R405 is connected to the PG11 pin of the management chip U1; the first end of the resistor R415 is connected to the second power supply, and the second end of the resistor R415 is respectively connected to the PA.9 pin of the metering chip U2 and the PG12 pin of the management chip U1; The clock module includes a clock chip RTC, the second connection circuit includes a resistor R402 and a resistor R403, the first end of the resistor R402 is connected to the SDA pin of the clock chip RTC, the second end of the resistor R402 is connected to the PD.10 pin of the metering chip U2, the first end of the resistor R403 is connected to the SCL pin of the clock chip RTC, and the second end of the resistor R403 is connected to the PD.11 pin of the metering chip U2; The SDA pin of the clock chip RTC is connected to the PG3 pin of the management chip U1, and the SCL pin of the clock chip RTC is connected to the PG2 pin of the management chip U1; The metering chip U2 is used to obtain the first level state of the PG11 or PG12 pin of the management chip U1 through the first connection circuit after the concentrator is powered on; when the first level state is in an unset state, set the PA.9 or PA.10 pin of the metering chip U2, read the first clock information provided by the clock chip RTC, and use the first clock information as the first soft clock reference to reset the PA.9 or PA.10 pin of the metering chip U2; The management chip U1 is used to obtain the second level state of the PA.9 or PA.10 pin of the metering chip U2 through the first connection circuit after the concentrator is powered on; when the second level state is in an unset state, set the PG11 or PG12 pin of the management chip U1, read the second clock information provided by the clock chip RTC, and use the second clock information as the second soft clock reference to reset the PG11 or PG12 pin of the management chip U1.
2. The concentrator clock synchronization circuit according to claim 1, characterized in that: The clock module also includes a capacitor C147 and a capacitor C8U, a first end of the capacitor C147 is connected to the VDD pin of the clock chip RTC, a second end of the capacitor C147 is connected to the FOE pin of the clock chip RTC, and the capacitor C8U is connected in parallel with the capacitor C147.
3. The concentrator clock synchronization circuit according to claim 2, characterized in that: The first end of the capacitor C147 is also connected to the third power supply, and the second end of the capacitor C147 is grounded.
4. The concentrator clock synchronization circuit according to claim 2, characterized in that: The clock module also includes resistor R59, resistor R61 and resistor R65. The SDA pin of the clock chip RTC is also connected to the first end of the resistor R59, the second end of the resistor R59 is connected to the first end of the resistor R61, the second end of the resistor R61 is connected to the SCL pin of the clock chip RTC, the first end of the resistor R65 is connected to the INTA pin of the clock chip RTC, and the second end of the resistor R65 is connected to the second end of the resistor R59.
5. The concentrator clock synchronization circuit according to claim 4, characterized in that: The first end of the resistor R61 is also connected to a fourth power supply, and the GND pin of the clock chip RTC is grounded.