Semiconductor device
By designing the source field plate to bypass the gate and the source, the opposite area between the source field plate and the gate is reduced, the problem of increasing parasitic capacitance is solved, and the frequency response performance of semiconductor devices is improved.
Patent Information
- Application Number
- CN202323486213.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-20
- Publication Date
- 2025-02-14
- Estimated Expiration
- 2033-12-20
AI Technical Summary
The opposite area between the source field plate and the gate in existing high electron mobility transistors is large, resulting in an increase in parasitic capacitance and affecting the frequency response of the device.
By designing the source field plate to extend from the active region to the passive region and electrically connect to the source by the gate and the source, the opposite area between the gate and the source field plate is reduced, thereby reducing the parasitic capacitance.
This design effectively reduces parasitic capacitance and improves the frequency response performance and reliability of semiconductor devices.
Smart Images
Figure CN222485185U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of microelectronic devices, in particular to a semiconductor device. Background Art
[0002] With the further development of the microelectronics industry, the operating frequency of electronic products is getting higher and higher, and the bandwidth and operating frequency requirements of semiconductor chips are also getting higher and higher. Among them, the gallium nitride high electron mobility transistor (HEMT) is a high electron mobility device formed by the two-dimensional electron gas at the AlGaN or GaN heterojunction, which can be better applied to high frequency, high voltage and high power fields.
[0003] In order to improve the breakdown voltage of high electron mobility transistors and give full play to their advantages of high output power, researchers at home and abroad have proposed many methods, and the source field plate structure is the most effective and widely used one among them.
[0004] The source field plate is a conductive structure placed between the gate and the drain and connected to the source. The first function of this structure is to suppress the maximum electric field strength in the channel region and increase the breakdown voltage; the second is to suppress the trapping effect of defects in the device and improve device performance. However, the current design for the source field plate is to achieve an electrical connection between the source field plate and the source by crossing the gate with a connecting wire. This design requires the source field plate to be thick enough to ensure that the connecting wire of the source field plate will not be disconnected when climbing at the gate. However, this design will introduce additional gate-source capacitance, which will affect the frequency response of the device. Utility Model Content
[0005] The embodiment of the utility model provides a semiconductor device, which reduces the facing area between the source field plate and the gate, thereby reducing the parasitic capacitance and improving the frequency response of the semiconductor device.
[0006] The present invention provides a semiconductor device, comprising:
[0007] An active region and a passive region surrounding the active region;
[0008] A substrate disposed in the active region and the passive region and an epitaxial structure located on one side of the substrate;
[0009] A source electrode, a drain electrode and a gate electrode located between the source electrode and the drain electrode on a side of the epitaxial structure away from the substrate;
[0010] A source field plate is located on a side of the gate away from the substrate and is insulated from the gate; the source field plate extends from the active area to the passive area and extends until the source field plate bypasses the gate and is electrically connected to the source.
[0011] Optionally, the gate includes a first gate division located in the active area and a second gate division located in the passive area; the source field plate includes a first division located in the active area, a second division located in the passive area, and a third division located in the active area and overlapping with the source; along the extension direction of the gate, the second division extends to a side of the second gate division away from the active area, and the second division and the second gate division are spaced apart.
[0012] Optionally, the maximum width W1 of the third section is greater than the maximum width W2 of the second section.
[0013] Optionally, the widths of the second sections are set equally, or the widths of the second sections increase along a direction from the source field plate to the source.
[0014] Optionally, an interval D1 between the second subsection and the second subsection of the gate satisfies 0<D1≤200 μm.
[0015] Optionally, a distance D2 between the second sub-portion and the active area satisfies D1<D2≤300 μm.
[0016] Optionally, a source through hole is provided on the source electrode;
[0017] The orthographic projection of the third section on the substrate surface has no overlap with the orthographic projection of the source through hole on the substrate surface, or the overlapping area is smaller than 1 / 2 of the area of the orthographic projection of the third section on the substrate surface.
[0018] Optionally, at least two source field plates are included, and the at least two source field plates include a first source field plate and a second source field plate respectively located on both sides of the source and adjacent to each other;
[0019] The second subsection of the first source field plate and the second subsection of the second source field plate are connected into an integrated structure to form a source field plate interconnection structure; the first source field plate and the second source field plate share a third subsection; and the source field plate interconnection structure is connected to the third subsection.
[0020] Optionally, the first subsection of the first source field plate and the first subsection of the second source field plate are symmetrical about a first symmetry axis;
[0021] The source field plate interconnect structure is symmetrical about a second symmetry axis, and the second symmetry axis is the same as the first symmetry axis.
[0022] Optionally, the epitaxial structure includes:
[0023] A nucleation layer, located on one side of the substrate;
[0024] A buffer layer, located on a side of the nucleation layer away from the substrate;
[0025] A channel layer, located on a side of the buffer layer away from the substrate;
[0026] The barrier layer is located at a side of the channel layer away from the substrate, and the barrier layer and the channel layer form a heterojunction structure.
[0027] According to the technical solution of the embodiment of the utility model, the semiconductor device includes a source field plate extending from the active area to the passive area, and extending until it bypasses the gate and is electrically connected to the source, so as to reduce the facing area between the gate and the source field plate; the second section of the source field plate located in the passive area is spaced apart from the second section of the gate located in the passive area, that is, the source field plate and the gate are arranged not to overlap in the extension direction of the gate in the passive area, so as to further reduce the facing area between the gate and the source field plate, and improve the performance and reliability of the semiconductor device.
[0028] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present utility model, nor are they intended to limit the scope of the present utility model. Other features of the present utility model will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS
[0029] Figure 1 A schematic top view of a semiconductor device provided by an embodiment of the utility model;
[0030] Figure 2 for Figure 1 A schematic diagram of a cross-sectional structure of a semiconductor device along a cross-sectional line AA' is provided;
[0031] Figure 3 A schematic top view of another semiconductor device provided by an embodiment of the utility model;
[0032] Figure 4 A schematic top view of another semiconductor device provided in an embodiment of the utility model. DETAILED DESCRIPTION
[0033] In order to enable those skilled in the art to better understand the solution of the utility model, the technical solution in the embodiment of the utility model will be clearly and completely described below in conjunction with the drawings in the embodiment of the utility model. Obviously, the described embodiment is only a part of the embodiment of the utility model, not all of the embodiments. Based on the embodiment of the utility model, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the utility model.
[0034] HEMT is a wide bandgap semiconductor device with high concentration of two-dimensional electron gas (2DEG). It has the advantages of high output power density, high temperature resistance, strong stability and high breakdown voltage. It has great application potential in both radio frequency and power electronic devices. In order to achieve high performance at high frequency, the parasitic capacitance of the device needs to be minimized in the structural design of semiconductor devices.
[0035] The parasitic capacitance of semiconductor devices is mainly divided into gate-source capacitance, gate-drain capacitance and source-drain capacitance. Among them, gate-source capacitance has the greatest impact on device frequency. There are two main sources of gate-source capacitance of semiconductor devices, one is the parasitic capacitance of the gate metal and the channel, and the other is the capacitance between the gate metal and the source field plate.
[0036] When the semiconductor device is working, the source field plate and the source are both at zero potential. At this time, the source field plate can increase the area of the depletion region on the side of the gate close to the drain, increase the drain-source voltage that the depletion region can bear, and thus increase the breakdown voltage of the device; at the same time, the source field plate is used to modulate the distribution of the electric field lines in the depletion region of the barrier layer, reducing the gate leakage current. The technical solution of the embodiment of the utility model aims to reduce the parasitic capacitance between the gate and the source field plate by designing the source field plate, thereby improving the performance and reliability of the semiconductor device. The technical solution of the embodiment of the utility model is described in detail below.
[0037] Figure 1 A schematic top view of a semiconductor device provided by an embodiment of the utility model, Figure 2 for Figure 1 A schematic diagram of a cross-sectional structure of a semiconductor device along a cross-sectional line AA' is provided, as shown in FIG. Figure 1 and Figure 2 As shown, the semiconductor device includes an active area aa and a passive area bb surrounding the active area aa: the semiconductor device also includes a source 301, a drain 302 and a gate 303 located in the active area aa; a substrate 10 is arranged in both the active area aa and the passive area bb, and an epitaxial structure 20 is located on one side of the substrate 10; the source 301, the drain 302 and the gate 303 located between the source 301 and the drain 302 are arranged on the side of the epitaxial structure 20 away from the substrate 10; the source field plate 40 is located on the side of the gate 303 away from the substrate 10 and is insulated from the gate 303; the source field plate 40 extends from the active area aa to the passive area bb, and extends until it bypasses the gate 303 and is electrically connected to the source 301, so that not only the application flexibility of the source field plate connection can be improved, but also the area directly facing the source field plate and the gate can be reduced, thereby reducing the parasitic capacitance between the gate and the source field plate.
[0038] Further, such as Figure 1As shown, the gate 303 includes a first gate subdivision 3031 located in the active region aa and a second gate subdivision 3032 located in the passive region bb; the source field plate 40 includes a first subdivision 401 located in the active region aa and a second subdivision 402 located in the passive region bb; along the extension direction of the gate 303, the second subdivision 402 extends to the side of the second gate subdivision 3032 away from the active region aa, and the second subdivision 402 is spaced from the second gate subdivision 3032. In this way, the source field plate and the gate are arranged so that they do not overlap in the extension direction of the gate in the passive region and are spaced at a certain distance, which can further reduce the area facing the gate and the source field plate, and improve the performance and reliability of the semiconductor device.
[0039] It can be understood that the semiconductor device includes but is not limited to the substrate 10, the epitaxial structure 20, the electrode structure 30, the dielectric layer 50, the field plate 40, etc. along the thickness direction, and no specific limitation is made here, as long as the top view structure meets the requirements of the present invention.
[0040] Exemplarily, the substrate 10 may be aluminum gallium nitride, gallium nitride, aluminum gallium arsenic, gallium arsenic, silicon carbide or silicon, etc. The embodiment of the utility model does not specifically limit the type of the material of the substrate 10. The epitaxial structure 20 located on one side of the substrate 10 may be formed of one or more of III-V group nitrides such as gallium nitride, aluminum gallium nitride, indium gallium nitride, aluminum nitride or indium aluminum gallium nitride.
[0041] Exemplarily, the epitaxial structure 20 may include a nucleation layer, a buffer layer, a channel layer, and a barrier layer stacked on one side of the substrate 10, wherein a heterojunction structure may be formed between the channel layer and the barrier layer. It is understood that the epitaxial structure 20 may also include a cap layer, which is located on the surface of the barrier layer away from the substrate 10. The cap layer may reduce the surface state, reduce the surface leakage of subsequent semiconductor devices, and suppress current collapse, thereby improving the performance and reliability of the epitaxial structure 20 and the semiconductor device.
[0042] Further, the electrode structure 30 located on the side of the epitaxial structure 20 away from the substrate may include a source 301, a drain 302, and a gate 303 located between the source 301 and the drain 302. Both the source 301 and the drain 3021 may form an ohmic contact with the epitaxial structure 20. Exemplarily, the source 301 may be used as the input terminal of the semiconductor device, the drain 302 may be used as the output terminal of the semiconductor device, the gate 303 may be used as the control terminal of the semiconductor device, and the current flow between the source 301 and the drain 302 may be achieved by controlling the voltage of the gate 303. That is, when a certain voltage is applied to the gate 303, a current will be generated between the source 301 and the drain 302, and the current between the source 301 and the drain 302 can be controlled by changing the voltage of the gate 303.
[0043] Specifically, the source field plate 40 is located on the side of the gate 303 away from the substrate 10 and is insulated from the gate 303, that is, the source field plate 40 is not in direct contact with the gate 303, but the gate 303 and the source field plate 40 are insulated by setting a dielectric layer 50 on the upper surface and the side of the gate 303. It can be understood that in the direction from the source 301 to the drain 302, the source field plate 40 can overlap or not overlap with the gate 303, and the source field plate 40 and the gate 303 can be set in the passive region bb along the extension direction of the gate without overlapping and at a certain distance, so as to reduce the area facing the gate and the source field plate, and reduce the gate-source parasitic capacitance.
[0044] Specifically, the active region aa can be understood as a region where two-dimensional electron gas, electrons or holes exist below it, and its working state and characteristics are affected by the external circuit, and it is the active working region of the semiconductor device. The passive region bb participates in the work of the semiconductor device, but its working state is not affected by the external circuit. For example, the lead-out structure of the electrode in the active region aa can be set in the passive region bb, and the passive region bb can be set around the active region aa.
[0045] Understandable, such as Figure 3 As shown, the semiconductor device may further include a gate pad 304, which is connected to the gate 303 in the active area aa, and provides a gate voltage signal to the gate 303 to ensure the normal operation of the semiconductor device. Exemplarily, the material of the source 301, the drain 302, the gate 303 and the source field plate 40 may be gold, silver, copper, iron, aluminum, indium, platinum, titanium, nickel or other metals or alloys formed by any combination thereof.
[0046] As a feasible implementation method, Figure 3 2 is a top view of another semiconductor device, wherein the interval between the second subdivision 402 of the source field plate 40 and the second subdivision 3032 of the gate is D1, wherein D1 satisfies 0<D1≤200μm. Setting the interval between the second subdivision 402 and the second subdivision 3032 of the gate is conducive to reducing the facing area while optimizing the device area and improving performance.
[0047] For example, the interval D1 between the second subdivision 402 of the source field plate 40 and the second subdivision 3032 of the gate may be D1 =50 μm, D1 =100 μm, D1 =150 μm or D1 =180 μm.
[0048] Optionally, the distance between the second subdivision 402 of the source field plate 40 and the active area aa is D2, and D2 satisfies D1<D2≤300μm. In the layout design of the semiconductor device, the second subdivision 402 of the source field plate 40 and the second subdivision 3032 of the gate need to maintain a certain distance, and it is not possible to set it arbitrarily. The distance between the second subdivision 402 of the source field plate 40 and the active area aa will affect the area and performance of the entire semiconductor device. Setting D2 to satisfy D1<D2≤300μm is conducive to reducing the area of the entire semiconductor device and improving the performance of the integrated circuit.
[0049] Exemplarily, the distance D2 between the second sub-portion 402 of the source field plate 40 and the active area aa may be D2 =50 μm, D2 =100 μm, D2 =150 μm or D3 =200 μm.
[0050] Optionally, the source field plate 40 further includes a third section 403 located in the active area aa and overlapping with the source 301. The three sections of the source field plate 40 are sequentially connected as the first section 401, the second section 402, and the third section 403. The maximum width of the third section 403 is W1, and the maximum width of the second section 402 is W2, and the two satisfy W1>W2, which can further improve the connection stability between the source field plate and the source while minimizing the area facing the gate and the source field plate, thereby improving the reliability of the device.
[0051] Optionally, the width of the second division 402 of the source field plate 40 is set to be equal, or the width of the second division 402 of the source field plate 40 is increased in the direction along the source field plate 40 pointing to the source 301. The width of the second division 402 of the source field plate 40 is equal in the extension direction of the source field plate 40 from the active area aa to the passive area bb, which is beneficial to improve the stability of the source field plate 40 in the passive area and avoid affecting the device performance. Alternatively, the width of the second division 402 is increased in the direction along the source field plate 40 pointing to the source 301, which can improve the stability of the electrical connection between the source field plate and the source and improve the reliability.
[0052] As a feasible implementation method, refer to Figure 3 The source field plate 40 further includes a third subdivision 403, which is located in the active area aa and overlaps with the source 301. Optionally, a source through hole 11 is provided corresponding to the source 301, and the source 301 can be connected to the back side of the semiconductor device through the source through hole 11. Exemplarily, the source through hole can penetrate the substrate 10 and the epitaxial structure 20.
[0053] Optionally, the orthographic projection of the third section 403 on the surface of the substrate 10 has no overlap with the orthographic projection of the source through hole 11 on the surface of the substrate 10 , or the overlapping area is less than 1 / 2 of the area of the orthographic projection of the third section 403 on the surface of the substrate 10 .
[0054] It should also be noted that the semiconductor device can be a single cell structure, for example, only including a source 301, a drain 302, a gate 303 and a source field plate 40. The semiconductor device can also be a multiple cell structure, that is, including at least two gates 303 and two source field plates 40. The structure of the source field plate 40 can be applied to both a single cell structure and a multi-cell structure.
[0055] As a feasible implementation method, Figure 4 : is a top view schematic diagram of another semiconductor device. The semiconductor device includes at least two source field plates 40, and the at least two source field plates 40 include a first source field plate 41 and a second source field plate 42 respectively located on both sides of the source 301 and adjacently arranged. The first source field plate 41 and the second source field plate 42 both include a first subdivision 411 (421), a second subdivision 412 (422), and a third subdivision 413 (423); the first subdivision 411 (421) is located in the active area aa, the second subdivision 412 (422) is located in the passive area bb, and the third subdivision 413 (423) is located in the active area aa and overlaps with the source 301. The second division 412 of the first source field plate 41 and the second division 422 of the second source field plate 42 are connected into an integrated structure to form a source field plate interconnection structure 44; the third division 413 of the first source field plate 41 and the third division 423 of the second source field plate 42 completely overlap, or in other words, the first source field plate 41 and the second source field plate 42 share a third division 413; and the source field plate interconnection structure 44 is connected to the third division 413.
[0056] Optionally, the first subsection 411 of the first source field plate 41 and the first subsection 421 of the second source field plate 42 are symmetrical about the first symmetry axis; the source field plate interconnection structure 44 is symmetrical about the second symmetry axis, and the second symmetry axis and the first symmetry axis are the same symmetry axis. The symmetrical arrangement of the source field plate interconnection structure 44 is beneficial to improving the radio frequency characteristics of the semiconductor device.
[0057] The semiconductor device of the present invention may further include a gate pad 304, the gate pad 304 is connected to the gate 303 in the active area aa, and the second subdivision 402 and the third subdivision 403 of the source field plate 40 are located on the other side opposite to the gate pad 304. It can be understood that in the semiconductor device having the source field plate interconnection structure 44, the source field plate interconnection structure 44 is located on the other side opposite to the gate pad 304.
[0058] Understandable, continue to refer to Figure 2, epitaxial structure 20: a nucleation layer 201, located on one side of the substrate 10; a buffer layer 202, located on the side of the nucleation layer 201 away from the substrate 10; a channel layer 203, located on the side of the buffer layer 202 away from the substrate 10; a barrier layer 204, located on the side of the channel layer 203 away from the substrate 10, the barrier layer 204 and the channel layer 203 form a heterojunction structure, and a two-dimensional electron gas is formed at the interface.
[0059] For example, continue to refer to Figure 2 The material of the nucleation layer 201 can be aluminum nitride, which is located between the substrate 10 and the buffer layer 202. The nucleation layer 201 affects the crystal quality, surface morphology, electrical properties and other parameters of the heterojunction material above. The nucleation layer 201 varies with different substrate materials, and mainly plays the role of matching the substrate material and the semiconductor material layer in the heterojunction structure.
[0060] For example, continue to refer to Figure 2 , the buffer layer 202 is located on one side of the substrate 10. The material of the buffer layer 202 may be gallium nitride, and the buffer layer 202 may include iron atoms, which is conducive to achieving the high resistance of the buffer layer 202, ensuring that vertical leakage can be blocked and the pinch-off performance of the semiconductor device can be improved. The buffer layer 202 can play the role of bonding the semiconductor material layer to be grown next, and can protect the substrate 10 from being invaded by some metal ions. The material of the buffer layer 202 can be a group III nitride material such as AlGaN, GaN or AlGaInN.
[0061] For example, continue to refer to Figure 2 The channel layer 203 may be a group III nitride, such as Al x Ga 1－x N, where 0≤x<1, that is, at the interface between the channel layer 203 and the barrier layer 204, that is, the energy of the conduction band edge of the channel layer 203 is less than the energy of the conduction band edge of the barrier layer 204. Exemplarily, x=0 indicates that the channel layer 203 is GaN. The channel layer 203 may also be other III-group nitrides, such as InGaN and AlInGaN. The channel layer 203 may be undoped or unintentionally doped. The channel layer 203 may also be a multilayer structure, such as a combination of a superlattice, GaN or AlGaN.
[0062] For example, continue to refer to Figure 2 The barrier layer 204 may be AlN, AlInN, AlGaN or AlInGaN. The barrier layer 204 has a sufficient thickness and a sufficiently high Al composition to form a significant carrier concentration at the interface between the channel layer 203 and the barrier layer 204.
[0063] For example, continue to refer to Figure 2, the channel layer 203 may include GaN, and the barrier layer 204 may include AlGaN, that is, the material of the barrier layer 204 has a higher band gap than the material of the channel layer 203, and the channel layer 203 may also have a greater electron affinity than the barrier layer 204. Due to the band gap difference between the barrier layer 204 and the channel layer 203 and the piezoelectric effect at the interface between the barrier layer 204 and the channel layer 203, a two-dimensional electron gas is formed between the channel layer 203 and the barrier layer 204.
[0064] It is understandable that the epitaxial structure 20 may further include a cap layer, which is located on the surface of the barrier layer 204 away from the substrate 10. The cap layer can reduce the surface state, reduce the surface leakage of the subsequent semiconductor device, and inhibit current collapse, thereby improving the performance and reliability of the epitaxial structure 20 and the semiconductor device.
[0065] It should be understood that from the perspective of semiconductor device layout design, the embodiment of the utility model can reduce the capacitance between the source field plate and the gate and improve the frequency response of the semiconductor device by setting a connection structure between the source field plate and the source to bypass the gate from the passive area. The semiconductor devices include but are not limited to: high-power high electron mobility transistors (HEMT) operating in high voltage and high current environments, transistors with silicon-on-insulator (SOI) structures, transistors based on gallium arsenide (GaAs), and metal-oxide-semiconductor field-effect transistors (MOSFET), metal-insulator semiconductor field-effect transistors (MISFET), double heterojunction field-effect transistors (DHFET), junction field-effect transistors (JFET), metal-semiconductor field-effect transistors (MESFET), and metal-semiconductor heterojunction field-effect transistors (MESFET). Transistor, referred to as MISHFET) or other field effect transistors. The source field plate provided in the semiconductor device provided by the embodiment of the utility model can be widely used in the semiconductor device manufacturing fields such as radio frequency microwave and power electronics. In particular, the advantages of gallium nitride electronic devices with large bandgap width, high electron mobility, high breakdown field strength and good thermal conductivity are more obvious, and can better meet the high performance requirements of the rapidly developing electronic communication and other fields.
[0066] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention is described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims
1. A semiconductor device, characterized in that: include: An active region and a passive region surrounding the active region; A substrate disposed in the active region and the passive region and an epitaxial structure located on one side of the substrate; A source electrode, a drain electrode and a gate electrode located between the source electrode and the drain electrode on a side of the epitaxial structure away from the substrate; A source field plate is located on a side of the gate away from the substrate and is insulated from the gate; the source field plate extends from the active area to the passive area and extends until it bypasses the gate and is electrically connected to the source.
2. The semiconductor device according to claim 1, wherein: The gate includes a first gate division located in the active area and a second gate division located in the passive area; the source field plate includes a first division located in the active area, a second division located in the passive area, and a third division located in the active area and overlapping with the source; along the extension direction of the gate, the second division extends to a side of the second gate division away from the active area, and the second division and the second gate division are spaced apart.
3. The semiconductor device according to claim 2, characterized in that The maximum width W1 of the third section is greater than the maximum width W2 of the second section.
4. The semiconductor device according to claim 2, characterized in that The widths of the second sections are set to be equal, or the widths of the second sections increase along a direction from the source field plate to the source.
5. The semiconductor device according to claim 2, wherein: The interval D1 between the second sub-portion and the second sub-portion of the gate satisfies 0<D1≤200 μm.
6. The semiconductor device according to claim 2, wherein: A distance D2 between the second sub-portion and the active region satisfies D1<D2≤300 μm.
7. The semiconductor device according to claim 2, characterized in that A source through hole is provided on the source electrode; The orthographic projection of the third section on the substrate surface has no overlap with the orthographic projection of the source through hole on the substrate surface, or the overlapping area is smaller than 1 / 2 of the area of the orthographic projection of the third section on the substrate surface.
8. The semiconductor device according to claim 1, wherein: The semiconductor device comprises at least two source field plates, wherein the at least two source field plates comprise a first source field plate and a second source field plate respectively located on both sides of the source and arranged adjacent to each other; the source field plate comprises a first sub-portion located in the active region, a second sub-portion located in the passive region, and a third sub-portion located in the active region and arranged overlapping with the source; The second subsection of the first source field plate and the second subsection of the second source field plate are connected into an integrated structure to form a source field plate interconnection structure; the first source field plate and the second source field plate share a third subsection; The source field plate interconnect structure is connected to the third subsection.
9. The semiconductor device according to claim 8, characterized in that The first subsection of the first source field plate and the first subsection of the second source field plate are symmetrical about a first symmetry axis; The source field plate interconnect structure is symmetrical about a second symmetry axis, and the second symmetry axis is the same as the first symmetry axis.
10. The semiconductor device according to claim 1, wherein: The epitaxial structure comprises: A nucleation layer, located on one side of the substrate; A buffer layer, located on a side of the nucleation layer away from the substrate; A channel layer, located on a side of the buffer layer away from the substrate; The barrier layer is located at a side of the channel layer away from the substrate, and the barrier layer and the channel layer form a heterojunction structure.