Display panel and display device
By setting specific contact holes on the interlayer insulating layer and buffer layer of the thin film transistor display panel, and synchronous etching through a photocopy mask, the problem of high lithography capacity loss in the prior art is solved, and the capacity improvement is achieved and Guarantee of device performance.
Patent Information
- Application Number
- CN202420390038.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-02-29
- Publication Date
- 2025-02-14
- Estimated Expiration
- 2034-02-28
AI Technical Summary
When producing TG thin film transistor display panels, the existing BCE type thin film transistor display panels need to switch 8 photomonitors to 10 photomonitors, resulting in high loss of photomonitor production capacity and significant decline in production capacity.
The first contact hole, the second contact hole and the third contact hole are provided on the interlayer insulating layer, and the fourth contact hole is provided on the buffer layer. The contact holes are synchronously etched through a photocoat to reduce the number of photocoats, thereby Reduce the production capacity loss rate.
Reduce the 10-channel photomasks of TG thin film transistors to 9-channel photomasks to reduce the capacity loss rate of the BCE production line, improve production capacity and yield, and avoid overetching of the active layer to ensure device performance.
Smart Images
Figure CN222485190U_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of display devices, and in particular to a display panel and a display device. Background Art
[0002] The existing TG (Top Gate) type thin film transistor display panel adopts a 10-mask solution; the BCE (Back Channel Etch) type thin film transistor display panel adopts an 8-mask solution; when the existing BCE type thin film transistor display panel production line is used to produce the TG type thin film transistor display panel, it is necessary to switch the 8-mask process to a 10-mask process, which results in a high loss of lithography capacity and a significant drop in capacity. Utility Model Content
[0003] The embodiments of the present application provide a display panel and a display device, which can simultaneously etch contact holes on an interlayer insulating layer, reduce photomasks, and improve production capacity.
[0004] The embodiment of the present application provides a display panel, a substrate;
[0005] A metal light-shielding layer, wherein the metal light-shielding layer is disposed on the base substrate;
[0006] A buffer layer, the buffer layer is disposed on the base substrate and covers the metal light shielding layer;
[0007] An active layer, disposed on the buffer layer;
[0008] A gate insulating layer, disposed on the active layer;
[0009] A gate, disposed on the gate insulating layer;
[0010] an interlayer insulating layer, the interlayer insulating layer being disposed on the buffer layer and covering the active layer and the gate;
[0011] A source electrode, disposed on the interlayer insulating layer;
[0012] A drain electrode, disposed on the interlayer insulating layer;
[0013] Wherein, the interlayer insulating layer is provided with a first contact hole, a second contact hole and a third contact hole;
[0014] A fourth contact hole is provided on the buffer layer, and the fourth contact hole corresponds to the third contact hole and is connected to each other;
[0015] The source electrode corresponds to the first contact hole and is connected to the active layer via the first contact hole;
[0016] A portion of the drain electrode corresponds to the position of the second contact hole and is connected to the active layer via the second contact hole, and another portion of the drain electrode corresponds to the position of the third contact hole and is connected to the metal light shielding layer via the third contact hole and the fourth contact hole;
[0017] The apertures of the first contact hole and the second contact hole are larger than the aperture of the third contact hole, and the apertures of the first contact hole and the second contact hole are larger than the aperture of the fourth contact hole.
[0018] In one embodiment, the area of the first contact hole is set to S1, and the area of the second contact hole is set to S2, wherein 20 μm 2 ≤S1=S2≤100μm 2 .
[0019] In one embodiment, the area of the third contact hole is set to S3, wherein 3 μm 2 ≤S3≤10μm 2 .
[0020] In one embodiment, the number of the third contact holes is set to N, where 1≤N≤4.
[0021] In one embodiment, the first contact hole, the second contact hole and the third contact hole are spaced apart in the first direction;
[0022] A first auxiliary hole and a second auxiliary hole are further provided on the interlayer insulating layer, the first auxiliary hole and the second auxiliary hole are at least located on one side of the first contact hole in the second direction, the first auxiliary hole and the second auxiliary hole are arranged at intervals in the first direction, and correspond to the positions of the first contact hole and the second contact hole respectively, and the projections of the first auxiliary hole and the second auxiliary hole on the base substrate are staggered with the projection of the metal light shielding layer on the base substrate;
[0023] The first direction and the second direction are arranged to cross each other.
[0024] In one embodiment, in the first direction, the distance between the third contact hole and the auxiliary hole closest thereto is set to be 10 μm-100 μm.
[0025] In one embodiment, the second auxiliary hole is located on a side of the first auxiliary hole close to the third contact hole;
[0026] In the second direction, the interval between the second auxiliary hole and the first contact hole is set to be 2 μm to 5 μm.
[0027] In one embodiment, two first auxiliary holes are provided, and the two first auxiliary holes are located on both sides of the first contact hole in the second direction;
[0028] Two second auxiliary holes are provided, and the two second auxiliary holes are located at two sides of the first contact hole in the second direction.
[0029] In one embodiment, the metal light shielding layer forms a first orthographic projection on the base substrate;
[0030] The active layer forms a second orthographic projection on the base substrate;
[0031] The gate is formed with a third orthographic projection on the base substrate;
[0032] The source electrode is formed with a fourth orthographic projection on the base substrate;
[0033] The drain electrode is formed with a fifth orthographic projection on the base substrate;
[0034] The auxiliary hole group forms a sixth orthographic projection on the base substrate;
[0035] The sixth orthographic projection is staggered with the first orthographic projection, the second orthographic projection, the third orthographic projection, the fourth orthographic projection and the fifth orthographic projection.
[0036] An embodiment of the present application further provides a display device, which includes the above-mentioned display panel.
[0037] Beneficial effect: In the display panel provided by the present application, a first contact hole is arranged at a position corresponding to the source electrode on the interlayer insulating layer, a second contact hole and a third contact hole are arranged at a position corresponding to the drain electrode, and a fourth contact hole is arranged on the buffer layer; it can be known that under the same etching conditions, the larger the aperture, the lower the etching rate and the smaller the hole depth, and the smaller the aperture, the higher the etching rate and the larger the hole depth; since the apertures of the first contact hole and the second contact hole are larger than the aperture of the third contact hole, in the synchronous etching process, the first contact hole and the second contact hole are formed on the interlayer insulating layer, and the third contact hole is formed on the interlayer insulating layer, and the fourth contact hole is formed on the buffer layer at the same time. The fourth contact hole is formed; in this way, the first contact hole, the second contact hole, the third contact hole and the fourth contact hole are formed by one photomask, and the number of photomasks from 10 to 9 for the TG type thin film transistor is reduced, thereby reducing the capacity loss rate of the BCE production line, and further improving the production capacity and yield; at the same time, the aperture of the first contact hole and the second contact hole is set to be larger than the aperture of the third contact hole, not only does not need to adjust the original etching selectivity of the interlayer insulating layer and the buffer layer, but also can meet the hole depth requirements of the contact holes within the same etching time, avoid over-etching on the active layer, thereby ensuring the device performance of the TG type thin film transistor. BRIEF DESCRIPTION OF THE DRAWINGS
[0038] The technical solution and other beneficial effects of the present application will be made apparent by describing in detail the specific implementation methods of the present application in conjunction with the accompanying drawings.
[0039] Figure 1 A first structural plan view of a display panel provided in an embodiment of the present application;
[0040] Figure 2 A second structural plan view of a display panel provided in an embodiment of the present application;
[0041] Figure 3 A third structural plan view of a display panel provided in an embodiment of the present application;
[0042] Figure 4 for Figure 2 The cross-sectional view along AA in FIG.
[0043] Figure 5 for Figure 4 Schematic diagram of adding source and drain in ;
[0044] Figure 6 A flowchart of manufacturing a display panel provided in an embodiment of the present application;
[0045] Figure 7a for Figure 6 Schematic diagram of the photoresist layer in FIG.
[0046] Figure 7b for Figure 6 Schematic diagram of making contact holes and auxiliary holes;
[0047] Figure 7c for Figure 6 Schematic diagram of removing the photoresist layer;
[0048] Figure 7d for Figure 6 Schematic diagram of adding source and drain in . DETAILED DESCRIPTION
[0049] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.
[0050] In the description of the present application, it should be understood that the terms "upper", "lower", "front", "back", "left", "right", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and cannot be understood as limiting the present application. In addition, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature merely means that the first feature is higher in level than the second feature or that the first feature is lower in level than the second feature, and does not indicate a direct connection relationship.
[0051] In addition, the terms "first" and "second" are used for descriptive purposes only, and the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.
[0052] The disclosure below provides many different embodiments to realize the different structures of the present application. In order to simplify the disclosure of the present application, the parts and settings of specific examples are described below. Of course, they are only examples, and the purpose is not to limit the present application. In addition, the various specific processes and material examples provided by the present application, but those of ordinary skill in the art can appreciate the application of other processes and / or the use of other materials.
[0053] The embodiments of the present application provide a display panel and a display device. The display panel can be a display panel of a display device such as a mobile phone, a computer, a tablet, and a display screen, and no specific limitation is made here.
[0054] See also Figures 1 to 5The embodiment of the present application provides a display panel 100, the display panel 100 includes a base substrate 1, a metal light shielding layer 2, a buffer layer 3, an active layer 4a, a gate insulating layer 4b, a gate 4c, an interlayer insulating layer 5, a source 4d and a drain 4e; the metal light shielding layer 2 is arranged on the base substrate 1; the buffer layer 3 is arranged on the base substrate 1 and covers the metal light shielding layer 2; the active layer 4a is arranged on the buffer layer 3; the gate insulating layer 4b is arranged on the active layer 4a; the gate 4c is arranged on the gate insulating layer 4b, the interlayer insulating layer 5 is arranged on the buffer layer 3, and covers the gate 4c and the active layer 4a; the source 4d is arranged on the interlayer insulating layer 5, and the drain 4e is arranged on the interlayer insulating layer 5; wherein the interlayer insulating layer 5 is provided with a first contact electrode at intervals. contact hole 51, a second contact hole 52 and a third contact hole 53, a fourth contact hole 31 is arranged on the buffer layer 3, the fourth contact hole 31 corresponds to the third contact hole 53 and is interconnected; the source electrode 4d corresponds to the first contact hole 51 and is connected to the active layer 4a via the first contact hole 51; a part of the drain electrode 4e corresponds to the second contact hole 52 and is connected to the active layer 4a via the second contact hole 52, another part of the drain electrode 4e corresponds to the third contact hole 53 and is connected to the metal shading layer 2 via the third contact hole 53 and the fourth contact hole 31; the apertures of the first contact hole 51 and the second contact hole 52 are larger than the aperture of the third contact hole 53, and the apertures of the first contact hole 51 and the second contact hole 52 are larger than the aperture of the fourth contact hole 31.
[0055] In the display panel 100 provided in the present application, a first contact hole 51 is set at the position corresponding to the source electrode 4d on the interlayer insulating layer 5, a second contact hole 52 and a third contact hole 53 are set at the position corresponding to the drain electrode 4e, and a fourth contact hole 31 is set on the buffer layer 3; it can be known that under the same etching conditions, the larger the aperture, the lower the etching rate and the smaller the hole depth, and the smaller the aperture, the higher the etching rate and the larger the hole depth; since the apertures of the first contact hole 51 and the second contact hole 52 are larger than the aperture of the third contact hole 53, in the synchronous etching process, the first contact hole 51 and the second contact hole 52 are formed on the interlayer insulating layer 5, and the third contact hole 53 is formed on the interlayer insulating layer 5, and the third contact hole 53 is formed on the buffer layer 3 at the same time. 3, the fourth contact hole 31 is formed on the interlayer insulating layer 5 and the buffer layer 3; in this way, the first contact hole 51, the second contact hole 52, the third contact hole 53 and the fourth contact hole 31 are formed by one photomask, and the number of 10 photomasks of the TG type thin film transistor is reduced to 9 photomasks, thereby reducing the capacity loss rate of the BCE production line, and further improving the production capacity and yield; at the same time, the aperture of the first contact hole 51 and the second contact hole 52 is larger than the aperture of the third contact hole 53, not only does not need to adjust the etching selectivity of the original interlayer insulating layer 5 and the buffer layer 3, but also can meet the hole depth requirements of the contact holes within the same etching time, avoid over-etching on the active layer 4a, thereby ensuring the device performance of the TG type thin film transistor.
[0056] The present application does not impose any specific limitation on the shapes of the first contact hole 51 , the second contact hole 52 , and the third contact hole 53 , which may be circular, square, or polygonal, and the shapes of the first contact hole 51 , the second contact hole 52 , and the third contact hole 53 may be the same or different.
[0057] The present application does not impose any specific restrictions on the area of the first contact hole 51 and the area of the second contact hole 52. The area of the first contact hole 51 and the area of the second contact hole 52 may be the same or different. In one embodiment, the area of the first contact hole 51 is set to S1, and the area of the second contact hole 52 is set to S2, wherein 20 μm 2 ≤S1=S2≤100μm 2 .
[0058] Furthermore, the present application does not impose any specific restrictions on the area of the third contact hole 53. In the actual manufacturing process, it can be determined according to the thickness of the buffer layer 3 and the interlayer insulating layer 5. In one embodiment, the area of the third contact hole 53 is set to S3, where 3 μm 2 ≤S3≤10μm 2 .
[0059] It can be understood that, in the actual manufacturing process, the thickness of the interlayer insulating layer 5 is generally thicker than that of the buffer layer 3, that is, when performing synchronous etching, the depth of the first contact hole 51 and the depth of the second contact hole 52 are the thickness of the interlayer insulating layer 5, and the third contact hole 53 and the fourth contact hole 31 are to be etched simultaneously at the position of the third contact hole 53, and the sum of the depths of the third contact hole 53 and the fourth contact hole 31 is to be greater than twice the depth of the first contact hole 51. In order to ensure that the active layer 4a is not over-etched during the synchronous etching process, it is necessary to set the area of the first contact hole 51 to be greater than twice the area of the third contact hole 53; in this way, the etching rates of the first contact hole 51 and the second contact hole 52 can be relatively reduced, and the etching rate of the third contact hole 53 can be increased, so that within the same etching time, the hole depth requirements of each contact hole can be met, and over-etching of the active layer 4a can be avoided, thereby ensuring the device performance of the TG thin film transistor.
[0060] It should be noted that the number of the third contact holes 53 and the number of the fourth contact holes 31 are the same, and one third contact hole 53 corresponds to one fourth contact hole 31 .
[0061] The present application does not limit the specific number of the third contact holes 53. In one embodiment, the number of the third contact holes is set to N, where 1≤N≤4. If space permits, more third contact holes 53 can be set, but due to space limitations, the number of the third contact holes 53 is less than or equal to 4. In other words, the number of the third contact holes 53 can be set to 1, 2, 3, or 4.
[0062] See also Figure 1 In the first embodiment, the interlayer insulating layer 5 is provided with a first contact hole 51, a second contact hole 52 and a third contact hole 53 at intervals, and the buffer layer 3 is provided with a fourth contact hole 31, and the fourth contact hole 31 corresponds to the third contact hole 53 and is interconnected; the third contact holes 53 and the fourth contact holes 31 are the same in number and correspond in position, and there are four third contact holes 53. Due to space limitations, four third contact holes 53 are provided, so that the area of each of the third contact holes 53 is reduced, thereby further improving the etching rates of the third contact holes 53 and the fourth contact holes 31.
[0063] See also Figure 2In the second embodiment, a first contact hole 51, a second contact hole 52 and a third contact hole 53 are arranged on the interlayer insulating layer 5 at intervals, and a fourth contact hole 31 is arranged on the buffer layer 3, and the fourth contact hole 31 corresponds to the third contact hole 53 and is interconnected; the third contact holes 53 and the fourth contact holes 31 are the same in number and correspond in position; different from the first embodiment, two third contact holes 53 are arranged, so that the position, area and shape of the third contact hole 53 are not limited by space, so that the solution of the present application can adapt to different types of the first contact holes 51 and the second contact holes 52.
[0064] It can be known that in the actual process, the buffer layer 3 needs to be configured with different etching rate ratios under conditions of different thicknesses and different materials. For example, when the material of the buffer layer 3 is SiOX or SiNX, the etching rate is different; when the thickness of the interlayer insulating layer 5 is constant, when the thickness of the buffer layer 3 changes, the corresponding etching rate also needs to be changed. In order to simplify the process and ensure that the etching of the first contact hole 51, the second contact hole 52 and the third contact hole 53 meets the design requirements, please refer to Figure 3 and Figure 4 , the size of the first contact hole 51 can be changed to match different etching rate ratios. For example, when the area of the first contact hole 51 is A, the etching rate ratio can be matched. The interlayer insulating layer 5 and When the area of the first contact hole 51 is adjusted to B, it can match The interlayer insulating layer 5 and The buffer layer 3.
[0065] See also Figure 3In the third embodiment, the first contact hole 51, the second contact hole 52 and the third contact hole 53 are arranged at intervals in the first direction F1; at least one auxiliary hole group 6 is further arranged on the interlayer insulating layer 5, the auxiliary hole group 6 is located on one side of the first contact hole 51 in the second direction F2, and the auxiliary hole group 6 includes two auxiliary holes 61 arranged at intervals in the first direction F1, the two auxiliary holes 61 correspond to the positions of the first contact hole 51 and the second contact hole 52 respectively, and the projections of the two auxiliary holes 61 on the base substrate 1 are staggered with the projections of the metal light shielding layer 2 on the base substrate 1; by arranging the two auxiliary holes 61 at positions adjacent to the first contact hole 51 and the second contact hole 52, the etching rates of the first contact hole 51 and the second contact hole 52 can be further reduced, so as to achieve the etching balance of the first contact hole 51, the second contact hole 52 and the third contact hole 53, and then meet the hole depth requirements of each contact hole within the same etching time, avoid over-etching of the active layer 4a, and thus ensure the device performance of the TG type thin film transistor; at the same time, in Mini In the LED (sub-millimeter light emitting diode) display panel, since the LED chip particles are small and embedded, there is a large surplus space for wiring arrangement inside the Mini LED display panel, so that the setting of the two auxiliary holes 61 will not affect the performance of the display panel.
[0066] It should be noted that the present application does not impose any specific limitation on the first direction F1 and the second direction F2, as long as the first direction F1 and the second direction F2 are arranged to cross each other.
[0067] The present application does not impose any specific limitation on the location of the auxiliary hole 61 .
[0068] In the first direction F1, the spacing between the third contact hole 53 and the nearest auxiliary hole 61 is set to 10μm to 100μm; it can be understood that the auxiliary hole 61 is set to further reduce the etching rate of the first contact hole 51, but in order to ensure that the auxiliary hole 61 does not affect the process of the third contact hole 53, the spacing between the auxiliary hole 61 and the third contact hole 53 is set to be greater than 10μm; however, due to the internal wiring arrangement of the display panel, the spacing between the auxiliary hole 61 and the third contact hole 53 needs to be less than 100μm.
[0069] The present application does not impose any specific limitation on the distance between the auxiliary hole 61 and the third contact hole 53. The distance between the auxiliary hole 61 and the third contact hole 53 may be 10 μm, 20 μm, 30 μm, or 100 μm.
[0070] In the second direction F2, the distance between one of the auxiliary holes 61 and the first contact hole 51 is set to H1; the distance between the other auxiliary hole 61 and the second contact hole 52 is set to H2; wherein, 2μm≤H1=H2≤5μm; in order to achieve the purpose of reducing the etching rate of the first contact hole 51 and the second contact hole 52 by setting the auxiliary hole 61, it is necessary to set the spacing between the auxiliary hole 61 and the first contact hole 51 to be less than 5μm; at the same time, due to the limitations of equipment process, in order to avoid the collapse of the first contact hole 51 or the second contact hole 52 due to too short photoresist length, the spacing between the auxiliary hole 61 and the first contact hole 51 and the second contact hole 52 can be set to be more than 2μm.
[0071] The present application does not impose any specific limitation on the spacing between the auxiliary hole 61 and the first contact hole 51 and the second contact hole 52 , and the spacing may be 2 μm, 3 μm, 4 μm, or 5 μm.
[0072] The present application does not impose any specific limitation on the number of auxiliary holes 61. Figure 3 In the third embodiment, two auxiliary hole groups 6 are provided, and the two auxiliary hole groups 6 are respectively located on both sides of the first contact hole 51 in the second direction F2; that is, four auxiliary holes 61 are provided, and the first contact hole 51 and the second contact hole 52 correspond to two auxiliary holes 61 respectively; in this way, the etching rates of the first contact hole 51 and the second contact hole 52 can be appropriately adjusted by adjusting the number of the auxiliary holes 61 around the first contact hole 51 and the second contact hole 52.
[0073] Furthermore, in order to avoid the influence of the setting of the auxiliary hole 61 on the performance of the display panel; in one embodiment, the metal shading layer 2 forms a first orthographic projection on the base substrate 1; the active layer 4a forms a second orthographic projection on the base substrate 1; the gate 4c forms a third orthographic projection on the base substrate 1; the source 4d forms a fourth orthographic projection on the base substrate 1; the drain 4e forms a fifth orthographic projection on the base substrate 1; the auxiliary hole group 6 forms a sixth orthographic projection on the base substrate 1; wherein the sixth orthographic projection is staggered with the first orthographic projection, the second orthographic projection, the third orthographic projection, the fourth orthographic projection and the fifth orthographic projection; in this way, the setting of the auxiliary hole 61 will not affect the performance of the display panel.
[0074] See also Figure 6 Based on the structure of the display panel 100 described above, an embodiment of the present application provides a method for manufacturing the display panel 100 .
[0075] The manufacturing method of the display panel 100 includes:
[0076] S10: providing a substrate 1;
[0077] S20: forming a metal light shielding layer 2 on the base substrate 1;
[0078] S30: depositing a buffer layer 3 on the base substrate 1, wherein the buffer layer 3 covers the metal light shielding layer 2;
[0079] S40: forming an active layer 4a on the buffer layer 3;
[0080] S50: forming a gate insulating layer 4b on the active layer 4a;
[0081] S60: forming a gate 4c on the gate insulating layer 4b;
[0082] S70: etching the gate insulating layer 4b using the gate 4c as a mask;
[0083] S80: forming an interlayer insulating layer 5 on the buffer layer 3, wherein the interlayer insulating layer 5 covers the active layer 4a and the gate 4c;
[0084] See also Figure 7a S90: coating a photoresist layer 7 on the interlayer insulating layer 5, and performing exposure and development treatment on the photoresist layer 7 to form a first etching hole 71, a second etching hole 72, a third etching hole 73, a fourth etching hole (not shown in the figure), and a fifth etching hole (not shown in the figure) arranged at intervals in the first direction F1, wherein the first etching hole 71, the second etching hole 72, and the third etching hole 73 are arranged at intervals in the first direction F1, and the fourth etching hole and the fifth etching hole are at least located on one side of the first etching hole 71 in the second direction F2, and the fourth etching hole corresponds to the first etching hole 71 in position, and the fifth etching hole corresponds to the second etching hole 72 in position;
[0085] See also Figure 7b S100: etching to form a first contact hole 51 at a position corresponding to the first etching hole 71 on the interlayer insulating layer 5, and simultaneously etching to form a second contact hole 52 at a position corresponding to the second etching hole 72 on the interlayer insulating layer 5, and simultaneously etching to form a third contact hole 53 and a fourth contact hole 31 at a position corresponding to the third etching hole 73 on the interlayer insulating layer 5 and the buffer layer 3, and simultaneously etching to form two auxiliary holes 61 at positions corresponding to the fourth etching hole and the fifth etching hole on the interlayer insulating layer 5;
[0086] See also Figure 7c , S110: removing the photoresist layer 7;
[0087] See also Figure 7d , S120: A source electrode 4d and a drain electrode 4e are arranged on the interlayer insulating layer 5, the source electrode 4d corresponds to the position of the first contact hole 51, and is connected to the active layer 4a via the first contact hole 51, a part of the drain electrode 4e corresponds to the position of the second contact hole 52, and is connected to the active layer 4a via the second contact hole 52, another part of the drain electrode 4e corresponds to the position of the third contact hole 53, and is connected to the metal shading layer 2 via the third contact hole 53 and the fourth contact hole 31.
[0088] In this embodiment, a first contact hole 51 is set at the position corresponding to the source 4d on the interlayer insulating layer 5, a second contact hole 52 and a third contact hole 53 are set at the position corresponding to the drain 4e, and a fourth contact hole 31 is set on the buffer layer 3; it can be known that under the same etching conditions, the larger the aperture, the lower the etching rate and the smaller the hole depth, and the smaller the aperture, the higher the etching rate and the larger the hole depth; since the apertures of the first contact hole 51 and the second contact hole 52 are larger than the aperture of the third contact hole 53, in the synchronous etching process, the first contact hole 51 and the second contact hole 52 are formed on the interlayer insulating layer 5, and the third contact hole 53 is formed on the interlayer insulating layer 5, and the buffer layer 3 is formed at the same time. The fourth contact hole 31; in this way, the first contact hole 51, the second contact hole 52, the third contact hole 53 and the fourth contact hole 31 are formed by one photomask, and the 10 photomasks of the TG type thin film transistor are reduced to 9 photomasks, thereby reducing the capacity loss rate of the BCE production line, and then improving the production capacity and yield; at the same time, the aperture of the first contact hole 51 and the second contact hole 52 is larger than the aperture of the third contact hole 53, not only does not need to adjust the original etching selectivity of the interlayer insulating layer 5 and the buffer layer 3, but also can meet the hole depth requirements of each contact hole within the same etching time, avoid over-etching on the active layer 4a, thereby ensuring the device performance of the TG type thin film transistor.
[0089] In this embodiment, by setting two auxiliary holes 61 at positions adjacent to the first contact hole 51 and the second contact hole 52, the etching rates of the first contact hole 51 and the second contact hole 52 can be further reduced, thereby achieving an etching balance among the first contact hole 51, the second contact hole 52 and the third contact hole 53, and then within the same etching time, meeting the hole depth requirements of each contact hole, avoiding over-etching of the active layer 4a, thereby ensuring the device performance of the TG type thin film transistor.
[0090] An embodiment of the present application also provides a display device, which includes a display panel 100; it should be noted that the display panel 100 is configured as the above-mentioned display panel 100, that is, the display panel 100 has all the embodiments of the above-mentioned display panel 100, and the display device also has all the technical features of all the embodiments of the above-mentioned display panel 100, and also has all the beneficial effects brought by all the technical features, which will not be repeated here one by one.
[0091] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.
[0092] The above is a detailed introduction to a display panel and a display device provided in the embodiments of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.
Claims
1. A display panel, characterized in that: include: substrate substrate; A metal light-shielding layer, wherein the metal light-shielding layer is disposed on the base substrate; A buffer layer, the buffer layer is disposed on the base substrate and covers the metal light shielding layer; An active layer, disposed on the buffer layer; A gate insulating layer, disposed on the active layer; A gate, disposed on the gate insulating layer; an interlayer insulating layer, the interlayer insulating layer being disposed on the buffer layer and covering the active layer and the gate; A source electrode, disposed on the interlayer insulating layer; A drain electrode, disposed on the interlayer insulating layer; Wherein, the interlayer insulating layer is provided with a first contact hole, a second contact hole and a third contact hole; A fourth contact hole is provided on the buffer layer, and the fourth contact hole corresponds to the third contact hole and is connected to each other; The source electrode corresponds to the first contact hole and is connected to the active layer via the first contact hole; A portion of the drain electrode corresponds to the position of the second contact hole and is connected to the active layer via the second contact hole, and another portion of the drain electrode corresponds to the position of the third contact hole and is connected to the metal light shielding layer via the third contact hole and the fourth contact hole; The apertures of the first contact hole and the second contact hole are larger than the aperture of the third contact hole, and the apertures of the first contact hole and the second contact hole are larger than the aperture of the fourth contact hole.
2. The display panel according to claim 1, wherein: The area of the first contact hole is set to S1, and the area of the second contact hole is set to S2, wherein 20 μm 2 ≤S1=S2≤100μm 2 .
3. The display panel according to claim 1, wherein: The area of the third contact hole is set to S3, where 3 μm 2 ≤S3≤10μm 2 .
4. The display panel according to claim 1, wherein: The number of the third contact holes is set to N, where 1≤N≤4.
5. The display panel according to claim 1, wherein: The first contact hole, the second contact hole and the third contact hole are arranged at intervals in the first direction; At least one auxiliary hole group is also provided on the interlayer insulating layer, the auxiliary hole group is located on one side of the first contact hole in the second direction, the auxiliary hole group includes two auxiliary holes arranged at intervals in the first direction, the two auxiliary holes correspond to the positions of the first contact hole and the second contact hole respectively, and the projections of the two auxiliary holes on the base substrate are staggered with the projection of the metal light shielding layer on the base substrate; The first direction and the second direction are arranged to cross each other.
6. The display panel according to claim 5, wherein: In the first direction, the distance between the third contact hole and the auxiliary hole closest thereto is set to be 10 μm to 100 μm.
7. The display panel according to claim 5, wherein: In the second direction, the distance between one of the auxiliary holes and the first contact hole is set to H1; The distance between the other auxiliary hole and the second contact hole is set to H2; Among them, 2μm≤H1=H2≤5μm.
8. The display panel according to claim 5, wherein: There are two auxiliary hole groups, and the two auxiliary hole groups are respectively located at two sides of the first contact hole in the second direction.
9. The display panel according to claim 5, wherein: The metal light shielding layer forms a first orthographic projection on the base substrate; The active layer forms a second orthographic projection on the base substrate; The gate is formed with a third orthographic projection on the base substrate; The source electrode is formed with a fourth orthographic projection on the base substrate; The drain electrode is formed with a fifth orthographic projection on the base substrate; The auxiliary hole group forms a sixth orthographic projection on the base substrate; The sixth orthographic projection is staggered with the first orthographic projection, the second orthographic projection, the third orthographic projection, the fourth orthographic projection and the fifth orthographic projection.
10. A display device, characterized in that: Comprising the display panel as claimed in any one of claims 1 to 9.