Frequency converter protection circuit for input open-phase and relay pull-in detection

Abstract

The utility model relates to the technical field of frequency converters, in particular to a frequency converter protection circuit used for input open-phase and relay pull-in detection, which comprises a relay pull-in detection circuit, an input open-phase detection circuit and a signal synthesis circuit. The input end A of the NAND gate is connected with the relay pull-in detection circuit, the input end B of the NAND gate is connected with the input open-phase detection circuit, and the output end Y of the NAND gate is connected with the controller. Compared with a traditional detection circuit which only has high-level / low-level signals, the technical problems that in the prior art, two detection functions occupy two signal channels, the circuit is difficult to design, and cost is high can be effectively solved, and the advantage that the states of the two detection functions can be expressed only through the same signal line is achieved.

Description

Technical Field

[0001] The utility model relates to the technical field of frequency converters, in particular to a frequency converter protection circuit for input phase loss and relay pull-in detection. Background Art

[0002] The frequency converter is a power control device that uses frequency conversion technology and microelectronics technology to control AC motors by changing the frequency of the motor's working power supply. It is mainly composed of rectification (AC to DC), filtering, inversion (DC to AC), braking unit, drive unit, detection unit, and microprocessor unit. The frequency converter adjusts the voltage and frequency of the output power supply by the internal IGBT's opening and closing, and provides the required power supply voltage according to the actual needs of the motor, thereby achieving the purpose of energy saving and speed regulation. In addition, the frequency converter has many protection functions, such as over-current, over-voltage, overload protection, etc. With the continuous improvement of industrial automation, frequency converters have also been widely used.

[0003] In the existing inverter design, input phase loss detection and relay pull-in detection are very practical functions. Among them, input phase loss detection can prevent the inverter from working under poor power supply conditions. When the grid loses phase, the power supply is unstable. Long-term operation will cause the temperature of the energy storage capacitor in the inverter to rise, which is easy to damage the device. Relay pull-in detection can prevent the inverter charging relay from not being pulled in, and a large current will pass through the charging resistor during operation, causing damage to the resistor.

[0004] Currently, these two functions are generally designed independently, which will cause the following problems:

[0005] 1. It needs to occupy two MCU pin channels and occupy more chip resources.

[0006] 2. Multi-channel signals will increase the difficulty of system design.

[0007] 3. The R&D and production costs of independent designs will be higher.

[0008] Therefore, a new technical solution is urgently needed to solve the above technical problems. Utility Model Content

[0009] The purpose of the utility model is to overcome the above-mentioned problems of the prior art and provide an inverter protection circuit for input phase loss and relay closure detection to solve the technical problems of the prior art that an independent design needs to occupy two MCU pin channels, occupies more chip resources, and multiple signals increase the difficulty of system design, as well as high R&D costs and production costs.

[0010] The above objectives are achieved through the following technical solutions:

[0011] A frequency converter protection circuit for input phase loss and relay closure detection, comprising a relay closure detection circuit, an input phase loss detection circuit and a signal synthesis circuit, wherein the signal synthesis circuit comprises a NAND gate, an input end A of the NAND gate is connected to the relay closure detection circuit, an input end B of the NAND gate is connected to the input phase loss detection circuit, and an output end Y of the NAND gate is connected to a controller;

[0012] The relay pull-in detection circuit comprises a relay, a charging resistor, a step-down rectifier circuit and a first optical coupler which are connected to each other, and the collector of the first optical coupler is connected to the input terminal A of the NAND gate;

[0013] The input phase loss detection circuit includes a three-phase power supply line, a three-phase step-down rectifier filter circuit and a second optical coupler connected to each other, and the emitter of the second optical coupler is connected to the input terminal B of the NAND gate.

[0014] Further, the step-down rectifier circuit includes a second resistor, a third resistor, a fourth resistor, a fifth resistor, and a rectifier bridge composed of a first diode, a second diode, a third diode and a fourth diode; the cathode of the first diode is connected to the cathode of the second diode to form a first connection end of the rectifier bridge; the anode of the second diode is connected to the cathode of the fourth diode to form a second connection end of the rectifier bridge; the anode of the fourth diode is connected to the anode of the third diode to form a third connection end of the rectifier bridge; the anode of the first diode is connected to the cathode of the third diode to form a fourth connection end of the rectifier bridge; one end of the second resistor is connected to the relay, and the other end is connected to the fourth connection end of the rectifier bridge; one end of the third resistor is connected to the relay, and the other end is connected to the second connection end of the rectifier bridge; one end of the fourth resistor is connected to the first connection end of the rectifier bridge, and the other end is connected to the anode of the first optical coupler, and the cathode of the first optical coupler is connected to the third connection end of the rectifier bridge; the fifth resistor is connected in parallel between the first connection end of the rectifier bridge and the third connection end of the rectifier bridge.

[0015] Furthermore, the collector of the first optical coupler is also connected to a sixth resistor.

[0016] Furthermore, a first capacitor is connected in parallel between the collector and the emitter of the first optical coupler.

[0017] Furthermore, the three-phase power supply line includes an R-phase power supply line, an S-phase power supply line and a T-phase power supply line; the three-phase step-down rectifier and filter circuit includes a second capacitor, a tenth resistor, an eleventh resistor, and a three-phase rectifier bridge composed of a fifth diode, a sixth diode, a seventh diode, an eighth diode, a ninth diode and a tenth diode; the cathode of the fifth diode, the sixth diode and the cathode of the seventh diode are connected to form a first connection end of the three-phase rectifier bridge; the anodes of the eighth diode, the ninth diode and the tenth diode are connected to form a second connection end of the three-phase rectifier bridge; the anode of the fifth diode and the cathode of the eighth diode are connected to form a third connection end of the three-phase rectifier bridge; the sixth diode The anode of the seventh diode is connected to the cathode of the ninth diode, forming the fourth connection terminal of the three-phase rectifier bridge; the anode of the seventh diode is connected to the cathode of the tenth diode, forming the fifth connection terminal of the three-phase rectifier bridge; the first connection terminal of the three-phase rectifier bridge is connected to the positive electrode of the second optical coupler through the eleventh resistor, and the negative electrode of the second optical coupler is connected to the second connection terminal of the three-phase rectifier bridge; the second capacitor and the tenth resistor are respectively connected in parallel between the first connection terminal of the three-phase rectifier bridge and the second connection terminal of the three-phase rectifier bridge; the R-phase power supply line is connected to the third connection terminal of the three-phase rectifier bridge, the S-phase power supply line is connected to the fourth connection terminal of the three-phase rectifier bridge, and the T-phase power supply line is connected to the fifth connection terminal of the three-phase rectifier bridge.

[0018] Furthermore, a seventh resistor is arranged between the R-phase power supply line and the third connection end of the three-phase rectifier bridge, an eighth resistor is arranged between the S-phase power supply line and the fourth connection end of the three-phase rectifier bridge, and a ninth resistor is arranged between the T-phase power supply line and the fifth connection end of the three-phase rectifier bridge.

[0019] Furthermore, a twelfth resistor is connected to the emitter of the second optical coupler.

[0020] Furthermore, a first transistor is connected to the output terminal Y of the NAND gate, a base of the first transistor is connected to the output terminal Y of the NAND gate, a collector of the first transistor is connected to the controller, and an emitter of the first transistor is grounded.

[0021] Furthermore, a thirteenth resistor is connected between the output terminal Y of the NAND gate and the base of the first transistor.

[0022] Furthermore, a fifteenth resistor is provided on the collector of the first transistor, and the fifteenth resistor is used to pull up the output signal.

[0023] The inverter protection circuit for inputting phase loss and relay closure detection provided by the utility model combines the two signals of phase loss detection and relay closure detection into one line for transmission without interfering with each other, so that the controller can accurately identify the phase loss and relay closure status. Compared with the traditional detection circuit which only has two high-level / low-level signals, this solution can effectively solve the technical problems of two detection functions occupying two signal channels, the difficulty of circuit design and high cost in the prior art, and realizes the advantage of using only the same signal line to express the status of the two detection functions. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 The circuit diagram of the inverter protection circuit for input phase loss and relay pull-in detection described in the utility model;

[0025] Figure 2 It is a schematic diagram of three-phase AC half-wave rectification and phase loss in the inverter protection circuit for input phase loss and relay pull-in detection described in the utility model;

[0026] Figure 3 This is a waveform diagram of the optocoupler conversion measurement in the inverter protection circuit for input phase loss and relay pull-in detection under normal conditions of three-phase AC power;

[0027] Figure 4 This is a waveform diagram of the optocoupler conversion measurement in the case of a three-phase AC phase loss in the inverter protection circuit for input phase loss and relay pull-in detection described in the utility model;

[0028] Figure 5 The utility model discloses a truth table of a NAND gate in a frequency converter protection circuit for detecting input phase loss and relay closure. DETAILED DESCRIPTION

[0029] The utility model is further described in detail below based on the accompanying drawings and embodiments. The described embodiments are only part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments of the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.

[0030] like Figure 1 As shown, a frequency converter protection circuit for input phase loss and relay closure detection includes a relay closure detection circuit, an input phase loss detection circuit and a signal synthesis circuit, wherein the signal synthesis circuit includes a NAND gate U3, an input terminal A of the NAND gate U3 is connected to the relay closure detection circuit, an input terminal B of the NAND gate U3 is connected to the input phase loss detection circuit, and an output terminal Y of the NAND gate U3 is connected to a controller;

[0031] The relay pull-in detection circuit comprises a relay K1, a charging resistor R1, a step-down rectifier circuit and a first optical coupler U1 which are connected to each other, and the collector of the first optical coupler U1 is connected to the input terminal A of the NAND gate U3;

[0032] The input phase loss detection circuit includes a three-phase power supply line, a three-phase step-down rectifier filter circuit and a second optical coupler U2 connected to each other, and the emitter of the second optical coupler U2 is connected to the input end B of the NAND gate U3.

[0033] Working principle:

[0034] In this embodiment, the relay pull-in signal has two level states: pull-in and non-pull-in, including:

[0035] When the relay is not closed, the current of the entire device will pass through the charging resistor R1, generating a voltage drop, which will be captured by the detection circuit, and the first optocoupler U1 will light up and output a low-level signal;

[0036] When the relay is in the energized state, the electric shock short-circuits the charging resistor R1. At this time, the voltage drop is about 0V, and the second optocoupler U2 will not light up, and a high-level signal will be output.

[0037] In this embodiment, the input phase loss signal has three level states, including:

[0038] like Figure 2 As shown, when the three-phase power supply is stable, the half-wave signals rectified by them have maximum and minimum values, and the fluctuation is not large. After being converted by the second optical coupler U2, it is a stable high level, such as Figure 3 As shown;

[0039] like Figure 4 As shown, when a phase loss occurs, the half-wave signal cannot be output continuously and completely, and a fixed pulse waveform will appear under the conversion of the second optical coupler U2;

[0040] A low level means there is no power input and the device is turned off.

[0041] In this embodiment, the relay closure signal and the input phase loss signal are processed by the NAND gate U3, and the two signals of phase loss detection and relay closure detection are combined into one line for transmission without interfering with each other, so that the controller can accurately identify the phase loss and relay closure status.

[0042] like Figure 5 As shown, in this embodiment, the NAND gate U3 outputs the final signal according to the truth table, which is specifically:

[0043] When the relay is closed and there is no phase failure, the final output is high level;

[0044] When the relay is closed and there is a phase failure, a pulse waveform is finally output;

[0045] When the relay is not energized, regardless of whether there is a phase failure, the final output is a low level;

[0046] It should be noted that the relay failure has a high priority and will definitely damage the charging resistor R1 if it is running; while the phase loss fault has a low priority and will not cause damage to the device if it is running for a short time. Therefore, when a low-level signal appears, the relay must be checked.

[0047] like Figure 1 As shown, the step-down rectifier circuit in this embodiment includes a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, and a rectifier bridge composed of a first diode D1, a second diode D2, a third diode D3 and a fourth diode D4;

[0048] The cathode of the first diode D1 is connected to the cathode of the second diode D2, forming a first connection end of the rectifier bridge; the anode of the second diode D2 is connected to the cathode of the fourth diode D4, forming a second connection end of the rectifier bridge; the anode of the fourth diode D4 is connected to the anode of the third diode D3, forming a third connection end of the rectifier bridge; the anode of the first diode D1 is connected to the cathode of the third diode D3, forming a fourth connection end of the rectifier bridge;

[0049] One end of the second resistor R2 is connected to the relay K1, and the other end is connected to the fourth connection end of the rectifier bridge; one end of the third resistor R3 is connected to the relay K1, and the other end is connected to the second connection end of the rectifier bridge;

[0050] One end of the fourth resistor R4 is connected to the first connection end of the rectifier bridge, and the other end is connected to the positive electrode of the first optical coupler U1, and the negative electrode of the first optical coupler U1 is connected to the third connection end of the rectifier bridge;

[0051] The fifth resistor R5 is connected in parallel between the first connection end of the rectifier bridge and the third connection end of the rectifier bridge.

[0052] The step-down rectifier circuit described in this embodiment is used to shape and limit the collected signal and then transmit it to the first optocoupler U1, and protect the first optocoupler U1 from damage; the first optocoupler U1 converts the relay closure state into high and low level signals and transfers them to the subsequent circuit for processing.

[0053] The collector of the first optical coupler U1 is also connected to a sixth resistor R6 . In this embodiment, the sixth resistor R6 is used as a pull-up resistor to provide a high level 5V.

[0054] A first capacitor C1 is also connected in parallel between the collector and the emitter of the first optical coupler U1 . The first capacitor C1 is used for filtering to improve the anti-interference capability of the signal in the circuit.

[0055] like Figure 1 As shown, the three-phase power supply line in this embodiment includes an R-phase power supply line, an S-phase power supply line and a T-phase power supply line;

[0056] The three-phase step-down rectifier and filter circuit includes a second capacitor C2, a tenth resistor R10, an eleventh resistor R11, and a three-phase rectifier bridge composed of a fifth diode D5, a sixth diode D6, a seventh diode D7, an eighth diode D8, a ninth diode D9 and a tenth diode D10;

[0057] The cathode of the fifth diode D5, the sixth diode D6 and the cathode of the seventh diode D7 are connected to form a first connection end of the three-phase rectifier bridge; the anodes of the eighth diode D8, the ninth diode D9 and the tenth diode D10 are connected to form a second connection end of the three-phase rectifier bridge; the anode of the fifth diode D5 and the cathode of the eighth diode D8 are connected to form a third connection end of the three-phase rectifier bridge; the anode of the sixth diode D6 and the cathode of the ninth diode D9 are connected to form a fourth connection end of the three-phase rectifier bridge; the anode of the seventh diode D7 and the cathode of the tenth diode D10 are connected to form a fifth connection end of the three-phase rectifier bridge;

[0058] The first connection end of the three-phase rectifier bridge is connected to the positive electrode of the second optical coupler U2 through the eleventh resistor R11, and the negative electrode of the second optical coupler U2 is connected to the second connection end of the three-phase rectifier bridge;

[0059] The second capacitor C2 and the tenth resistor R10 are respectively connected in parallel between the first connection end of the three-phase rectifier bridge and the second connection end of the three-phase rectifier bridge;

[0060] The R-phase power supply line is connected to the third connection end of the three-phase rectifier bridge, the S-phase power supply line is connected to the fourth connection end of the three-phase rectifier bridge, and the T-phase power supply line is connected to the fifth connection end of the three-phase rectifier bridge.

[0061] In this embodiment, the three-phase rectifier bridge composed of the fifth diode D5, the sixth diode D6, the seventh diode D7, the eighth diode D8, the ninth diode D9 and the tenth diode D10 is used to rectify the three-phase alternating current into a half-wave signal;

[0062] The second capacitor C2 is used to adjust the signal delay and sensitivity of the input optical coupler; and the tenth resistor R10 and the eleventh resistor R11 are used to stabilize the signal quality.

[0063] A seventh resistor R7 is arranged between the R-phase power supply line and the third connection end of the three-phase rectifier bridge, an eighth resistor R8 is arranged between the S-phase power supply line and the fourth connection end of the three-phase rectifier bridge, and a ninth resistor R9 is arranged between the T-phase power supply line and the fifth connection end of the three-phase rectifier bridge.

[0064] In this embodiment, the seventh resistor R7, the eighth resistor R8 and the ninth resistor R9 are current limiting circuits, which are used to limit the high-voltage electrical signal into a low-current signal, control the current of the input circuit, and thus achieve the purpose of energy saving.

[0065] A twelfth resistor R12 is also connected to the emitter of the second optical coupler U2 , and the twelfth resistor R12 serves as a pull-down resistor for providing a low level of 0V.

[0066] like Figure 1 As shown, the output terminal Y of the NAND gate U3 is connected to a first transistor Q1, the base of the first transistor Q1 is connected to the output terminal Y of the NAND gate U3, the collector of the first transistor Q1 is connected to the controller, and the emitter of the first transistor Q1 is grounded. Specifically, in this embodiment, the first transistor Q1 is used to amplify current and enhance the output current signal.

[0067] In addition, a thirteenth resistor R13 is connected between the output terminal Y of the NAND gate U3 and the base of the first transistor Q1. The thirteenth resistor R13 is used for current limiting to protect the NAND gate U3 from the impact of excessive current.

[0068] A fifteenth resistor R15 is provided on the collector of the first transistor Q1, and the fifteenth resistor R15 is used to pull up the output signal; in this embodiment, a fourteenth resistor R14 is connected in parallel between the base of the first transistor Q1 and the emitter of the first transistor Q1, and the fourteenth resistor R14 is used to pull down the control signal.

[0069] The above description is only for illustrating the implementation mode of the present invention and is not intended to limit the present invention. For those skilled in the art, any modification, equivalent substitution, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A frequency converter protection circuit for input phase loss and relay closure detection, characterized in that: It comprises a relay closure detection circuit, an input phase loss detection circuit and a signal synthesis circuit, wherein the signal synthesis circuit comprises a NAND gate (U3), an input end A of the NAND gate (U3) is connected to the relay closure detection circuit, an input end B of the NAND gate (U3) is connected to the input phase loss detection circuit, and an output end Y of the NAND gate (U3) is connected to a controller; The relay pull-in detection circuit comprises a relay (K1), a charging resistor (R1), a step-down rectifier circuit and a first optical coupler (U1) which are connected to each other, and the collector of the first optical coupler (U1) is connected to the input terminal A of the NAND gate (U3); The input phase loss detection circuit comprises a three-phase power supply line, a three-phase step-down rectifier filter circuit and a second optical coupler (U2) which are connected to each other, and the emitter of the second optical coupler (U2) is connected to the input end B of the NAND gate (U3).

2. The inverter protection circuit for input phase loss and relay pull-in detection according to claim 1, characterized in that: The step-down rectifier circuit comprises a second resistor (R2), a third resistor (R3), a fourth resistor (R4), a fifth resistor (R5), and a rectifier bridge composed of a first diode (D1), a second diode (D2), a third diode (D3) and a fourth diode (D4); The cathode of the first diode (D1) is connected to the cathode of the second diode (D2) to form a first connection end of the rectifier bridge; the anode of the second diode (D2) is connected to the cathode of the fourth diode (D4) to form a second connection end of the rectifier bridge; the anode of the fourth diode (D4) is connected to the anode of the third diode (D3) to form a third connection end of the rectifier bridge; the anode of the first diode (D1) is connected to the cathode of the third diode (D3) to form a fourth connection end of the rectifier bridge; One end of the second resistor (R2) is connected to the relay (K1), and the other end is connected to the fourth connection end of the rectifier bridge; one end of the third resistor (R3) is connected to the relay (K1), and the other end is connected to the second connection end of the rectifier bridge; One end of the fourth resistor (R4) is connected to the first connection end of the rectifier bridge, and the other end is connected to the positive electrode of the first optical coupler (U1), and the negative electrode of the first optical coupler (U1) is connected to the third connection end of the rectifier bridge; The fifth resistor (R5) is connected in parallel between the first connection end of the rectifier bridge and the third connection end of the rectifier bridge.

3. The inverter protection circuit for input phase loss and relay pull-in detection according to claim 1 or 2, characterized in that: The collector of the first optical coupler (U1) is also connected to a sixth resistor (R6).

4. The inverter protection circuit for input phase loss and relay pull-in detection according to claim 3, characterized in that: A first capacitor (C1) is also connected in parallel between the collector and emitter of the first optical coupler (U1).

5. The inverter protection circuit for input phase loss and relay pull-in detection according to claim 1, characterized in that: The three-phase power supply line includes an R-phase power supply line, an S-phase power supply line and a T-phase power supply line; The three-phase step-down rectifier and filter circuit comprises a second capacitor (C2), a tenth resistor (R10), an eleventh resistor (R11), and a three-phase rectifier bridge composed of a fifth diode (D5), a sixth diode (D6), a seventh diode (D7), an eighth diode (D8), a ninth diode (D9) and a tenth diode (D10); The cathode of the fifth diode (D5), the cathode of the sixth diode (D6) and the cathode of the seventh diode (D7) are connected to form a first connection end of the three-phase rectifier bridge; the anodes of the eighth diode (D8), the ninth diode (D9) and the tenth diode (D10) are connected to form a second connection end of the three-phase rectifier bridge; the anode of the fifth diode (D5) and the cathode of the eighth diode (D8) are connected to form a third connection end of the three-phase rectifier bridge; the anode of the sixth diode (D6) and the cathode of the ninth diode (D9) are connected to form a fourth connection end of the three-phase rectifier bridge; the anode of the seventh diode (D7) and the cathode of the tenth diode (D10) are connected to form a fifth connection end of the three-phase rectifier bridge; The first connection end of the three-phase rectifier bridge is connected to the positive electrode of the second optical coupler (U2) through the eleventh resistor (R11), and the negative electrode of the second optical coupler (U2) is connected to the second connection end of the three-phase rectifier bridge; The second capacitor (C2) and the tenth resistor (R10) are respectively connected in parallel between the first connection end of the three-phase rectifier bridge and the second connection end of the three-phase rectifier bridge; The R-phase power supply line is connected to the third connection end of the three-phase rectifier bridge, the S-phase power supply line is connected to the fourth connection end of the three-phase rectifier bridge, and the T-phase power supply line is connected to the fifth connection end of the three-phase rectifier bridge.

6. The inverter protection circuit for input phase loss and relay closure detection according to claim 5, characterized in that: A seventh resistor (R7) is arranged between the R-phase power supply line and the third connection end of the three-phase rectifier bridge, an eighth resistor (R8) is arranged between the S-phase power supply line and the fourth connection end of the three-phase rectifier bridge, and a ninth resistor (R9) is arranged between the T-phase power supply line and the fifth connection end of the three-phase rectifier bridge.

7. The inverter protection circuit for input phase loss and relay closure detection according to claim 5, characterized in that: The emitter of the second optical coupler (U2) is also connected to a twelfth resistor (R12).

8. The inverter protection circuit for input phase loss and relay pull-in detection according to claim 1, characterized in that: A first transistor (Q1) is connected to the output end Y of the NAND gate (U3), a base of the first transistor (Q1) is connected to the output end Y of the NAND gate (U3), a collector of the first transistor (Q1) is connected to the controller, and an emitter of the first transistor (Q1) is grounded.

9. The inverter protection circuit for input phase loss and relay pickup detection according to claim 8, characterized in that: A thirteenth resistor (R13) is connected between the output terminal Y of the NAND gate (U3) and the base of the first transistor (Q1).

10. The inverter protection circuit for input phase loss and relay pickup detection according to claim 8, characterized in that: A fifteenth resistor (R15) is arranged on the collector of the first transistor (Q1), and the fifteenth resistor (R15) is used to pull up the output signal.

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