Current backflow prevention circuit and communication terminal

Abstract

The utility model relates to a current backflow prevention circuit and a communication terminal, the current backflow prevention circuit is used for a multiprocessor system, the multiprocessor system comprises a first central processing unit (CPU) and a second CPU, and the current backflow prevention circuit comprises a first switch tube and a second switch tube; the first switch tube is respectively connected with the second switch tube, the first output end of the first CPU and the input end of the second CPU; the second switch tube is also connected with the voltage input end of the second CPU; when the second CPU is not powered on, the second switch tube is disconnected, the first switch tube is disconnected when the second switch tube is disconnected, and the first output end of the first CPU is disconnected with the input end of the second CPU; when the second CPU is powered on, the second switch tube is switched on, the first switch tube is switched on when the second switch tube is switched on, and the first output end of the first CPU is switched on with the input end of the second CPU. According to the invention, the problem of current backflow in the prior art is solved.

Description

Technical Field

[0001] The present application relates to the field of circuit technology, and in particular to a current backflow prevention circuit and a communication terminal. Background Art

[0002] At present, handheld narrowband terminals, multi-mode terminals, and vehicle-mounted terminals are all multi-processor systems. When a multi-processor system communicates, current backflow problems often occur due to the order in which the processors are powered on. Current backflow can cause abnormal power-on and startup of the processors to which the backflow is applied, resulting in abnormal operation. Utility Model Content

[0003] The present application provides a current backflow prevention circuit and a communication terminal to solve the current backflow problem in the prior art.

[0004] In a first aspect, the present application provides an anti-current backflow circuit for a multi-processor system, wherein the multi-processor system comprises a first central processing unit (CPU) and a second CPU, and the anti-current backflow circuit comprises a first switch tube and a second switch tube; the first switch tube is respectively connected to the second switch tube, the first output end of the first CPU, and the input end of the second CPU; the second switch tube is also connected to the voltage input end of the second CPU; when the second CPU is not powered on, the second switch tube is disconnected, the first switch tube is disconnected when the second switch tube is disconnected, and the first output end of the first CPU is disconnected from the input end of the second CPU; when the second CPU is powered on, the second switch tube is turned on, the first switch tube is turned on when the second switch tube is turned on, and the first output end of the first CPU is connected to the input end of the second CPU.

[0005] Optionally, the first switch tube and the second switch tube are both MOS tubes.

[0006] Optionally, the first switch tube is a PMOS tube, and the second switch tube is an NMOS tube. The gate of the PMOS tube is connected to the drain of the NMOS tube, the source of the PMOS tube is connected to the first output end of the first CPU, and the drain of the PMOS tube is connected to the input end of the second CPU; the gate of the NMOS tube is connected to the voltage input end of the second CPU, and the source of the NMOS tube is grounded.

[0007] Optionally, the current backflow prevention circuit further includes a resistor; one end of the resistor is connected to the first output end of the first CPU, and the other end of the resistor is connected to the gate of the PMOS tube.

[0008] In a second aspect, the present application provides a communication terminal, including a multi-processor system and the current backflow prevention circuit described in the first aspect.

[0009] Optionally, the communication terminal also includes a power control module, which is respectively connected to the second output end of the first CPU and the voltage input end of the second CPU; the power control module is used to provide voltage to the voltage input end of the second CPU when enabled by the control signal output by the first CPU, so as to power on the second CPU.

[0010] Optionally, the power control module includes a low-dropout linear regulator LDO, an enable terminal of the LDO is connected to the second output terminal of the first CPU, and a voltage output terminal of the LDO is connected to a voltage input terminal of the second CPU.

[0011] Optionally, the power control module includes a power switch module DC-DC, an enable end of the DC-DC is connected to the second output end of the first CPU, and a voltage output end of the DC-DC is connected to the voltage input end of the second CPU.

[0012] The above technical solution provided by the embodiment of the present application has the following advantages compared with the prior art: in the embodiment of the present application, by connecting the first switch tube and the second switch tube in series between the two CPUs, when the first CPU is powered on and the second CPU is not powered on, if the second switch is disconnected, the first switch tube is also disconnected, and after the second CPU is powered on, the first switch tube and the second switch tube are both turned on. That is, when only one CPU is powered on, there is no conduction between the first CPU and the second CPU, which prevents current backflow. Only after both CPUs are powered on, the first switch tube and the second switch tube will be turned on, that is, the two CPUs can communicate normally. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The accompanying drawings herein are incorporated in and constitute a part of the specification, illustrate embodiments consistent with the present utility model, and together with the description, are used to explain the principles of the present utility model.

[0014] In order to more clearly illustrate the technical solutions in the embodiments of the utility model or the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0015] One or more embodiments are exemplarily described by pictures in the corresponding drawings, and these exemplified descriptions do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings represent similar elements, and unless otherwise stated, the figures in the drawings do not constitute proportional limitations.

[0016] Figure 1 This is one of the schematic diagrams of the current backflow prevention circuit in the prior art;

[0017] Figure 2 The second schematic diagram of the current backflow prevention circuit in the prior art;

[0018] Figure 3 is a schematic diagram of an anti-backflow circuit in an embodiment of the present application;

[0019] Figure 4 It is an optional schematic diagram of the anti-backflow circuit in the embodiment of the present application. DETAILED DESCRIPTION

[0020] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0021] The disclosure below provides many different embodiments or examples for realizing different structures of the present invention. In order to simplify the disclosure of the present invention, the components and settings of specific examples are described below. Of course, they are only examples, and the purpose is not to limit the present invention. In addition, the present invention may repeat reference numbers and / or letters in different examples. This repetition is for the purpose of simplification and clarity, and does not itself indicate the relationship between the various embodiments and / or settings discussed.

[0022] like Figure 1 As shown, the current backflow prevention circuit in the prior art includes a first switch circuit and a second switch circuit, and controls the current backflow through the two-stage switch circuit of PMOS and triode. However, the circuit in the prior art requires a control circuit IO to control the state of the switch circuit, which is relatively complicated, and because of the introduction of IO control, if the IO port is abnormal or damaged, the current backflow prevention circuit fails.

[0023] like Figure 2 As shown, another bidirectional IO circuit for preventing current backflow in the prior art describes a bidirectional IO circuit, which includes a gate voltage bias module, a substrate voltage bias module, 2 PMOS, and one NMOS. It can be seen that the circuit is relatively costly and complex.

[0024] It can be seen that the prior art generally attempts to solve the problem by configuring the sending end IO with software, or by connecting a voltage divider resistor in series to weaken the backflow current. However, the software version modification test time is too long, and if the software configuration cannot solve the backflow, there is no alternative solution. In other words, the anti-backflow method in the prior art has a high time cost, is relatively complex, and its stability needs to be improved.

[0025] In view of the circuit for preventing backflow in the above-mentioned prior art, the embodiment of the present application provides a circuit for preventing current backflow, such as Figure 3 As shown, the current backflow prevention circuit in the embodiment of the present application is used in a multi-processor system, and the multi-processor system includes a first central processing unit CPU and a second CPU, and the current backflow prevention circuit includes a first switch tube and a second switch tube;

[0026] The first switch tube is connected to the second switch tube, the first output terminal of the first CPU, and the input terminal of the second CPU respectively; the second switch tube is also connected to the voltage input terminal of the second CPU;

[0027] When the second CPU is not powered on, the second switch tube is turned off, the first switch tube is turned off when the second switch tube is turned off, and the first output end of the first CPU is disconnected from the input end of the second CPU;

[0028] When the second CPU is powered on, the second switch tube is turned on, the first switch tube is turned on when the second switch tube is turned on, and the first output end of the first CPU is connected to the input end of the second CPU.

[0029] In the embodiment of the present application, the first switch tube and the second switch tube are connected in series between the two CPUs. When only one CPU is powered on, there is no conduction between the first CPU and the second CPU, thereby preventing current backflow. Only after both CPUs are powered on, the first switch tube and the second switch tube are both turned on, that is, the two CPUs communicate normally, thereby solving the problem of current backflow.

[0030] In an optional implementation manner in the embodiments of the present application, Figure 4 As shown, the first switch tube and the second switch tube in the embodiment of the present application are both MOS tubes, and the first switch tube is a PMOS tube, and the second switch tube is an NMOS tube. Among them, the gate of the PMOS tube is connected to the drain of the NMOS tube, the source of the PMOS tube is connected to the first output terminal of the first CPU, and the drain of the PMOS tube is connected to the input terminal of the second CPU; the gate of the NMOS tube is connected to the voltage input terminal of the second CPU, and the source of the NMOS tube is grounded.

[0031] It can be seen that in the embodiment of the present application, by connecting the NMOS tube and the PMOS tube in series between the two CPUs, when the first CPU is powered on and the second CPU is not powered on, the PMOS tube and the NMOS tube are both turned off, and after the second CPU is powered on, the PMOS tube and the NMOS tube are both turned on. That is, when only one CPU is powered on, there is no conduction between the first CPU and the second CPU, which prevents current backflow. Only after both CPUs are powered on, the PMOS tube and the NMOS tube will be turned on, that is, the two CPUs can communicate normally, which solves the problem of current backflow in the prior art, and compared with Figure 1 and Figure 2 The prior art has a better effect of preventing backflow.

[0032] like Figure 4 As shown, the current backflow prevention circuit in the embodiment of the present application also includes a resistor; one end of the resistor is connected to the first output end of the first CPU, and the other end of the resistor is connected to the gate of the PMOS tube.

[0033] like Figure 4 As shown, the current backflow prevention circuit in the embodiment of the present application also includes a low voltage difference linear regulator LDO; the enable end (EN pin) of the LDO is connected to the second output end (OUTPUT2 signal pin) of the first CPU, and the voltage output end (VCCOUT signal pin) of the LDO is connected to the voltage input end of the second CPU, wherein the voltage input end of the second CPU is a pin connected to the power supply VCC2. Or, the current backflow prevention circuit also includes a power switch module DC-DC, the enable end (EN pin) of the DC-DC is connected to the second output end (OUTPUT2 signal pin) of the first CPU, and the voltage output end (VCC OUT signal pin) of the DC-DC is connected to the voltage input end of the second CPU.

[0034] It should be noted that for dual CPU communication, the power-on timing is different. The IO of the first CPU that is powered on first will backflow current to the pin of the second CPU that is powered on later, causing the second CPU to work abnormally or start abnormally. Based on the anti-backflow circuit of the above-mentioned embodiment of the present application, in the embodiment of the present application, PMOS and NMOS circuits are connected in series between the unidirectional signals of the two CPUs; the problem of backflow current is solved by controlling the switching state of the two MOS tubes. Specifically: the first CPU is powered on first, and after power-on, when the power supply VCC2 of the second CPU is not powered on; NMOS tube Q2 (second MOS tube) is turned off, and thus PMOS tube Q1 (first MOS tube) is turned off; the first output end (OUTPUT1 signal pin) of the first CPU is isolated from the input end (signal pin INPUT1) of the second CPU, preventing OUTPUT1 from backflowing current to INPUT1. Therefore, after the power supply VCC2 of the second CPU is powered on, the VGS of NMOS is greater than the threshold voltage VGS(th) of the NMOS tube, and the NMOS is turned on. At this time, the VGS of PMOS is less than the threshold voltage VGS(th) of the PMOS tube, and the PMOS is turned on. OUTPUT1 can send data to INPUT1 to start communication.

[0035] In other embodiments of the embodiments of the present application, the embodiments of the present application further provide a system including a multi-processor system and the above-mentioned current backflow prevention circuit.

[0036] Among them, the communication terminal also includes a power control module, which is respectively connected to the second output end of the first CPU and the voltage input end of the second CPU; the power control module is used to provide voltage to the voltage input end of the second CPU when enabled by the control signal output by the first CPU, so as to power on the second CPU.

[0037] In a specific example, the power control module in the embodiment of the present application includes a low voltage difference linear regulator LDO, an enable end of the LDO is connected to the second output end of the first CPU, and a voltage output end of the LDO is connected to the voltage input end of the second CPU.

[0038] In a specific example, the power control module in the embodiment of the present application includes a power switch module DC-DC, the enable end of the DC-DC is connected to the second output end of the first CPU, and the voltage output end of the DC-DC is connected to the voltage input end of the second CPU.

[0039] The device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0040] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a general hardware platform, and of course, by hardware. Based on this understanding, the above technical solution is essentially or the part that contributes to the relevant technology can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0041] It should be understood that the terms used herein are only for the purpose of describing specific example embodiments and are not intended to be limiting. Unless the context clearly indicates otherwise, the singular forms "one", "an" and "said" as used herein may also be meant to include plural forms. The terms "include", "comprise", "contain", and "have" are inclusive, and therefore specify the existence of stated features, steps, operations, elements and / or parts, but do not exclude the existence or addition of one or more other features, steps, operations, elements, parts, and / or combinations thereof. The method steps, processes, and operations described herein are not interpreted as necessarily requiring them to be performed in the specific order described or illustrated, unless the execution order is clearly indicated. It should also be understood that additional or alternative steps may be used.

[0042] The above description is only a specific embodiment of the present invention, so that those skilled in the art can understand or implement the present invention. Various modifications to these embodiments will be obvious to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but should conform to the widest scope consistent with the principles and novel features applied herein.

Claims

1. A current backflow prevention circuit, characterized in that: Used in a multi-processor system, the multi-processor system includes a first central processing unit (CPU) and a second CPU, and the current backflow prevention circuit includes a first switch tube and a second switch tube; The first switch tube is connected to the second switch tube, the first output terminal of the first CPU, and the input terminal of the second CPU respectively; the second switch tube is also connected to the voltage input terminal of the second CPU; When the second CPU is not powered on, the second switch tube is turned off, the first switch tube is turned off when the second switch tube is turned off, and the first output end of the first CPU is disconnected from the input end of the second CPU; When the second CPU is powered on, the second switch tube is turned on, the first switch tube is turned on when the second switch tube is turned on, and the first output end of the first CPU is connected to the input end of the second CPU.

2. The current backflow prevention circuit according to claim 1, characterized in that: The first switch tube and the second switch tube are both MOS tubes.

3. The current backflow prevention circuit according to claim 2, characterized in that: The first switch tube is a PMOS tube, and the second switch tube is an NMOS tube. The gate of the PMOS tube is connected to the drain of the NMOS tube, the source of the PMOS tube is connected to the first output end of the first CPU, and the drain of the PMOS tube is connected to the input end of the second CPU; the gate of the NMOS tube is connected to the voltage input end of the second CPU, and the source of the NMOS tube is grounded.

4. The current backflow prevention circuit according to claim 3, characterized in that: The current backflow prevention circuit also includes a resistor; one end of the resistor is connected to the first output end of the first CPU, and the other end of the resistor is connected to the gate of the PMOS tube.

5. A communication terminal, characterized in that: It comprises a multi-processor system and the current backflow prevention circuit as described in any one of claims 1 to 4.

6. The communication terminal according to claim 5, characterized in that: The communication terminal also includes a power control module, which is respectively connected to the second output end of the first CPU and the voltage input end of the second CPU; the power control module is used to provide voltage to the voltage input end of the second CPU when enabled by the control signal output by the first CPU, so as to power on the second CPU.

7. The communication terminal according to claim 6, characterized in that: The power control module includes a low-dropout linear regulator LDO, an enable terminal of the LDO is connected to the second output terminal of the first CPU, and a voltage output terminal of the LDO is connected to the voltage input terminal of the second CPU.

8. The communication terminal according to claim 6, characterized in that: The power control module comprises a power switch module DC-DC, an enable end of the DC-DC is connected to the second output end of the first CPU, and a voltage output end of the DC-DC is connected to the voltage input end of the second CPU.

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