Composite trench gate silicon carbide VDMOS capable of improving gate reliability
By adopting a composite trench gate structure in SiC VDMOS and using high K dielectric hafnium dioxide as the gate dielectric layer, the reliability problem caused by electric field concentration at the bottom corner of the gate is solved, and higher device reliability and lower on-resistance.
Patent Information
- Application Number
- CN202420794500.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-04-17
- Publication Date
- 2025-02-18
- Estimated Expiration
- 2034-04-17
AI Technical Summary
The gate dielectric reliability of trench gate SiC VDMOS is affected by the electric field concentration at the corner of the gate and the SiC/SiO2 interface defects, resulting in limited device development.
A composite trench gate structure is adopted, the device gate lower part uses high K dielectric hafnium dioxide as the gate dielectric layer, and the device gate upper part uses traditional SiO2 as the first gate dielectric layer to improve the electric field tolerance at the corners of the bottom of the gate.
Improves gate reliability, reduces on-resistance, and maintains the switching speed of the device.
Smart Images
Figure CN222509864U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of silicon carbide vertical power devices, in particular to a composite trench gate silicon carbide VDMOS with improved gate reliability. Background Art
[0002] As a representative device among SiC power devices, SiC VDMOS is widely used in electric vehicles, aerospace, power conversion and other fields. Trench-gate SiC VDMOS has become the focus of research due to its strong gate control capability and low on-resistance. However, due to the electric field concentration at the bottom corner of the trench gate and the SiC / SiO2 interface defect problem, the gate dielectric reliability has always restricted the development of trench-gate SiC VDMOS. Utility Model Content
[0003] The technical problem to be solved by the utility model is to provide a composite trench gate silicon carbide VDMOS with improved gate reliability, wherein the electric field concentration at the bottom corner of the gate has higher tolerance, thereby improving the reliability of the gate.
[0004] The utility model is implemented as follows: a composite trench gate silicon carbide VDMOS with improved gate reliability, comprising:
[0005] Silicon carbide substrate,
[0006] A drift layer, wherein the lower side of the drift layer is connected to the upper side of the silicon carbide substrate, a well region is provided on the drift layer, a p-type source region and an N-type source region are provided in the well region, and a side of the P-type source region is connected to a side of the N-type source region; and a groove is provided on the drift layer;
[0007] A high-K gate dielectric layer, wherein the high-K gate dielectric layer is disposed in the groove, and the high-K gate dielectric layer is provided with a groove;
[0008] a first gate dielectric layer, wherein the first gate dielectric layer is disposed in the groove and above the high-K gate dielectric layer, and a through hole is disposed on the first gate dielectric layer, and the through hole is connected to the groove;
[0009] A gate metal layer, the gate metal layer is disposed in the through hole and the groove;
[0010] A source metal layer, the source metal layer is connected to the N-type source region and the P-type source region;
[0011] and a drain metal layer connected to a lower side of the silicon carbide substrate.
[0012] The advantages of the utility model are:
[0013] 1. The device adopts a trench gate VDMOS structure, which has strong gate control capability and low on-resistance;
[0014] Second, the device adopts a composite trench gate structure, with high-K dielectric hafnium dioxide used as the dielectric layer at the bottom of the device gate, and traditional SiO2 used as the first gate dielectric layer at the top of the device gate;
[0015] 3. The high-K dielectric layer at the bottom of the device gate has both process compatibility and higher quality, high critical breakdown field strength, and higher tolerance to electric field concentration at the bottom corner of the gate, thereby improving the reliability of the gate;
[0016] 4. The high-K gate dielectric layer uses hafnium dioxide, which has a higher dielectric constant k. Therefore, when the device is turned on, the electron concentration formed in the bottom area of the gate is higher, and the on-resistance of the device is smaller;
[0017] 5. Silicon dioxide is still used as the first gate dielectric layer on the top of the device gate. The preparation process is more mature, the preparation speed is fast, the dielectric constant is small, the gate-source capacitance is small, and the switching speed of the device can be effectively guaranteed. BRIEF DESCRIPTION OF THE DRAWINGS
[0018] The present invention will be further described below in conjunction with the embodiments with reference to the accompanying drawings.
[0019] Figure 1 The utility model is a schematic diagram of a composite trench gate silicon carbide VDMOS for improving gate reliability.
[0020] Figure 2 The utility model discloses a flow chart of a method for preparing a composite trench gate silicon carbide VDMOS for improving gate reliability.
[0021] Figure 3 This is a cross-sectional view of the process of a composite trench gate silicon carbide VDMOS with improved gate reliability according to the utility model. Figure 1 .
[0022] Figure 4 This is a cross-sectional view of the process of a composite trench gate silicon carbide VDMOS with improved gate reliability according to the utility model. Figure 2 .
[0023] Figure 5 This is a cross-sectional view of the process of a composite trench gate silicon carbide VDMOS with improved gate reliability according to the utility model. Figure 3 .
[0024] Figure 6 This is a cross-sectional view of the process of a composite trench gate silicon carbide VDMOS with improved gate reliability according to the utility model. Figure 4 .
[0025] Figure 7This is a cross-sectional view of the process of a composite trench gate silicon carbide VDMOS with improved gate reliability according to the utility model. Figure 5 .
[0026] Figure 8 This is a cross-sectional view of the process of a composite trench gate silicon carbide VDMOS with improved gate reliability according to the utility model. Figure 6 .
[0027] Fig. 9 This is a cross-sectional view of the process of a composite trench gate silicon carbide VDMOS with improved gate reliability according to the utility model. Figure 7 .
[0028] Fig.10 This is a cross-sectional view of the process of a composite trench gate silicon carbide VDMOS with improved gate reliability according to the utility model. Figure 8 .
[0029] Fig.11 This is a cross-sectional view of the process of a composite trench gate silicon carbide VDMOS with improved gate reliability according to the utility model. Figure 9 .
[0030] Fig.12 This is a cross-sectional view of the process of a composite trench gate silicon carbide VDMOS with improved gate reliability according to the utility model. Figure 10 . DETAILED DESCRIPTION
[0031] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.
[0032] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.
[0033] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "in contact with ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or part discussed below can be represented as a second element, component, region, layer or part.
[0034] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of one element or feature described in the figures to other elements or features. It should be understood that, in addition to the orientations described in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.
[0035] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.
[0036] like Figure 1 As shown, the embodiment of the present application provides a composite trench gate silicon carbide VDMOS with improved gate reliability, including:
[0037] Silicon carbide substrate 1,
[0038] A drift layer 2, wherein the lower side of the drift layer 2 is connected to the upper side of the silicon carbide substrate 1, a well region 21 is provided on the drift layer 2, a p-type source region 22 and an N-type source region 23 are provided in the well region 21, and a side of the P-type source region 22 is connected to a side of the N-type source region 23; a groove 24 is provided on the drift layer 2;
[0039] A high-K gate dielectric layer 3, wherein the high-K gate dielectric layer 3 is disposed in the groove 24, and a groove 31 is disposed on the high-K gate dielectric layer 3;
[0040] A first gate dielectric layer 4, wherein the first gate dielectric layer 4 is disposed in the groove 24 and above the high-K gate dielectric layer 3, and a through hole 41 is disposed on the first gate dielectric layer 4, and the through hole 41 is connected to the groove 31;
[0041] A gate metal layer 5, wherein the gate metal layer 5 is disposed in the through hole 41 and the groove 31;
[0042] A source metal layer 6, wherein the source metal layer 6 is connected to the N-type source region 23 and the P-type source region 22;
[0043] and a drain metal layer 7 , wherein the drain metal layer 7 is connected to the lower side of the silicon carbide substrate 1 .
[0044] The depth of the groove 24 minus the thickness of the well region 21 is 100-500nm; the thickness of the high-K gate dielectric layer 3 is 200-600nm, and the top of the high-K gate dielectric layer 3 is 100nm higher than the bottom of the well region 21, and the depth of the trench 31 is at least 50nm.
[0045] The device adopts a composite trench gate structure, and a high-K dielectric hafnium dioxide is used in the high-K gate dielectric layer 3 at the bottom of the device gate, and the traditional SiO2 is used as the gate dielectric at the top of the device gate to solve the gate dielectric breakdown problem caused by the electric field concentration at the bottom corner of the gate. The high-K dielectric hafnium dioxide in the high-K gate dielectric layer 3 at the bottom of the device gate has both the process compatibility of silicon carbide and higher quality than silicon dioxide, a high critical breakdown field strength, and a higher tolerance to the electric field concentration at the bottom corner of the gate, thereby improving the reliability of the gate; the dielectric constant k of hafnium dioxide is higher, so when the device is turned on, the electron concentration formed in the bottom area of the gate is higher, and the electron concentration increase area formed by its gate control overlaps with the conductive channel, which can effectively reduce the on-resistance of the device; silicon dioxide is still used as the gate dielectric at the top of the device gate, and the preparation process is more mature, the preparation speed is fast, the dielectric constant is small, the gate-source capacitance is small, and the switching speed of the device can be effectively guaranteed.
[0046] like Figures 1 to 12 As shown, the method for preparing the silicon carbide VDMOS obtained by the above manufacturing method comprises the following steps:
[0047] Step 1: depositing metal on one side of the silicon carbide substrate 1 to form a drain metal layer 7, and depositing and growing a drift layer 2 on the other side of the silicon carbide substrate 1;
[0048] Step 2: depositing a barrier layer a on the drift layer 2, etching the barrier layer a to form a through hole, and performing ion implantation into the drift layer 2 through the through hole to form a well region 21, wherein the ion implantation energy is 10-200 keV;
[0049] Step 3, removing the barrier layer a, re-depositing to form the barrier layer a, etching the barrier layer a to form a through hole, and performing ion implantation into the well region 21 through the through hole to form an N-type source region 23, wherein the ion implantation energy is 10-100 keV;
[0050] Step 4, remove the original barrier layer a, re-form the barrier layer a, etch the barrier layer a to form a through hole, and perform ion implantation into the well region 21 through the through hole to form a P-type source region 22, with the ion implantation energy being 10-100 keV;
[0051] Step 5, removing the original barrier layer a, re-forming the barrier layer a, etching to form a through hole, and performing metal deposition through the through hole to form a source metal layer 6;
[0052] Step 6, removing the original barrier layer a, re-forming the barrier layer a, etching the barrier layer a and the drift layer 2, respectively forming a through hole and a groove 24, first depositing a high-K gate dielectric layer 3 in the groove 24, and then depositing a first gate dielectric layer 4;
[0053] Step 7, remove the original barrier layer a, re-form the barrier layer a, etch the barrier layer a, the first gate dielectric layer 4 and the high-K gate dielectric layer 3 to form a through hole, a perforation 41 and a groove 31 respectively, deposit metal through the through hole to form a gate metal layer 5, remove the barrier layer a, and complete the manufacturing.
[0054] The depth of the groove 24 minus the thickness of the well region 21 is 100-500nm; the thickness of the high-K gate dielectric layer 3 is 200-600nm, and the top of the high-K gate dielectric layer 3 is 100nm higher than the bottom of the well region 21, and the top of the high-K gate dielectric layer 3 is 100nm higher than the bottom of the p-type well region 21. This is to ensure that the interface between the high-K gate dielectric layer 3 and the first gate dielectric layer is higher than the bottom surface of the well region 21, thereby suppressing possible gate leakage at the interface.
[0055] The depth of the trench 31 is at least 50 nm, ensuring that the gate metal is completely in the hafnium dioxide dielectric at the corners. The high-K gate dielectric layer 3 is hafnium dioxide.
[0056] The silicon carbide substrate 1 and the drift layer 2 are N-type; the well region 21 is P-type, the doping concentration of the silicon carbide substrate 1 is 2e18cm-3, the doping concentration of the drift layer is 3e16cm-3, the doping concentration of the P-type source region is 6e18cm-3, the doping concentration of the N-type source region is 2e18cm-3, and the doping concentration of the P-type well region is 3e17 cm-3. The device adopts a trench gate VDMOS structure with strong gate control capability and low on-resistance.
[0057] Although the specific implementation methods of the present invention are described above, those skilled in the art should understand that the specific embodiments described are only illustrative and are not intended to limit the scope of the present invention. Equivalent modifications and changes made by those skilled in the art in accordance with the spirit of the present invention should be included in the scope of protection of the claims of the present invention.
Claims
1. A composite trench gate silicon carbide VDMOS with improved gate reliability, characterized in that: include: Silicon carbide substrate, A drift layer, wherein the lower side of the drift layer is connected to the upper side of the silicon carbide substrate, a well region is provided on the drift layer, a P-type source region and an N-type source region are provided in the well region, and a side of the P-type source region is connected to a side of the N-type source region; and a groove is provided on the drift layer; A high-K gate dielectric layer, wherein the high-K gate dielectric layer is disposed in the groove, and the high-K gate dielectric layer is provided with a groove; a first gate dielectric layer, wherein the first gate dielectric layer is disposed in the groove and above the high-K gate dielectric layer, and a through hole is disposed on the first gate dielectric layer, and the through hole is connected to the groove; A gate metal layer, the gate metal layer is disposed in the through hole and the groove; A source metal layer, the source metal layer is connected to the N-type source region and the P-type source region; and a drain metal layer connected to a lower side of the silicon carbide substrate.
2. A composite trench gate silicon carbide VDMOS with improved gate reliability as claimed in claim 1, characterized in that: The depth of the groove minus the thickness of the well region is 100-500nm; the thickness of the high-K gate dielectric layer is 200-600nm, and the top of the high-K gate dielectric layer is 100nm higher than the bottom of the well region.
3. A composite trench gate silicon carbide VDMOS with improved gate reliability as claimed in claim 1, characterized in that: The depth of the groove is at least 50 nm.
4. A composite trench gate silicon carbide VDMOS with improved gate reliability as claimed in claim 1, characterized in that: The high-K gate dielectric layer is hafnium dioxide.
5. A composite trench gate silicon carbide VDMOS with improved gate reliability as claimed in claim 1, characterized in that: The silicon carbide substrate and the drift layer are of N type; the well region is of P type.