Circuit board deformation detection device

Abstract

The utility model relates to the technical field of circuit boards, and particularly provides a circuit board deformation detection device, which comprises a capacitance bridge, a detection module, a detection module and a processing module, and is characterized in that the capacitance bridge comprises a plurality of capacitors with the same capacitance; the capacitor is packaged on a circuit board to be tested; the capacitor bridge is connected with the input end of the voltage acquisition circuit, the output end of the voltage acquisition circuit is electrically connected with the input end of the analog-to-digital converter, the analog-to-digital converter is used for converting an electric signal into a binary digital signal, and the output end of the analog-to-digital converter is electrically connected with the signal recorder; and the capacitor bridge is electrically connected with an alternating current power supply. According to the invention, the stress borne by the circuit board can be recorded in real time, and for high-reliability application, all stress bearing processes experienced by the circuit board after welding is completed can be recorded no matter whether the circuit board is powered off or not.

Description

Technical Field

[0001] The present invention belongs to the technical field of circuit boards, and in particular relates to a circuit board deformation detection device method, system, terminal and storage medium. Background Art

[0002] In high-reliability fields such as edge servers and vehicle-mounted controller electronic products, circuit boards are commonly used to form circuits to achieve specific functions of the product. In edge server products, due to the large size of the product, the circuit board is also larger than other products such as mobile phones. Large circuit boards are more sensitive to deformation. Deformation of circuit boards can cause circuit connection failure and damage to electronic components, resulting in reduced product reliability. After the circuit board is welded, each link in production, testing, delivery, and use may cause failure caused by bending and deformation of the circuit board. The detection and response methods for circuit board deformation play an important role in improving product reliability.

[0003] At present, in order to deal with the deformation of circuit boards, strain gauges are mainly used to test the deformation stress of circuit boards to detect the design quality.

[0004] Sticking strain gauges on key positions of circuit boards to detect circuit board stress is only an experimental measure to verify that product designs meet stress requirements, such as product stress when circuit boards are installed on structures. It cannot be used on mass-produced products to constantly detect deformation stress at all stages of the circuit board, such as when the circuit board is transported without power, or when the circuit board is assembled and screwed in, resulting in sudden stress increases that can cause damage to the circuit board. Summary of the invention

[0005] In view of the above-mentioned deficiencies in the prior art, the present invention provides a circuit board deformation detection device to solve the above-mentioned technical problems.

[0006] The present invention provides a circuit board deformation detection device, comprising:

[0007] A capacitor bridge, the capacitor bridge comprising a plurality of capacitors with the same capacitance value; the capacitors are packaged on a circuit board to be tested;

[0008] The capacitor bridge is connected to the input end of the voltage acquisition circuit, the output end of the voltage acquisition circuit is electrically connected to the input end of the analog-to-digital converter, the analog-to-digital converter is used to convert the electrical signal into a binary digital signal, and the output end of the analog-to-digital converter is electrically connected to a signal recorder;

[0009] The capacitor bridge is electrically connected to an AC power source.

[0010] In an optional embodiment, the capacitor bridge comprises:

[0011] A first branch and a second branch are connected in parallel, wherein the first branch includes 2n capacitors connected in series, and the second branch includes 2n capacitors connected in series; wherein n is an integer greater than 0.

[0012] In an optional implementation, the first branch includes a first resistor and a second resistor; 2n capacitors are connected in series between the first resistor and the second resistor.

[0013] In an optional implementation, the second branch includes a third resistor and a fourth resistor, and 2n capacitors are connected in series between the third resistor and the fourth resistor.

[0014] In an optional implementation, the first resistor, the second resistor, the third resistor and the fourth resistor have the same resistance value.

[0015] In an optional embodiment, the first branch includes a first voltage collection point, and the second branch includes a second voltage collection point; the number of upstream capacitors of the first voltage collection point is the same as the number of downstream capacitors; the number of upstream capacitors of the second voltage collection point is the same as the number of downstream capacitors.

[0016] In an optional embodiment, the voltage acquisition circuit includes an operational amplifier; the first input terminal of the operational amplifier is connected to the first voltage acquisition point; the second input terminal of the operational amplifier is connected to the second voltage acquisition point; and the output terminal of the operational amplifier is electrically connected to the input terminal of the analog-to-digital converter.

[0017] In an optional implementation, the signal recorder is a CPU.

[0018] In an optional implementation, the signal recorder is a CPLD, and the CPLD is connected to the BMC via an I2C bus.

[0019] In an optional embodiment, it includes a first capacitor bridge and a second capacitor bridge, wherein the multiple capacitors of the first capacitor bridge are evenly distributed on the edge of the top layer of the circuit board; the multiple capacitors of the second capacitor bridge are evenly distributed on the edge of the bottom layer of the circuit board; the first capacitor bridge is connected to a first voltage acquisition circuit, and the first voltage acquisition circuit is connected to a signal recorder via a first analog-to-digital converter; the second capacitor bridge is connected to a second voltage acquisition circuit, and the second voltage acquisition circuit is connected to a signal recorder via a second analog-to-digital converter.

[0020] The beneficial effect of the present invention is that the circuit board deformation detection device method, system, terminal and storage medium provided by the present invention can record the stress of the circuit board at all times, regardless of whether the power is off. For high-reliability applications, all stress processes experienced by the circuit board after welding can be recorded. Timely reporting of stress risks that the circuit board may be subjected to, timely troubleshooting of design or production defects of circuit board stress, and screening out circuit boards that are over-stressed are of great significance for high-reliability equipment.

[0021] In addition, the invention has a reliable design principle, a simple structure and a very broad application prospect. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0023] Figure 1 The figure is a schematic diagram of the principle of a circuit board deformation detection device according to an embodiment of the present invention.

[0024] Figure 2 It is a schematic structural diagram of a circuit board deformation detection device according to an embodiment of the present invention.

[0025] Figure 3 is another schematic structural diagram of a circuit board deformation detection device according to an embodiment of the present invention.

[0026] Figure 4 It is a workflow diagram of a circuit board deformation detection device in an application scenario according to an embodiment of the present invention.

[0027] Among them, 1. Capacitor; 2. Circuit board. DETAILED DESCRIPTION

[0028] In order to enable those skilled in the art to better understand the technical solutions in the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0029] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used in the specification of the present invention herein are only for the purpose of describing specific embodiments and are not intended to limit the present invention.

[0030] To facilitate understanding of the present invention, the circuit board deformation detection device provided by the present invention is further described below based on the principle of the circuit board deformation detection device of the present invention in combination with embodiments and drawings.

[0031] Specifically, the circuit board deformation detection device includes:

[0032] A capacitance bridge, the capacitance bridge comprises a plurality of capacitors 1 with the same capacitance value; the capacitors 1 are packaged on a circuit board 2 to be tested; the capacitance bridge is connected to the input end of a voltage acquisition circuit, the output end of the voltage acquisition circuit is electrically connected to the input end of an analog-to-digital converter ADC, the analog-to-digital converter ADC is used to convert an electrical signal into a binary digital signal, the output end of the analog-to-digital converter ADC is electrically connected to a signal recorder; the capacitance bridge is electrically connected to an AC power supply U.

[0033] like Figure 1 As shown, a capacitor bridge is formed by capacitor 1, and the capacitance values ​​of C1, C2, C3, and C4 are the same. When an AC signal is added to the upper and lower ends of the capacitor bridge, the voltage at the connection of capacitors C1 and C3 and the connection of C2 and C4 are the same. The two leads are connected to a differential operational amplifier. After the signal is amplified, it enters the ADC for voltage sampling. In theory, because the capacitance values ​​of the capacitors are the same, the sampled voltage is 0 and the capacitance is normal. When the sampled voltage error exceeds the capacitance error range, it is considered that capacitor 1 is faulty, and it is necessary to investigate the cause of the abnormal capacitance value of the capacitor. If a crack occurs, it means that the stress of circuit board 2 exceeds the standard. In this way, the stress abnormality of circuit board 2 is detected.

[0034] When the area of ​​the circuit board 2 is large, multiple capacitors 1 need to be set to improve the detection accuracy. The capacitor bridge includes: a first branch and a second branch connected in parallel, the first branch includes 2n capacitors 1 connected in series, and the second branch includes 2n capacitors 1 connected in series; wherein n is an integer greater than 0.

[0035] In addition, in order to improve the safety of the detection circuit and avoid the adverse consequences caused by the circuit short circuit, the first branch includes a first resistor R1 and a second resistor R2; 2n capacitors 1 are connected in series between the first resistor R1 and the second resistor R2. The second branch includes a third resistor R3 and a fourth resistor R4, and 2n capacitors 1 are connected in series between the third resistor R3 and the fourth resistor R4. The resistance values ​​of the first resistor, the second resistor, the third resistor and the fourth resistor are the same, all of which are 0 ohms. The reason for connecting the 0 ohm resistors in series at both ends is that when the capacitor fails, the circuit board 2 detects the capacitor failure, and it is necessary to locate which position of the capacitor fails, then remove the 0 ohm resistor, so that the capacitor has no relevant connection with other power supplies and ground, so that the reserved test points at both ends of each capacitor are tested with a multimeter, and the failure of the capacitor failure can be easily measured, and then the position where the circuit board 2 is bent the most can be easily determined. If the resistor is not arranged, the capacitor needs to be removed and then tested (because on the circuit board 2, connecting the power supply and ground will interfere with the test), so that in the process of removal, the capacitor may be damaged, resulting in the failure cannot be located (is it a fault caused by the process of removing the capacitor or a fault caused by the bending of the circuit board 2).

[0036] like Figure 2 As shown, a capacitor is rotated in a circle on the edge of the whole circuit board 2 (where the board is deformed the most) to detect the deformation of the circuit board 2, and a test point is reserved in each capacitor series branch, and a protection resistor is set, and the entire circuit structure is symmetrical. That is, the first branch includes a first voltage collection point, and the second branch includes a second voltage collection point; the number of upstream capacitors 1 of the first voltage collection point is the same as the number of downstream capacitors 1; the number of upstream capacitors 1 of the second voltage collection point is the same as the number of downstream capacitors 1. The voltage collection circuit includes an operational amplifier OPA; the first input end of the operational amplifier OPA is connected to the first voltage collection point; the second input end of the operational amplifier OPA is connected to the second voltage collection point; the output end of the operational amplifier OPA is electrically connected to the input end of the analog-to-digital converter ADC. The signal recorder is a CPU.

[0037] like Figure 3 As shown, the circuit board 2 deformation detection device includes a first capacitor bridge and a second capacitor bridge, and multiple capacitors 1 of the first capacitor bridge are evenly distributed on the edge of the top layer of the circuit board 2; multiple capacitors 1 of the second capacitor bridge are evenly distributed on the edge of the bottom layer of the circuit board 2; the first capacitor bridge is connected to a first voltage acquisition circuit, and the first voltage acquisition circuit is connected to a signal recorder via a first analog-to-digital converter ADC; the second capacitor bridge is connected to a second voltage acquisition circuit, and the second voltage acquisition circuit is connected to a signal recorder via a second analog-to-digital converter ADC.

[0038] This mirror layout takes into account that ceramic capacitors (MLCC) have weak tensile stress resistance and are more prone to breakage. The upper and lower layers are arranged symmetrically. No matter which direction the circuit board is tilted, the capacitor on one side will be subjected to tensile force, causing the capacitor to fail. This is used to detect circuit board bending.

[0039] In another embodiment, the signal recorder may use a complex programmable logic device (CPLD), which is connected to the BMC via an I2C bus. The CPLD can process and record data signals and report the detection data to the BMC, which uses an independent power supply to improve data security.

[0040] Please refer to Figure 4 In one implementation, capacitor C can be uniformly 1206 package 1uF capacitor, and the resistor is selected as 0 ohm. First, a sine wave 10K Hz signal source is used, the sine wave peak voltage is 3V3, and the differential op amp gain is 1. When the circuit board is working normally, since the upper and lower capacitors have the same voltage division, the differential op amp output is 0V, and the differential voltage sampled by the ADC is 0V.

[0041] When a capacitor is short-circuited due to the bending of the board, assuming it is C1, then:

[0042] The upper capacitor voltage division (sine wave peak voltage) is: 3.3V / (5 / 11)=1.5V, the lower capacitor voltage division (sine wave peak voltage) is: 3.3V / (5 / 12)=1.65V, the sine wave peak voltage difference is: 1.65-1.5=0.15V, then the ADC can detect a sine wave with an amplitude of 0.15V.

[0043] When a capacitor is disconnected due to board bending, assuming it is C1, then:

[0044] The above capacitor voltage division (peak voltage of the sine wave) is: 3.3V. Similarly, a sine wave with an amplitude of 1.65V can be detected by the ADC.

[0045] The power supply provides a 10KHz sine wave, and the CPU obtains the differential voltage collected by the ADC. The CPU determines whether the differential voltage is greater than 0.1V. If the differential voltage is not greater than 0.1V, the CPU continues to sample and judge. If the differential voltage is greater than 0.1V, it is determined that the circuit board is under stress, and the log is recorded and the alarm indicator light is turned on. After the operator sees that the indicator light is on, he will repair the circuit board, remove the head and tail resistors, and test the capacitance of each capacitor to find the capacitor of the short circuit or circuit. The position of the short-circuited or open-circuited capacitor is the stress position of the circuit board. By analyzing the possible stress conditions at the stress position, the circuit board can be improved to avoid stress again.

[0046] Although the present invention has been described in detail with reference to the accompanying drawings and in combination with the preferred embodiments, the present invention is not limited thereto. Without departing from the spirit and essence of the present invention, a person of ordinary skill in the art may make various equivalent modifications or substitutions to the embodiments of the present invention, and these modifications or substitutions shall be within the scope of the present invention. Any person of ordinary skill in the art may easily think of changes or substitutions within the technical scope disclosed by the present invention, and these shall be within the scope of protection of the present invention.

Claims

1. A circuit board deformation detection device, characterized in that: include: A capacitance bridge, the capacitance bridge comprising a plurality of capacitors having the same capacitance value; The capacitor is packaged on a circuit board to be tested; The capacitor bridge is connected to the input end of the voltage acquisition circuit, the output end of the voltage acquisition circuit is electrically connected to the input end of the analog-to-digital converter, the analog-to-digital converter is used to convert the electrical signal into a binary digital signal, and the output end of the analog-to-digital converter is electrically connected to a signal recorder; The capacitor bridge is electrically connected to an AC power source.

2. The circuit board deformation detection device according to claim 1, characterized in that: The capacitor bridge comprises: A first branch and a second branch are connected in parallel, wherein the first branch includes 2n capacitors connected in series, and the second branch includes 2n capacitors connected in series; wherein n is an integer greater than 0.

3. The circuit board deformation detection device according to claim 2, characterized in that: The first branch includes a first resistor and a second resistor; 2n capacitors are connected in series between the first resistor and the second resistor.

4. The circuit board deformation detection device according to claim 3, characterized in that: The second branch includes a third resistor and a fourth resistor, and 2n capacitors are connected in series between the third resistor and the fourth resistor.

5. The circuit board deformation detection device according to claim 4, characterized in that: The first resistor, the second resistor, the third resistor and the fourth resistor have the same resistance value.

6. The circuit board deformation detection device according to claim 2, characterized in that: The first branch includes a first voltage collection point, and the second branch includes a second voltage collection point; the number of upstream capacitors and downstream capacitors of the first voltage collection point is the same; the number of upstream capacitors and downstream capacitors of the second voltage collection point is the same.

7. The circuit board deformation detection device according to claim 6, characterized in that: The voltage collection circuit includes an operational amplifier; a first input end of the operational amplifier is connected to the first voltage collection point; a second input end of the operational amplifier is connected to the second voltage collection point; and an output end of the operational amplifier is electrically connected to an input end of an analog-to-digital converter.

8. The circuit board deformation detection device according to claim 1, characterized in that: The signal recorder is a CPU.

9. The circuit board deformation detection device according to claim 1, characterized in that: The signal recorder is a CPLD, and the CPLD is connected to the BMC via an I2C bus.

10. The circuit board deformation detection device according to claim 1, characterized in that: It includes a first capacitor bridge and a second capacitor bridge, wherein a plurality of capacitors of the first capacitor bridge are evenly distributed on the edge of the top layer of the circuit board; The plurality of capacitors of the second capacitance bridge are evenly distributed on the edge of the bottom layer of the circuit board; The first capacitor bridge is connected to a first voltage acquisition circuit, which is connected to a signal recorder via a first analog-to-digital converter; the second capacitor bridge is connected to a second voltage acquisition circuit, which is connected to a signal recorder via a second analog-to-digital converter.

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