Three-level bidirectional buck-boost circuit

Abstract

The utility model relates to the technical field of power supply circuits, in particular to a three-level bidirectional buck-boost circuit. One end of the current-limiting resistor R1 and one end of the input capacitor C1 are both connected with a power supply input end, the other end of the current-limiting resistor R1 is connected with one end of the switching device S1, and the other end of the switching device S1 is connected with a source electrode of the switching tube Q1. According to the circuit, the current-limiting resistor R1 and the switch device S1 are connected to the front end of the flying capacitor C2, and the current-limiting resistor R1 is used as a pre-charging device of the flying capacitor C2 and can be connected to the circuit through the switch device S1 to realize pre-charging when a power supply is turned on. Therefore, the voltage of the flying capacitor can be effectively controlled when the power supply is started, namely, the voltage-sharing control of the flying capacitor is realized, the damage of the MOS tube is avoided, and the reliability of the power supply is improved.

Description

Technical Field

[0001] This utility model relates to the field of power supply circuit technology, specifically to a three-level bidirectional buck-boost circuit. Background Technology

[0002] With the development of new energy technologies, especially driven by the electric vehicle sector, the demand for bidirectional test power supplies with high-voltage output is constantly increasing. In fields such as DC power conversion, power control, and energy consumption, three-level DC-DC converters are widely used when the DC bus voltage is high, effectively solving the technical difficulties of high-voltage DC input. Among them, the flying capacitor three-level bidirectional buck-boost circuit has been widely used in scenarios with high DC input voltage and a wide range of output voltage.

[0003] The circuit diagram of the existing three-level bidirectional buck-boost circuit is as follows: Figure 1 As shown, the three-level bidirectional buck-boost circuit has the following characteristics:

[0004] Ideally, the voltage across the flying capacitor C2 is half the input voltage Vin, and the drain-source voltage (DS) of the MOSFETs (Q1-Q4) is also half the input voltage Vin. This characteristic leads to the use of three-level bidirectional buck-boost circuits in high-voltage input applications, allowing for the selection of lower MOSFET voltages and reducing costs. However, since the voltage distribution across the flying capacitor directly affects the circuit's reliability, voltage equalization control of the flying capacitor in a three-level bidirectional buck-boost circuit is crucial.

[0005] Existing three-level bidirectional buck-boost circuits cannot achieve voltage equalization control of flying capacitors. Therefore, developing a three-level bidirectional buck-boost circuit that can achieve voltage equalization control of flying capacitors is a technical problem that urgently needs to be solved in this field. Utility Model Content

[0006] The purpose of this invention is to address the shortcomings of existing technologies by providing a three-level bidirectional buck-boost circuit. By controlling the connection of the current-limiting resistor R1 through the switching device S1, the voltage of the flying capacitor can be effectively controlled when the power supply is turned on, thus achieving voltage equalization control of the flying capacitor and avoiding damage to the MOSFET.

[0007] This utility model discloses a three-level bidirectional buck-boost circuit, comprising switching transistors Q1, Q2, Q3, and Q4, an inductor L1, an input capacitor C1, an output capacitor C3, a current-limiting resistor R1, a switching device S1, and a flying capacitor C2. The drain of the switching transistor Q1, one end of the current-limiting resistor R1, and one end of the input capacitor C1 are all connected to the power input terminal. The other end of the current-limiting resistor R1 is connected to one end of the switching device S1. One end of the input capacitor is connected to the source of the switching transistor Q1, the drain of the switching transistor Q2, and one end of the flying capacitor C2. The other end of the flying capacitor C2 is connected to the source of the switching transistor Q3 and the drain of the switching transistor Q4. The source of the switching transistor Q2 and the drain of the switching transistor Q3 are connected to one end of the inductor L1. The other end of the inductor L1 and one end of the output capacitor C3 are connected to the power supply output terminal. The other end of the input capacitor C1, the source of the switching transistor Q4, and the other end of the output capacitor C3 are all connected to the power supply common ground.

[0008] Preferably, the current-limiting resistor R1 is an adjustable resistor.

[0009] More preferably, it also includes a first voltage sampling circuit for acquiring the voltage of the flying capacitor C2 and a second voltage sampling circuit for acquiring the voltage at the power input terminal.

[0010] Preferably, the first voltage sampling circuit is a differential sampling circuit.

[0011] Preferably, the first voltage sampling circuit includes resistors R1 to R10 and a first operational amplifier X1. One end of resistor R1 is connected to one end of the flying capacitor C2, the other end of resistor R1 is connected to one end of resistor R2, the other end of resistor R2 is connected to one end of resistor R3, the other end of resistor R3 is connected to one end of resistor R4, the other end of resistor R4 is connected to the non-inverting input terminal of the first operational amplifier X1, one end of resistor R5 is connected to the other end of the flying capacitor C2, and the other end of resistor R5 is connected to the other end of resistor R6. One end of resistor R6 is connected to one end of resistor R7, the other end of resistor R7 is connected to one end of resistor R8, the other end of resistor R8 is connected to the inverting input of the first operational amplifier X1, the non-inverting output of the first operational amplifier X1 is connected to one end of resistor R9, the other end of resistor R9 is the first differential signal output of the first voltage sampling circuit, the inverting output of the first operational amplifier X1 is connected to one end of resistor R10, and the other end of resistor R10 is the second differential signal output of the first voltage sampling circuit.

[0012] Preferably, the second voltage sampling circuit is a single-ended sampling circuit.

[0013] Preferably, the second voltage sampling circuit includes resistors R12, R15-R19, R21, and a second operational amplifier X2. The power input terminal is connected to one end of resistor R19, the other end of resistor R19 is connected to one end of resistor R18, the other end of resistor R18 is connected to one end of resistor R16, the other end of resistor R16 is connected to one end of resistor R15, the other end of resistor R15 is connected to one end of resistor R21 and the non-inverting input terminal of the second operational amplifier X2, the other end of resistor R21 is grounded, the inverting input terminal of the second operational amplifier X2 is connected to one end of resistor R12, the other end of resistor R12 is connected to the output terminal of the second operational amplifier X2, the output terminal of the second operational amplifier X2 is connected to one end of resistor R17, and the other end of resistor R17 is the sampling signal output terminal of the second voltage sampling circuit.

[0014] Preferably, the switching device S1 is an electrically driven switch, which is any one of a MOSFET, a transistor, or a relay.

[0015] More preferably, it also includes a comparator circuit for controlling the switching device S1 to turn off.

[0016] Preferably, the comparator circuit includes a third operational amplifier X2, resistors R30 and R31. The output of the first voltage sampling circuit is connected to the inverting input of the third operational amplifier X2, the output of the second voltage sampling circuit is connected to the non-inverting input of the third operational amplifier X2, the output of the third operational amplifier X2 is connected to one end of resistor R30, the other end of resistor R30 is connected to the control signal input of the switching device S1, one end of resistor R31 is connected to the other end of resistor R30, and the other end is connected to the positive power input of the third operational amplifier X2.

[0017] The beneficial effects of this invention are as follows: This circuit connects a current-limiting resistor R1 and a switching device S1 to the front end of the flying capacitor C2. The current-limiting resistor R1 acts as a pre-charging device for the flying capacitor C2, and can be connected to the circuit via the switching device S1 when the power is turned on to achieve pre-charging. This allows for effective control of the flying capacitor voltage when the power is turned on, thus achieving voltage equalization control of the flying capacitor, avoiding damage to the MOSFET, and improving the reliability of the power supply. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of an existing three-level bidirectional buck-boost circuit;

[0019] Figure 2 This is a schematic diagram of the three-level bidirectional buck-boost circuit provided in this embodiment;

[0020] Figure 3 This is a schematic diagram of the first sampling circuit provided in this embodiment;

[0021] Figure 4 This is a schematic diagram of the second voltage sampling circuit provided in this embodiment;

[0022] Figure 5 This is a schematic diagram of the comparator circuit provided in this embodiment. Detailed Implementation

[0023] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0024] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0025] References to "one embodiment" or "some embodiments" in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized. "A plurality" means "two or more."

[0026] Example 1

[0027] Figure 2 A schematic diagram of a three-level bidirectional buck-boost circuit according to a preferred embodiment of this application is shown. For ease of explanation, only the parts relevant to this embodiment are shown, and the details are as follows:

[0028] It includes switching transistors Q1, Q2, Q3, and Q4, an inductor L1, an input capacitor C1, an output capacitor C3, a current-limiting resistor R1, a switching device S1, and a flying capacitor C2. The drain of the switching transistor Q1, one end of the current-limiting resistor R1, and one end of the input capacitor C1 are all connected to the power input terminal. The other end of the current-limiting resistor R1 is connected to one end of the switching device S1. The other end of the switching device S1 is connected to the source of the switching transistor Q1, the drain of the switching transistor Q2, and one end of the flying capacitor C2. The other end of the flying capacitor C2 is connected to the source of the switching transistor Q3 and the drain of the switching transistor Q4. The source of the switching transistor Q2 and the drain of the switching transistor Q3 are connected to one end of the inductor L1. The other end of the inductor L1 and one end of the output capacitor C3 are connected to the power output terminal. The other end of the input capacitor C1, the source of the switching transistor Q4, and the other end of the output capacitor C3 are all connected to the power ground.

[0029] In one embodiment, the current-limiting resistor R1 is an adjustable resistor.

[0030] In one embodiment, the switching device S1 is a manual switch.

[0031] In application, after a high-voltage DC current is applied to the power input terminal Vin (i.e., when the power is turned on), the switching device S1 is in the open state, allowing the switching transistors Q1 to Q4 to remain in the open state. After a period of time, the switching device S1 is closed, connecting the current-limiting resistor R1 to the circuit to pre-charge the flying capacitor C2. After another period of time, the switching device S1 is opened, removing the current-limiting resistor R1 from the circuit. Then, the switching transistors Q1 to Q4 can operate normally. The duration of each stage can be set or determined based on experience. To achieve automatic control of the switching device S1, a delay control circuit can be integrated into the circuit provided in this embodiment to work with a relay for automatic control. Since the delay control circuit is a mature technology in this field, any circuit capable of achieving delay control can be used in this solution to control the connection of the current-limiting resistor R1 or the turn-off control of the switching transistors Q1 to Q4.

[0032] In this embodiment, a current-limiting resistor R1 and a switching device S1 are connected to the front end of the flying capacitor C2. The current-limiting resistor R1 acts as a pre-charging device for the flying capacitor C2, and can be connected to the circuit through the switching device S1 when the power is turned on to achieve pre-charging. This enables effective control of the flying capacitor voltage when the power is turned on, thus achieving voltage equalization control of the flying capacitor, avoiding damage to the MOSFET, and improving the reliability of the power supply.

[0033] In one embodiment, the input voltage Vbus and the voltage Vc of the flying capacitor C2 can also be obtained through a sampling circuit. By accurately monitoring the magnitudes of these two voltages, and combining them with a comparator circuit, automatic control of the switching device S1 can be achieved. Compared with the delay control circuit proposed in the previous embodiment, this embodiment can achieve a more accurate timing for the current-limiting resistor R1 to be applied, thus having higher reliability. When the comparator circuit drives the switching device S1 to turn off, the switching device S1 can be any one of a MOSFET, a transistor, or a relay.

[0034] like Figure 3 As shown, in one embodiment, the first voltage sampling circuit is a differential sampling circuit. The first voltage sampling circuit includes resistors R1 to R10 and a first operational amplifier X1. One end of resistor R1 is connected to one end of the flying capacitor C2, the other end of resistor R1 is connected to one end of resistor R2, the other end of resistor R2 is connected to one end of resistor R3, the other end of resistor R3 is connected to one end of resistor R4, the other end of resistor R4 is connected to the non-inverting input terminal of the first operational amplifier X1, one end of resistor R5 is connected to the other end of the flying capacitor C2, and the other end of resistor R5 is connected to one end of resistor R6. The other end of resistor R6 is connected to one end of resistor R7, the other end of resistor R7 is connected to one end of resistor R8, the other end of resistor R8 is connected to the inverting input of the first operational amplifier X1, the non-inverting output of the first operational amplifier X1 is connected to one end of resistor R9, the other end of resistor R9 is the first differential signal output of the first voltage sampling circuit, the inverting output of the first operational amplifier X1 is connected to one end of resistor R10, and the other end of resistor R10 is the second differential signal output of the first voltage sampling circuit.

[0035] like Figure 4 As shown, in one embodiment, the second voltage sampling circuit is a single-ended sampling circuit. The second voltage sampling circuit includes resistors R12, R15-R19, R21, and a second operational amplifier X2. The power input terminal is connected to one end of resistor R19. The other end of resistor R19 is connected to one end of resistor R18. The other end of resistor R18 is connected to one end of resistor R16. The other end of resistor R16 is connected to one end of resistor R15. The other end of resistor R15 is connected to one end of resistor R21 and the non-inverting input terminal of the second operational amplifier X2. The other end of resistor R21 is grounded. The inverting input terminal of the second operational amplifier X2 is connected to one end of resistor R12. The other end of resistor R12 is connected to the output terminal of the second operational amplifier X2. The output terminal of the second operational amplifier X2 is connected to one end of resistor R17. The other end of resistor R17 is the sampling signal output terminal of the second voltage sampling circuit.

[0036] like Figure 5 As shown, in one embodiment, the comparator circuit includes a third operational amplifier X2, resistors R30 and R31. The output terminal of the first voltage sampling circuit is connected to the inverting input terminal of the third operational amplifier X2, the output terminal of the second voltage sampling circuit is connected to the non-inverting input terminal of the third operational amplifier X2, the output terminal of the third operational amplifier X2 is connected to one end of the resistor R30, the other end of the resistor R30 is connected to the control signal input terminal of the switching device S1, one end of the resistor R31 is connected to the other end of the resistor R30, and the other end is connected to the positive power input terminal of the third operational amplifier X2.

[0037] In applications, voltage sampling can be achieved using the two sampling circuits described above, thereby enabling monitoring of the input voltage and the voltage across the flying capacitor C2. This allows for more accurate control of the closing timing of the switching device S1, further improving the reliability of the circuit. The specific working principle is as follows:

[0038] When the device is powered on, the sampled Vbus voltage is greater than the VC voltage, so the comparator outputs a high level, meaning the S1 control signal is high. This, in turn, controls the conduction of S1, which charges capacitor C2. When the voltage of capacitor C2 reaches the set value, the sampled VC voltage becomes higher than the Vbus voltage, so the comparator outputs a low level, meaning the S1 control signal is low. This, in turn, instructs the S1 control signal to turn off S1. By setting the sampling signals Vbus and VC, the voltage of capacitor C2 can be flexibly controlled.

[0039] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A three-level bidirectional buck-boost circuit, characterized in that: The invention comprises a switch tube Q1, a switch tube Q2, a switch tube Q3, a switch tube Q4, an inductor L1, an input capacitor C1, an output capacitor C3, a current limiting resistor R1, a switch device S1 and a flying capacitor C2. The drain of the switch tube Q1, one end of the current limiting resistor R1 and one end of the input capacitor C1 are all connected to the power input end, the other end of the current limiting resistor R1 is connected to one end of the switch device S1, the other end of the switch device S1 is connected to the source of the switch tube Q1, the drain of the switch tube Q2 and one end of the flying capacitor C2, the other end of the flying capacitor C2 is connected to the source of the switch tube Q3 and the drain of the switch tube Q4, the source of the switch tube Q2 and the drain of the switch tube Q3 are connected to one end of the inductor L1, the other end of the inductor L1 and one end of the output capacitor C3 are connected to the power output end, and the other end of the input capacitor C1, the source of the switch tube Q4 and the other end of the output capacitor C3 are all commonly connected to the power supply.

2. The three-level bidirectional buck-boost circuit according to claim 1, characterized in that: The current limiting resistor R1 is an adjustable resistor.

3. The three-level bidirectional buck-boost circuit according to claim 1, characterized in that: It also includes a first voltage sampling circuit for sampling the voltage of the flying capacitor C2 and a second voltage sampling circuit for sampling the voltage of the power input terminal.

4. The three-level bidirectional buck-boost circuit according to claim 3, characterized in that: The first voltage sampling circuit is a differential sampling circuit.

5. The three-level bidirectional buck-boost circuit according to claim 3, characterized in that: The first voltage sampling circuit includes resistors R1 to R10 and a first operational amplifier X1, one end of the resistor R1 is connected to one end of the flying capacitor C2, the other end of the resistor R1 is connected to one end of the resistor R2, the other end of the resistor R2 is connected to one end of the resistor R3, the other end of the resistor R3 is connected to one end of the resistor R4, the other end of the resistor R4 is connected to the non-inverting input terminal of the first operational amplifier X1, one end of the resistor R5 is connected to the other end of the flying capacitor C2, and the other end of the resistor R5 is connected to one end of the resistor R6. The other end of the resistor R6 is connected to one end of the resistor R7, the other end of the resistor R7 is connected to one end of the resistor R8, the other end of the resistor R8 is connected to the inverting input end of the first operational amplifier X1, the non-inverting output end of the first operational amplifier X1 is connected to one end of the resistor R9, the other end of the resistor R9 is the first differential signal output end of the first voltage sampling circuit, the inverting output end of the first operational amplifier X1 is connected to one end of the resistor R10, and the other end of the resistor R10 is the second differential signal output end of the first voltage sampling circuit.

6. The three-level bidirectional buck-boost circuit according to claim 3, characterized in that: The second voltage sampling circuit is a single-ended sampling circuit.

7. The three-level bidirectional buck-boost circuit according to claim 3, characterized in that: The second voltage sampling circuit includes resistors R12, R15-R19, R21 and a second operational amplifier X2, wherein the power input terminal is connected to one end of the resistor R19, the other end of the resistor R19 is connected to one end of the resistor R18, the other end of the resistor R18 is connected to one end of the resistor R16, the other end of the resistor R16 is connected to one end of the resistor R15, the other end of the resistor R15 is connected to one end of the resistor R21 and the non-inverting input terminal of the second operational amplifier X2, the other end of the resistor R21 is grounded, the inverting input terminal of the second operational amplifier X2 is connected to one end of the resistor R12, the other end of the resistor R12 is connected to the output terminal of the second operational amplifier X2, the output terminal of the second operational amplifier X2 is connected to one end of the resistor R17, and the other end of the resistor R17 is the sampling signal output terminal of the second voltage sampling circuit.

8. The three-level bidirectional buck-boost circuit according to claim 1, characterized in that: The switch device S1 is an electrically driven switch, and the electrically driven switch is any one of a MOS tube, a triode, and a relay.

9. The three-level bidirectional buck-boost circuit according to claim 3, characterized in that: A comparator circuit is also included for controlling the switch device S1 to be turned off.

10. The three-level bidirectional buck-boost circuit according to claim 9, characterized in that: The comparator circuit includes a third operational amplifier X2, a resistor R30 and a resistor R31, the output end of the first voltage sampling circuit is connected to the inverting input end of the third operational amplifier X2, the output end of the second voltage sampling circuit is connected to the non-inverting input end of the third operational amplifier X2, the output end of the third operational amplifier X2 is connected to one end of the resistor R30, the other end of the resistor R30 is connected to the control signal input end of the switch device S1, one end of the resistor R31 is connected to the other end of the resistor R30, and the other end is connected to the positive power input end of the third operational amplifier X2.

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