Downclocking circuit and frequency demultiplier

Abstract

The utility model belongs to the field of microwave communication, and provides a down-conversion circuit and a down-conversion device, and the down-conversion circuit comprises a vertical antenna and a horizontal antenna. The frequency reduction circuit further comprises a first signal amplification circuit connected with the vertical antenna, a second signal amplification circuit connected with the horizontal antenna, an intermediate frequency signal processing circuit, an oscillation circuit, a first output circuit and a second output circuit. The output end of the first signal amplification circuit is connected with the first receiving end of the intermediate frequency signal processing circuit, and the output end of the second signal amplification circuit is connected with the second receiving end of the intermediate frequency signal processing circuit, so that a first input circuit is formed; the output end of the oscillating circuit is connected with the third receiving end of the intermediate frequency signal processing circuit to form a second input circuit; and the intermediate frequency signal processing circuit is respectively connected with the first output circuit and the second output circuit to form a signal output circuit. The performance of the down-conversion circuit is improved, and the cost of the down-conversion circuit is reduced.

Description

Technical Field

[0001] The utility model belongs to the field of microwave communication, and in particular relates to a frequency reduction circuit and a frequency reducer. Background Art

[0002] Downconversion in RF signals refers to the process of converting RF signals originally located in the high frequency band into intermediate frequency signals or baseband signals of lower frequencies through specific circuits or equipment. Through downconversion, high-frequency signals that were originally difficult to process directly can be converted into intermediate frequency signals that are easier to analyze and process, thereby significantly reducing the complexity of signal processing and meeting the needs of various communication and detection applications.

[0003] However, the existing frequency reduction circuit can only process the radio frequency signal of a specific antenna, and its performance is insufficient to meet the communication needs of users. Therefore, a new frequency reduction circuit is urgently needed. Utility Model Content

[0004] The utility model provides a frequency reduction circuit, aiming to solve the problem of insufficient performance of the existing frequency reduction circuit.

[0005] In order to solve the above technical problems, the utility model is achieved as follows:

[0006] A frequency reduction circuit, comprising a vertical antenna and a horizontal antenna, the frequency reduction circuit further comprising: a first signal amplifying circuit connected to the vertical antenna, a second signal amplifying circuit connected to the horizontal antenna, an intermediate frequency signal processing circuit, an oscillating circuit, a first output circuit and a second output circuit;

[0007] The output end of the first signal amplifying circuit is connected to the first receiving end of the intermediate frequency signal processing circuit, and the output end of the second signal amplifying circuit is connected to the second receiving end of the intermediate frequency signal processing circuit, forming a first input circuit;

[0008] The output end of the oscillation circuit is connected to the third receiving end of the intermediate frequency signal processing circuit to form a second input circuit;

[0009] The intermediate frequency signal processing circuit is respectively connected to the first output circuit and the second output circuit to form a signal output circuit.

[0010] Further, in the frequency reduction circuit, the first signal amplification circuit includes a PNP transistor Q1, a resistor R1, a resistor R2, a capacitor C1, a capacitor C2, a capacitor C3, and a first power supply;

[0011] The base of the PNP transistor Q1 is connected to the vertical antenna and the first end of the resistor R1 respectively, the second end of the resistor R1 and the first end of the capacitor C4 are connected to the negative electrode of the first power supply respectively, and the second end of the capacitor C4 is grounded;

[0012] The first end of R2 and the first end of the capacitor C2 are respectively connected to the positive electrode of the first power supply, and the second end of the capacitor C2 is grounded;

[0013] The second end of R2 and the first end of C3 are respectively connected to the emitter of the PNP transistor Q1 , the collector of the PNP transistor Q1 is grounded, and the second end of C3 is the output end of the first signal amplifying circuit.

[0014] Further, in the frequency reduction circuit, the second signal amplification circuit includes a PNP transistor Q2, a resistor R3, a resistor R4, a capacitor C4, a capacitor C5, and a capacitor C6;

[0015] The base of the PNP transistor Q2 is connected to the horizontal antenna and the first end of the resistor R3 respectively, the second end of the resistor R3 and the first end of the capacitor C4 are connected to the low level end of the intermediate frequency signal processing circuit respectively, and the second end of the capacitor C4 is grounded;

[0016] The first end of R4 and the first end of the capacitor C5 are respectively connected to the high level end of the intermediate frequency signal processing circuit, and the second end of the capacitor C5 is grounded;

[0017] The second end of R4 and the first end of C6 are respectively connected to the emitter of the PNP transistor Q2, the collector of the PNP transistor Q2 is grounded, and the second end of C6 is the output end of the second signal amplifying circuit.

[0018] Further, in the frequency reduction circuit, the intermediate frequency signal processing circuit includes a mixer U1, a resistor R5, a resistor R6, and a second power supply;

[0019] The first end of the resistor R5 and the first end of the resistor R6 are connected to the mixer U1 respectively, and the second end of the resistor R5 and the second end of the resistor R6 are grounded respectively;

[0020] The power pin of the mixer U1 is connected to the positive electrode of the second power supply, the negative electrode pin of the mixer U1 is connected to the negative electrode of the second power supply, and the ground pin of the mixer U1 is grounded.

[0021] The first pin of the mixer U1 is the first receiving end of the intermediate frequency signal processing circuit, the second pin of the mixer U1 is the second receiving end of the intermediate frequency signal processing circuit, and the third pin of the mixer U1 is the third receiving end of the intermediate frequency signal processing circuit.

[0022] Furthermore, in the frequency reduction circuit, the oscillation circuit includes an oscillator U2 and a capacitor C13, a first end of the capacitor C13 is connected to the intermediate frequency signal processing circuit and the output end of the oscillator U2, a second end of the capacitor C13 is grounded, and the output end of the oscillator U2 is the output end of the oscillation circuit.

[0023] Furthermore, in the frequency reduction circuit, the oscillator U2 is a local oscillator or a crystal oscillator.

[0024] Further, in the frequency reduction circuit, the first output circuit includes a resistor R7, a resistor R8, a resistor R9, a capacitor C7, a capacitor C8, a capacitor C9, a capacitor C10, a capacitor C11, a capacitor C12, a voltage regulator U3, an intermediate frequency signal filter F1, and a first output terminal O1;

[0025] The first end of the resistor R7 is connected to the intermediate frequency signal processing circuit, the second end of the resistor R7 is respectively connected to the first end of the capacitor C9, the first end of the resistor R8, the first end of the capacitor C10 and the first end of R9, the second end of the capacitor C9 and the second end of the resistor R8 are respectively grounded, and the second end of the capacitor C10 and the second end of R9 are respectively connected to the input end of the intermediate frequency signal filter F1;

[0026] Pin 1 of the voltage stabilizer U3 is respectively connected to the intermediate frequency signal processing circuit and the first end of the capacitor C11, pin 2 of the voltage stabilizer U3 and the second end of the capacitor C11 are respectively grounded, pin 3 of the voltage stabilizer U3 and the first end of the capacitor C12 are respectively connected to the input end of the intermediate frequency signal filter F1, and the second end of the capacitor C12 is grounded;

[0027] The first end of the capacitor C7 is connected to the intermediate frequency signal processing circuit, the second end of the capacitor C7 and the output end of the intermediate frequency signal filter F1 are respectively connected to the input end of the first output terminal O1, and the output end of the first output terminal O1 is the output end of the first output circuit.

[0028] Further, in the frequency reduction circuit, the second output circuit includes a resistor R10, a resistor R11, a resistor R12, a capacitor C13, a capacitor C14, a capacitor C15, a capacitor C16, a capacitor C17, a capacitor C18, a capacitor C19, a voltage stabilizer U4, an intermediate frequency signal filter F2, and a second output terminal O2;

[0029] The first end of the resistor R12 is connected to the intermediate frequency signal processing circuit, and the second end of the resistor R12 is respectively connected to the first end of the capacitor C15, the first end of the resistor R10, the first end of the capacitor C16 and the first end of R11;

[0030] The second end of the capacitor C15 and the second end of the resistor R10 are grounded respectively, and the second end of the capacitor C16 and the second end of R11 are connected to the input end of the intermediate frequency signal filter F2 respectively;

[0031] Pin 1 of the voltage stabilizer U4 is respectively connected to the intermediate frequency signal processing circuit and the first end of the capacitor C18, pin 2 of the voltage stabilizer U4 and the second end of the capacitor C18 are respectively grounded, pin 3 of the voltage stabilizer U4 and the first end of the capacitor C19 are respectively connected to the input end of the intermediate frequency signal filter F2, and the second end of the capacitor C19 is grounded;

[0032] The first end of the capacitor C17 is connected to the intermediate frequency signal processing circuit, the second end of the capacitor C17 and the output end of the intermediate frequency signal filter F2 are respectively connected to the input end of the second output terminal O2, and the output end of the second output terminal O2 is the output end of the second output circuit.

[0033] Furthermore, in the frequency reduction circuit, the intermediate frequency signal filter F2 is a bandpass filter or a ceramic filter.

[0034] Another object of the present invention is to provide a frequency reducer, comprising the frequency reduction circuit mentioned above.

[0035] In the utility model, since the frequency reduction circuit includes a first signal amplifying circuit connected to the vertical antenna and a second signal amplifying circuit connected to the horizontal antenna, it can process the RF signals of the vertical antenna and the horizontal antenna, thereby improving the performance of the frequency reduction circuit in processing RF signals. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 This utility model Embodiment 1 A structural block diagram of a frequency reduction circuit is provided;

[0037] Figure 2 This utility model Embodiment 2 A circuit structure diagram of a frequency reduction circuit is provided. DETAILED DESCRIPTION

[0038] In order to make the purpose, technical solution and advantages of the utility model more clear, the utility model is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the utility model and are not used to limit the utility model.

[0039] Embodiment 1

[0040] refer to Figure 1 , Figure 1This is a structural block diagram of a frequency reduction circuit provided in Example 1. For the sake of convenience, only the parts related to the embodiment of the utility model are listed, which are described in detail as follows:

[0041] A frequency reduction circuit, comprising a vertical antenna and a horizontal antenna, the frequency reduction circuit further comprising: a first signal amplifying circuit 1 connected to the vertical antenna, a first signal amplifying circuit 2 connected to the horizontal antenna, an intermediate frequency signal processing circuit 3, an oscillating circuit 4, a first output circuit 5 and a second output circuit 6;

[0042] The output end of the first signal amplifying circuit 1 is connected to the first receiving end of the intermediate frequency signal processing circuit 3, and the output end of the first signal amplifying circuit 2 is connected to the second receiving end of the intermediate frequency signal processing circuit 3, forming a first input circuit;

[0043] The output end of the oscillator circuit 4 is connected to the third receiving end of the intermediate frequency signal processing circuit 3 to form a second input circuit;

[0044] The intermediate frequency signal processing circuit 3 is respectively connected to the first output circuit 5 and the second output circuit 6 to form a signal output circuit.

[0045] The working principle of a frequency reduction circuit is described below, as detailed below:

[0046] In wireless communication systems, RF reception is a key link in information transmission. Vertical and horizontal antennas are used to capture RF signals from radio waves in the air. Vertical antennas can maximize the concentration and capture of vertically polarized RF signals, while horizontal antennas can capture horizontally polarized signals or RF signals from multiple directions. These RF signals carry information, but their frequencies are usually extremely high, sometimes ranging from hundreds of megahertz to tens of gigahertz.

[0047] Since the received RF signal is often very weak, the first signal amplification circuit 1 is required to amplify the RF signal of the vertical antenna, and the first signal amplification circuit 2 is required to amplify the RF signal of the horizontal antenna, and enhance these RF signals to sufficient strength so that the subsequent intermediate frequency signal processing circuit 3 can accurately parse and extract information. The first signal amplification circuit 1 and the first signal amplification circuit 2 not only enhance the amplitude of the RF signal, but also ensure the integrity of the RF signal, providing a solid foundation for subsequent signal processing.

[0048] The intermediate frequency signal processing circuit 3 further processes the amplified radio frequency signal by first converting the radio frequency signal into an intermediate frequency signal, which is a relatively low frequency signal and is easy to process and analyze later.

[0049] In the utility model, since the frequency reduction circuit includes a first signal amplifying circuit 1 connected to the vertical antenna and a first signal amplifying circuit 2 connected to the horizontal antenna, it can process the RF signals of the vertical antenna and the horizontal antenna, thereby improving the performance of the frequency reduction circuit in processing RF signals.

[0050] Embodiment 2

[0051] The implementation of this embodiment is based on the first embodiment. Figure 2 , Figure 2 It is a circuit structure diagram of a frequency reduction circuit, which is described in detail as follows:

[0052] The first signal amplifying circuit includes a PNP transistor Q1, a resistor R1, a resistor R2, a capacitor C1, a capacitor C2, a capacitor C3, and a first power supply;

[0053] The base of the PNP transistor Q1 is connected to the vertical antenna and the first end of the resistor R1 respectively, the second end of the resistor R1 and the first end of the capacitor C4 are connected to the negative electrode of the first power supply respectively, and the second end of the capacitor C4 is grounded;

[0054] The first end of R2 and the first end of the capacitor C2 are respectively connected to the positive electrode of the first power supply, and the second end of the capacitor C2 is grounded;

[0055] The second end of R2 and the first end of C3 are respectively connected to the emitter of the PNP transistor Q1, the collector of the PNP transistor Q1 is grounded, and the second end of C3 is the output end of the first signal amplifying circuit;

[0056] The second signal amplifying circuit includes a PNP transistor Q2, a resistor R3, a resistor R4, a capacitor C4, a capacitor C5, and a capacitor C6;

[0057] The base of the PNP transistor Q2 is connected to the horizontal antenna and the first end of the resistor R3 respectively, the second end of the resistor R3 and the first end of the capacitor C4 are connected to the low level end of the intermediate frequency signal processing circuit respectively, and the second end of the capacitor C4 is grounded;

[0058] The first end of R4 and the first end of the capacitor C5 are respectively connected to the high level end of the intermediate frequency signal processing circuit, and the second end of the capacitor C5 is grounded;

[0059] The second end of R4 and the first end of C6 are respectively connected to the emitter of the PNP transistor Q2, the collector of the PNP transistor Q2 is grounded, and the second end of C6 is the output end of the second signal amplifying circuit;

[0060] The intermediate frequency signal processing circuit includes a mixer U1, a resistor R5, a resistor R6, and a second power supply;

[0061] The first end of the resistor R5 and the first end of the resistor R6 are connected to the mixer U1 respectively, and the second end of the resistor R5 and the second end of the resistor R6 are grounded respectively;

[0062] The power pin of the mixer U1 is connected to the positive electrode of the second power supply, the negative electrode pin of the mixer U1 is connected to the negative electrode of the second power supply, and the ground pin of the mixer U1 is grounded.

[0063] The first pin of the mixer U1 is the first receiving end of the intermediate frequency signal processing circuit, the second pin of the mixer U1 is the second receiving end of the intermediate frequency signal processing circuit, and the third pin of the mixer U1 is the third receiving end of the intermediate frequency signal processing circuit.

[0064] The oscillation circuit includes an oscillator U2 and a capacitor C13. The first end of the capacitor C13 is connected to the intermediate frequency signal processing circuit and the output end of the oscillator U2. The second end of the capacitor C13 is grounded. The output end of the oscillator U2 is the output end of the oscillation circuit.

[0065] The first output circuit includes a resistor R7, a resistor R8, a resistor R9, a capacitor C7, a capacitor C8, a capacitor C9, a capacitor C10, a capacitor C11, a capacitor C12, a voltage stabilizer U3, an intermediate frequency signal filter F1, and a first output terminal O1;

[0066] The first end of the resistor R7 is connected to the intermediate frequency signal processing circuit, the second end of the resistor R7 is respectively connected to the first end of the capacitor C9, the first end of the resistor R8, the first end of the capacitor C10 and the first end of R9, the second end of the capacitor C9 and the second end of the resistor R8 are respectively grounded, and the second end of the capacitor C10 and the second end of R9 are respectively connected to the input end of the intermediate frequency signal filter F1;

[0067] Pin 1 of the voltage stabilizer U3 is respectively connected to the intermediate frequency signal processing circuit and the first end of the capacitor C11, pin 2 of the voltage stabilizer U3 and the second end of the capacitor C11 are respectively grounded, pin 3 of the voltage stabilizer U3 and the first end of the capacitor C12 are respectively connected to the input end of the intermediate frequency signal filter F1, and the second end of the capacitor C12 is grounded;

[0068] The first end of the capacitor C7 is connected to the intermediate frequency signal processing circuit, the second end of the capacitor C7 and the output end of the intermediate frequency signal filter F1 are respectively connected to the input end of the first output terminal O1, and the output end of the first output terminal O1 is the output end of the first output circuit.

[0069] The second output circuit includes a resistor R10, a resistor R11, a resistor R12, a capacitor C13, a capacitor C14, a capacitor C15, a capacitor C16, a capacitor C17, a capacitor C18, a capacitor C19, a voltage stabilizer U4, an intermediate frequency signal filter F2, and a second output terminal O2;

[0070] The first end of the resistor R12 is connected to the intermediate frequency signal processing circuit, and the second end of the resistor R12 is respectively connected to the first end of the capacitor C15, the first end of the resistor R10, the first end of the capacitor C16 and the first end of R11;

[0071] The second end of the capacitor C15 and the second end of the resistor R10 are grounded respectively, and the second end of the capacitor C16 and the second end of R11 are connected to the input end of the intermediate frequency signal filter F2 respectively;

[0072] Pin 1 of the voltage stabilizer U4 is respectively connected to the intermediate frequency signal processing circuit and the first end of the capacitor C18, pin 2 of the voltage stabilizer U4 and the second end of the capacitor C18 are respectively grounded, pin 3 of the voltage stabilizer U4 and the first end of the capacitor C19 are respectively connected to the input end of the intermediate frequency signal filter F2, and the second end of the capacitor C19 is grounded;

[0073] The first end of the capacitor C17 is connected to the intermediate frequency signal processing circuit, the second end of the capacitor C17 and the output end of the intermediate frequency signal filter F2 are respectively connected to the input end of the second output terminal O2, and the output end of the second output terminal O2 is the output end of the second output circuit.

[0074] exist Figure 2 In the figure, H is the vertical antenna and V is the horizontal antenna.

[0075] A1 is the negative electrode of the first power supply, and B1 is the positive electrode of the first power supply.

[0076] A2 is the negative electrode of the second power supply, and B2 is the positive electrode of the second power supply.

[0077] The first pin of the mixer U1 is the first receiving end of the intermediate frequency signal processing circuit, the second pin of the mixer U1 is the second receiving end of the intermediate frequency signal processing circuit, and the third pin of the mixer U1 is the third receiving end of the intermediate frequency signal processing circuit.

[0078] The working principle of a frequency reduction circuit is described below, as detailed below:

[0079] The vertical and horizontal antennas are responsible for capturing the RF signal from the transmitting source.

[0080] The base of the PNP transistor Q1 is respectively connected to the vertical antenna and the first end of the resistor R1, the second end of the resistor R1 and the first end of the capacitor C4 are respectively connected to the negative electrode of the first power supply, and after the first end of the capacitor C2 is connected to the positive electrode of the first power supply, the voltage of the emitter of the PNP transistor Q1 is controlled to be higher than the voltage of the base by more than 0.7V. At this time, since the collector of the PNP transistor Q1 is grounded, the voltage of the collector of the PNP transistor Q1 is lower than the voltage of the base of the PNP transistor Q1. Therefore, the PNP transistor Q1 is turned on, allowing the RF signal of the vertical antenna to pass through, and the RF signal of the vertical antenna is sent to the first signal amplification circuit. After the amplitude is enhanced, the power of the RF signal is significantly improved, providing a good foundation for subsequent processing.

[0081] The power pin of the mixer U1 is connected to the positive electrode of the second power supply. After the negative pin of the mixer U1 is connected to the negative electrode of the second power supply, the mixer U1 provides a voltage higher than the base to the emitter of the PNP transistor Q2, and controls the voltage of the emitter of the PNP transistor Q2 to be more than 0.7V higher than the voltage of the base. At this time, since the collector of the PNP transistor Q2 is grounded, the voltage of the collector of the PNP transistor Q2 is lower than the voltage of the base of the PNP transistor Q2. Therefore, the PNP transistor Q2 is turned on, allowing the RF signal of the horizontal antenna to pass through. The RF signal of the horizontal antenna is sent to the second signal amplification circuit. After the amplitude is enhanced, the power of the RF signal is significantly improved, which provides a good foundation for subsequent processing.

[0082] After the RF signal enters the mixer, the mixer multiplies the RF signal with the stable reference signal generated by the oscillator, reduces the RF signal frequency to the intermediate frequency range, and generates a composite signal containing the intermediate frequency signal. The required intermediate frequency signal is filtered out from the composite signal through the intermediate frequency signal filter F1 and the intermediate frequency signal filter F2.

[0083] In the utility model, the frequency reduction circuit can analyze and convert the radio frequency signal more quickly and accurately, greatly improving the efficiency and reliability of radio frequency signal processing.

[0084] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A frequency reduction circuit, comprising a vertical antenna and a horizontal antenna, characterized in that: The frequency reduction circuit further includes: a first signal amplifying circuit connected to the vertical antenna, a second signal amplifying circuit connected to the horizontal antenna, an intermediate frequency signal processing circuit, an oscillating circuit, a first output circuit and a second output circuit; The output end of the first signal amplifying circuit is connected to the first receiving end of the intermediate frequency signal processing circuit, and the output end of the second signal amplifying circuit is connected to the second receiving end of the intermediate frequency signal processing circuit, forming a first input circuit; The output end of the oscillation circuit is connected to the third receiving end of the intermediate frequency signal processing circuit to form a second input circuit; The intermediate frequency signal processing circuit is respectively connected to the first output circuit and the second output circuit to form a signal output circuit.

2. The frequency reduction circuit according to claim 1, characterized in that: The first signal amplifying circuit includes a PNP transistor Q1, a resistor R1, a resistor R2, a capacitor C1, a capacitor C2, a capacitor C3, and a first power supply; The base of the PNP transistor Q1 is connected to the vertical antenna and the first end of the resistor R1 respectively, the second end of the resistor R1 and the first end of the capacitor C4 are connected to the negative electrode of the first power supply respectively, and the second end of the capacitor C4 is grounded; The first end of R2 and the first end of the capacitor C2 are respectively connected to the positive electrode of the first power supply, and the second end of the capacitor C2 is grounded; The second end of R2 and the first end of C3 are respectively connected to the emitter of the PNP transistor Q1 , the collector of the PNP transistor Q1 is grounded, and the second end of C3 is the output end of the first signal amplifying circuit.

3. The frequency reduction circuit according to claim 1, characterized in that: The second signal amplifying circuit includes a PNP transistor Q2, a resistor R3, a resistor R4, a capacitor C4, a capacitor C5, and a capacitor C6; The base of the PNP transistor Q2 is connected to the horizontal antenna and the first end of the resistor R3 respectively, the second end of the resistor R3 and the first end of the capacitor C4 are connected to the low level end of the intermediate frequency signal processing circuit respectively, and the second end of the capacitor C4 is grounded; The first end of R4 and the first end of the capacitor C5 are respectively connected to the high level end of the intermediate frequency signal processing circuit, and the second end of the capacitor C5 is grounded; The second end of R4 and the first end of C6 are respectively connected to the emitter of the PNP transistor Q2, the collector of the PNP transistor Q2 is grounded, and the second end of C6 is the output end of the second signal amplifying circuit.

4. The frequency reduction circuit according to claim 1, characterized in that: The intermediate frequency signal processing circuit includes a mixer U1, a resistor R5, a resistor R6, and a second power supply; The first end of the resistor R5 and the first end of the resistor R6 are connected to the mixer U1 respectively, and the second end of the resistor R5 and the second end of the resistor R6 are grounded respectively; The power pin of the mixer U1 is connected to the positive electrode of the second power supply, the negative pin of the mixer U1 is connected to the negative electrode of the second power supply, and the ground pin of the mixer U1 is grounded; The first pin of the mixer U1 is the first receiving end of the intermediate frequency signal processing circuit, the second pin of the mixer U1 is the second receiving end of the intermediate frequency signal processing circuit, and the third pin of the mixer U1 is the third receiving end of the intermediate frequency signal processing circuit.

5. The frequency reduction circuit according to claim 1, characterized in that: The oscillation circuit includes an oscillator U2 and a capacitor C13. The first end of the capacitor C13 is connected to the intermediate frequency signal processing circuit and the output end of the oscillator U2. The second end of the capacitor C13 is grounded. The output end of the oscillator U2 is the output end of the oscillation circuit.

6. The frequency reduction circuit according to claim 5, characterized in that: The oscillator U2 is a crystal oscillator.

7. The frequency reduction circuit according to claim 1, characterized in that: The first output circuit includes a resistor R7, a resistor R8, a resistor R9, a capacitor C7, a capacitor C8, a capacitor C9, a capacitor C10, a capacitor C11, a capacitor C12, a voltage stabilizer U3, an intermediate frequency signal filter F1, and a first output terminal O1; The first end of the resistor R7 is connected to the intermediate frequency signal processing circuit, the second end of the resistor R7 is respectively connected to the first end of the capacitor C9, the first end of the resistor R8, the first end of the capacitor C10 and the first end of R9, the second end of the capacitor C9 and the second end of the resistor R8 are respectively grounded, and the second end of the capacitor C10 and the second end of R9 are respectively connected to the input end of the intermediate frequency signal filter F1; Pin 1 of the voltage stabilizer U3 is respectively connected to the intermediate frequency signal processing circuit and the first end of the capacitor C11, pin 2 of the voltage stabilizer U3 and the second end of the capacitor C11 are respectively grounded, pin 3 of the voltage stabilizer U3 and the first end of the capacitor C12 are respectively connected to the input end of the intermediate frequency signal filter F1, and the second end of the capacitor C12 is grounded; The first end of the capacitor C7 is connected to the intermediate frequency signal processing circuit, the second end of the capacitor C7 and the output end of the intermediate frequency signal filter F1 are respectively connected to the input end of the first output terminal O1, and the output end of the first output terminal O1 is the output end of the first output circuit.

8. The frequency reduction circuit according to claim 1, characterized in that: The second output circuit includes a resistor R10, a resistor R11, a resistor R12, a capacitor C13, a capacitor C14, a capacitor C15, a capacitor C16, a capacitor C17, a capacitor C18, a capacitor C19, a voltage stabilizer U4, an intermediate frequency signal filter F2, and a second output terminal O2; The first end of the resistor R12 is connected to the intermediate frequency signal processing circuit, and the second end of the resistor R12 is respectively connected to the first end of the capacitor C15, the first end of the resistor R10, the first end of the capacitor C16 and the first end of R11; The second end of the capacitor C15 and the second end of the resistor R10 are grounded respectively, and the second end of the capacitor C16 and the second end of R11 are connected to the input end of the intermediate frequency signal filter F2 respectively; Pin 1 of the voltage stabilizer U4 is respectively connected to the intermediate frequency signal processing circuit and the first end of the capacitor C18, pin 2 of the voltage stabilizer U4 and the second end of the capacitor C18 are respectively grounded, pin 3 of the voltage stabilizer U4 and the first end of the capacitor C19 are respectively connected to the input end of the intermediate frequency signal filter F2, and the second end of the capacitor C19 is grounded; The first end of the capacitor C17 is connected to the intermediate frequency signal processing circuit, the second end of the capacitor C17 and the output end of the intermediate frequency signal filter F2 are respectively connected to the input end of the second output terminal O2, and the output end of the second output terminal O2 is the output end of the second output circuit.

9. The frequency reduction circuit according to claim 8, characterized in that: The intermediate frequency signal filter F2 is a bandpass filter or a ceramic filter.

10. A frequency downconverter, characterized in that: The invention comprises the frequency reduction circuit as claimed in any one of claims 1 to 9.

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