Transient voltage suppression diode and circuit element

Abstract

The utility model relates to the technical field of diodes, in particular to a transient voltage suppressor diode and a circuit element, the transient voltage suppressor diode comprises a packaging frame, at least two chips and at least one series fuse wire, the packaging frame is enclosed to form at least two installation spaces, and the at least two chips are arranged in the installation spaces. Each chip is arranged in one mounting space and is connected with the packaging framework, and two ends of each series fuse wire are respectively connected with one chip, so that the chips are sequentially connected in series. The utility model mainly aims to provide a transient voltage suppressor diode, and aims to improve the anti-surge capability of a transient voltage suppressor diode protection circuit.

Description

Technical Field

[0001] The utility model relates to the technical field of diodes, in particular to a transient voltage suppression diode and a circuit element. Background Art

[0002] TVS (Transient Voltage Suppressor) is an overvoltage protection device with bidirectional voltage stabilization characteristics and bidirectional negative resistance characteristics. The transient voltage suppression diode generally includes a packaging frame, a single chip (with a functional structure for transient voltage protection) arranged in the packaging frame, and circuit connectors. The transient voltage suppression diode is in a high-resistance state under normal conditions (undamaged working state). Based on this characteristic, the transient voltage suppression diode is used as a circuit protection element to absorb surge pulse voltage in the circuit.

[0003] When the surge pulse voltage passes through the transient voltage suppression diode, there is a possibility that the transient voltage suppression diode is broken down. In this case, the chip broken down by the transient voltage is converted into a low-resistance state. When a secondary surge occurs in the circuit, the transient voltage suppression diode at this time fails and no longer has the function of protecting the circuit, causing other components in the circuit to be broken down and fail. Utility Model Content

[0004] The main purpose of the utility model is to provide a transient voltage suppression diode, aiming to improve the surge resistance of the transient voltage suppression diode protection circuit.

[0005] To achieve the above object, the transient voltage suppression diode comprises:

[0006] A packaging frame, wherein the packaging frame encloses at least two installation spaces;

[0007] at least two chips, each of which is disposed in one of the mounting spaces and connected to the packaging frame; and

[0008] At least one series fuse, two ends of each series fuse are respectively connected to one of the chips, so that the chips are connected in series in sequence.

[0009] In one embodiment, the packaging frame includes at least two packaging frames, at least two packaging frames are arranged in parallel and in series, each packaging frame encloses an installation space, and each chip is arranged in an installation space.

[0010] In one embodiment, a chip bonding surface of each of the chips is exposed in one of the mounting spaces.

[0011] In one embodiment, the packaging frame is provided with two installation spaces, each of which is provided with a chip; and the two chips are connected in series via the series fuse.

[0012] In one embodiment, a series fuse is provided between the two chips so that the two chips are connected in series.

[0013] In one embodiment, a plurality of the series fuses are disposed between the two chips, and the plurality of the series fuses are arranged in parallel.

[0014] In one embodiment, a filling gap is formed between each of the chips and the packaging frame, and a protection structure is provided in the filling gap.

[0015] In one embodiment, the transient voltage suppression diode further includes a sealing layer, and the sealing layer covers the package frame and the chip.

[0016] In one embodiment, the transient voltage suppression diode further includes a pin pad, and the pin pad is disposed on one side of the packaging frame and close to the chip.

[0017] The utility model also provides a circuit element, which includes the transient voltage suppression diode.

[0018] The utility model provides a transient voltage suppression diode, which includes a packaging frame, at least two chips and a series fuse. A plurality of chips are arranged in the packaging frame and any two adjacent chips are connected by the series fuse, so that the plurality of chips are connected in series. When a surge transient voltage is higher than the limit voltage that the transient voltage suppression diode can withstand, causing any chip to fail, the series connection of the series fuse makes the other chips in a high-resistance state. At this time, the transient voltage suppression diode is still in a high-resistance state. When a secondary surge passes through, the transient voltage suppression diode can still play a role in protecting the circuit. When the surge transient After the voltage passes through the transient voltage suppression diode, the chip is not broken down. At this time, the series fuse is blown due to the excessive voltage. At this time, multiple chips are disconnected, so that the transient voltage suppression diode enters an open circuit high resistance state. When the secondary surge passes through, the transient voltage suppression diode can still play a role in protecting the circuit; when the surge transient voltage passes through the transient voltage suppression diode, all chips are broken down and enter a low resistance state. At this time, the current becomes larger and burns the series fuse, causing all chips to be disconnected, so that the transient voltage suppression diode enters an open circuit high resistance state. When the secondary surge passes, the transient voltage suppression diode can still play a role in protecting the circuit. In summary, the utility model proposes a transient voltage suppression diode that can improve the surge resistance of the transient voltage suppression diode protection circuit, prevent the secondary surge transient voltage from damaging other components in the circuit, thereby avoiding circuit control failure, thereby improving the safety of the circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the embodiments of the utility model or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the utility model. For ordinary technicians in this field, other drawings can be obtained based on the structures shown in these drawings without paying creative work.

[0020] Figure 1 A schematic structural diagram of an embodiment of a transient voltage suppression diode provided by the utility model;

[0021] Figure 2 This is a schematic structural diagram of another embodiment of the transient voltage suppression diode provided by the utility model.

[0022] Description of Figure Numbers:

[0023] 10. Package frame; 101. Package frame; 20. Chip; 20a. Chip welding surface; 30. Series fuse; 40. Protection structure; 50. Pin pad.

[0024] The realization of the purpose, functional features and advantages of the utility model will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0025] The following will be combined with the drawings in the embodiments of the utility model to clearly and completely describe the technical solutions in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments of the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.

[0026] It should be noted that if the embodiments of the present invention involve directional indications (such as up, down, left, right, front, back...), the directional indications are only used to explain the relative position relationship, movement status, etc. between the components in a certain specific posture. If the specific posture changes, the directional indications will also change accordingly.

[0027] In addition, if there are descriptions involving "first", "second", etc. in the embodiments of the utility model, the descriptions of "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of technical features indicated. Therefore, the features limited to "first" and "second" may explicitly or implicitly include at least one of the features. In addition, if "and / or" or "and / or" appears in the full text, its meaning includes three parallel solutions. Taking "A and / or B" as an example, it includes solution A, solution B, or solutions that satisfy both A and B. In addition, the technical solutions between the various embodiments can be combined with each other, but it must be based on the ability of ordinary technicians in this field to implement. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such combination of technical solutions does not exist and is not within the scope of protection required by the utility model.

[0028] See also Figure 1 and Figure 2 , transient voltage suppressor diodes include:

[0029] The packaging frame 10 is enclosed to form at least two installation spaces;

[0030] At least two chips 20, each chip 20 is disposed in a mounting space and connected to the packaging frame 10; and

[0031] There is at least one series fuse 30 , and both ends of each series fuse 30 are connected to a chip 20 , so that each chip 20 is connected in series in sequence.

[0032] The utility model provides a transient voltage suppression diode, which includes a packaging frame 10, at least two chips 20 and a series fuse 30. A plurality of chips 20 are arranged in the packaging frame 10 and any two adjacent chips 20 are connected by the series fuse 30, so that the plurality of chips 20 are connected in series. When a surge transient voltage is higher than the limit voltage that the transient voltage suppression diode can withstand, causing any chip 20 to fail, the series connection of the series fuse 30 makes the other chips 20 in a high-resistance state. At this time, the transient voltage suppression diode is still in a high-resistance state. When a secondary surge passes through, the transient voltage suppression diode can still play a role in protecting the circuit. When the surge transient voltage passes through the transient voltage suppression diode, the chip 20 is not broken down. At this time, the series fuse 30 is blown due to the excessive voltage. At this time, multiple chips 20 are disconnected, so that the transient voltage suppression diode enters an open circuit high resistance state. When the secondary surge passes, the transient voltage suppression diode can still play a role in protecting the circuit; when the surge transient voltage passes through the transient voltage suppression diode, all chips 20 are broken down and enter a low resistance state. At this time, the current becomes larger and burns the series fuse 30, causing all chips 20 to be disconnected, so that the transient voltage suppression diode enters an open circuit high resistance state. When the secondary surge passes, the transient voltage suppression diode can still play a role in protecting the circuit. In summary, the utility model proposes a transient voltage suppression diode that can improve the surge resistance of the transient voltage suppression diode protection circuit, prevent the secondary surge transient voltage from damaging other components in the circuit, thereby avoiding control failure of the circuit, thereby improving the safety of the circuit.

[0033] The packaging frame 10 may be a planar frame or a three-dimensional frame. In one embodiment, the packaging frame 10 is a planar frame. It can be understood that the planar frame is still a three-dimensional structure with length, width and height (a certain length along the X-axis, Y-axis and Z-axis in the spatial coordinate system), and its height is negligible compared to the length or width. At least two installation spaces enclosed by the packaging frame 10 can be isolated by an isolation structure such as an isolation strip. Each chip 20 is arranged in an installation space. It can be understood that the position of the chip 20 and the packaging frame 10 can be fixed by a welding process, such as copper welding, and then a plurality of chips 20 are connected in sequence by a series fuse 30 between any two chips 20, so that the plurality of chips 20 are connected in series in sequence. It can be understood that the utility model The invention concept of this type is how to utilize multiple chips 20 to improve surge resistance and thus circuit protection capability under the series connection of series fuses 30. There is no restriction on the binding method of the series fuses 30, the packaging frame 10 and the chip 20, and adaptive limitations can be made according to actual processes; in another implementation, the packaging frame 10 is a three-dimensional frame, and the packaging frame 10 forms a plurality of installation spaces, and the plurality of installation spaces are stacked in sequence along the height direction of the packaging frame 10. An isolation plate can be provided between the plurality of installation spaces of the packaging frame 10 to isolate the plurality of installation spaces from each other, and one or more wire-passing channels are provided on the isolation plate, so that each series fuse 30 can connect two chips 20 in series through a wire-passing channel, thereby forming a plurality of chip 20 structures stacked in sequence and connected in series in the packaging frame 10.

[0034] In one embodiment, if Figure 1 As shown, the packaging frame 10 includes at least two packaging frames 101 . The at least two packaging frames 101 are arranged in parallel and in series. Each packaging frame 101 encloses a mounting space, and each chip 20 is arranged in a mounting space.

[0035] In this embodiment, the packaging frame 10 is a planar frame, and includes multiple packaging frames 101 along the length direction of the packaging frame 10. The multiple packaging frames 101 are arranged in parallel and in series, and each packaging frame 101 encloses an installation space. The installation spaces between any two adjacent ones are isolated by the frame structure so that the multiple chips 20 are arranged at intervals. In the process of fixing the chip 20, the isolation of multiple installation spaces from each other can avoid the contact between multiple chips 20 in a complete space and cause the position to loosen, thereby reducing the difficulty of fixing the chip 20.

[0036] In one embodiment, if Figure 1 and Figure 2 As shown, the chip bonding surface 20 a of each chip 20 is exposed in a mounting space.

[0037] In this embodiment, the chip welding surface 20a of each chip 20 is exposed in an installation space. In the positioning process before the chip 20 is fixed, because the chip welding surface 20a is exposed in the installation space, at this time, positioning detection tools such as camera probes can directly observe whether the structure used for positioning and fixing on the chip welding surface 20a of the chip 20 and the structure used for positioning and fixing on the packaging frame 10 match in position, and can directly confirm whether the chip 20 is placed in place, thereby reducing the problem of difficulty in positioning between the chip 20 and the packaging frame 101.

[0038] In one embodiment, if Figure 1 and Figure 2 As shown, the package frame 10 is provided with two installation spaces, each of which is provided with a chip 20 ; the two chips 20 are connected in series via a series fuse 30 .

[0039] In the present embodiment, the packaging frame 10 is provided with two installation spaces, each installation space is provided with a chip 20, and the two chips 20 are connected in series through a series fuse 30. It can be understood that in a transient voltage suppressor diode, only one chip 20 out of any number of chips 20 needs to be not broken down, or all chips 20 are broken down causing all series fuses 30 to burn out so that all chips 20 are disconnected. The transient voltage suppressor diodes are all in a high-resistance state. Therefore, under the premise that any one chip 20 in a transient voltage suppressor diode is not broken down, the transient voltage suppressor diode is still in a high-resistance state and can play a role in protecting the circuit. Based on this, two chips 20 connected in series through a series fuse 30 are provided in the transient voltage suppressor diode to realize the function of protecting the circuit, reduce the cost of structural materials, and can compress the installation space required for the transient voltage suppressor diode to the greatest extent, thereby improving the convenience of circuit installation.

[0040] In one embodiment, if Figure 1 As shown, a series fuse 30 is provided between the two chips 20 so that the two chips 20 are connected in series.

[0041] In this embodiment, a series fuse 30 is provided between the two chips 20 so that the two chips 20 are connected in series. At this time, a low surge current can more easily blow the series fuse 30 to put the transient voltage suppression diode in a high-resistance open circuit state for circuit protection.

[0042] In one embodiment, if Figure 2 As shown, a plurality of series fuses 30 are arranged between the two chips 20, and the plurality of series fuses 30 are arranged in parallel.

[0043] In this embodiment, a plurality of series fuses 30 are provided between two chips 20, and the two ends of each series fuse 30 are respectively connected to a chip 20, and the plurality of series fuses 30 are arranged in parallel. In this way, when the surge circuit does not break down the chip 20 but burns one of the series fuses 30, the plurality of series fuses 30 can improve the surge resistance of a transient voltage suppression diode, thereby increasing the use scenarios of the transient voltage suppression diode.

[0044] In one embodiment, if Figure 1 and Figure 2 As shown, a filling gap is formed between each chip 20 and the package frame 10 , and a protection structure 40 is provided in the filling gap.

[0045] In this embodiment, after the chip 20 is fixed on the packaging frame 10, a certain distance is provided between the chip 20 and the inner wall of the installation space to form a hollow area. The hollow area surrounds the outer peripheral side of the chip 20. A protective structure 40 such as protective glue, silicone grease, etc. can be filled in the hollow area. The protective structure 40 not only protects the chip 20, but also enhances the connection reliability between the chip 20 and the packaging frame 10.

[0046] In one embodiment, the transient voltage suppression diode further includes a sealing layer, and the sealing layer covers the package frame 10 and the chip 20 .

[0047] In this embodiment, the diode packaging structure also includes a sealing layer, which is an epoxy plastic sealing layer. The sealing layer covers the surface of the packaging frame 10 and the chip 20, thereby sealing the chip 20 and the packaging frame 10 to prevent the diode packaging structure from being affected by external influences such as moisture, temperature changes, pollutants, and mechanical shocks.

[0048] In one embodiment, if Figure 1 and Figure 2 As shown, the transient voltage suppression diode further includes a pin pad 50 , which is disposed on one side of the package frame 10 and close to the chip 20 .

[0049] In this embodiment, the transient voltage suppressor diode also includes a pin pad 50, which is arranged on one side of the packaging frame 10 and close to the chip 20. Wire pins connected to the external circuit can be set on the pin pad 50, so as to form a structural layout in which the chip 20 is connected to the packaging frame 10 and the packaging frame 10 is connected to the pin pad 50 on the same side of the transient voltage suppressor diode, so that the other outer side of the transient voltage suppressor diode can be used to set other functional structures.

[0050] The utility model also proposes a circuit element, which includes a transient voltage suppression diode for protecting the circuit. The circuit element can be a power line or a surge protector, which is not limited here. The specific structure of the transient voltage suppression diode refers to the above embodiment. Since the circuit element adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought by the technical solutions of the above embodiments, which will not be repeated here.

[0051] The above are only preferred embodiments of the present invention, and do not limit the patent scope of the present invention. All equivalent structural changes made by using the contents of the present invention specification and drawings under the inventive concept of the present invention, or directly / indirectly applied in other related technical fields are included in the patent protection scope of the present invention.

Claims

1. A transient voltage suppression diode, characterized in that: The transient voltage suppression diode comprises: A packaging frame (10), wherein the packaging frame (10) encloses at least two installation spaces; At least two chips (20), each of the chips (20) is disposed in one of the installation spaces and connected to the packaging frame (10); and At least one series fuse (30), with two ends of each series fuse (30) connected to a chip (20) respectively, so that each chip (20) is connected in series in sequence.

2. The transient voltage suppressor diode according to claim 1, characterized in that: The packaging frame (10) comprises at least two packaging frames (101), the at least two packaging frames (101) are arranged in parallel and in series, each packaging frame (101) encloses an installation space, and each chip (20) is arranged in an installation space.

3. The transient voltage suppressor diode according to claim 2, characterized in that: The chip welding surface (20a) of each chip (20) is exposed in an installation space.

4. The transient voltage suppressor diode according to any one of claims 1 to 3, characterized in that: The packaging frame (10) is provided with two installation spaces, each of which is provided with a chip (20); the two chips (20) are connected in series via the series fuse (30).

5. The transient voltage suppressor diode according to claim 4, characterized in that: A series fuse (30) is provided between the two chips (20) so that the two chips (20) are connected in series.

6. The transient voltage suppressor diode according to claim 4, characterized in that: A plurality of the series fuses (30) are arranged between the two chips (20), and the plurality of the series fuses (30) are arranged in parallel.

7. The transient voltage suppressor diode according to claim 1, wherein: A filling gap is formed between each chip (20) and the packaging frame (10), and a protection structure (40) is provided in the filling gap.

8. The transient voltage suppressor diode according to claim 1, wherein: The transient voltage suppression diode further comprises a sealing layer, wherein the sealing layer covers the packaging frame (10) and the chip (20).

9. The transient voltage suppressor diode according to claim 7, characterized in that: The transient voltage suppression diode further comprises a pin pad (50), wherein the pin pad (50) is arranged on one side of the packaging frame (10) and is disposed close to the chip (20).

10. A circuit element, characterized in that: The circuit element comprises a transient voltage suppression diode as claimed in any one of claims 1 to 9.

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