Back contact battery and photovoltaic module

Abstract

The utility model discloses a back contact cell and a photovoltaic assembly. The back contact cell comprises a silicon wafer; the tunneling oxide layer is arranged on one part of the surface of one side of the silicon wafer in the thickness direction; the first doped polycrystalline silicon layer is arranged on the side, away from the silicon wafer, of the tunneling oxide layer in the thickness direction, the thickness of the first doped polycrystalline silicon layer is d1, and d1 is larger than or equal to 60 nm and smaller than or equal to 80 nm. According to the back contact cell provided by the utility model, the first doped polycrystalline silicon layer with specific thickness and specific effective doping concentration is arranged on the surface of one side of the silicon wafer, so that the contact performance and excellent passivation effect of the first doped polycrystalline silicon layer are ensured at the same time. Therefore, the light absorption effect of the first doped polycrystalline silicon layer can be reduced, so that the short-circuit current of the back contact cell is greatly improved, and the conversion efficiency of the back contact cell is further improved.

Description

Technical Field

[0001] The utility model relates to the technical field of photovoltaic back contact cells, in particular to a back contact cell and a photovoltaic component. Background Art

[0002] In the prior art, the front of the back-contact heterojunction high-efficiency solar back-contact cell is generally passivated with amorphous silicon and anti-reflective layer of silicon nitride. The back is passivated and contacted by tunneling silicon oxide and polycrystalline silicon. However, polycrystalline silicon, like amorphous silicon, has a certain light absorption effect, which limits the improvement of short-circuit current, thus affecting the conversion efficiency of the back-contact cell. Utility Model Content

[0003] The utility model aims to solve at least one of the technical problems existing in the prior art. To this end, one purpose of the utility model is to provide a back contact battery with high conversion efficiency.

[0004] Another object of the present invention is to provide a photovoltaic module.

[0005] According to an embodiment of the first aspect of the utility model, the utility model provides a back-contact battery, comprising: a silicon wafer; a tunneling oxide layer, the tunneling oxide layer being arranged on a portion of a surface of one side in a thickness direction of the silicon wafer; a first doped polysilicon layer, the first doped polysilicon layer being arranged on a side away from the silicon wafer in a thickness direction of the tunneling oxide layer, the thickness of the first doped polysilicon layer being d1, wherein d1 satisfies: 60nm≤d1≤80nm.

[0006] According to the back contact cell of the specific embodiment of the utility model, a specific thickness (60nm-80nm) and a specific effective doping concentration (1e20cm -3 ~1.5e21cm -3 ) so that the effective doping concentration of the first doped polysilicon layer matches the thickness of the first doped polysilicon layer, while ensuring that the contact performance of the first doped polysilicon layer has an excellent passivation effect. In this way, the light absorption effect of the first doped polysilicon layer can be reduced, thereby greatly improving the short-circuit current of the back-contact battery, thereby improving the conversion efficiency of the back-contact battery.

[0007] According to some embodiments of the present invention, it also includes: a first intrinsic amorphous silicon layer, the first intrinsic amorphous silicon layer is at least arranged on one side of the thickness direction of the first doped polycrystalline silicon layer; a second doped microcrystalline silicon layer, the second doped microcrystalline silicon layer is arranged on the side of the first intrinsic amorphous silicon layer in the thickness direction away from the silicon wafer; preferably, the second doped microcrystalline silicon layer is a boron-doped microcrystalline silicon layer.

[0008] According to some embodiments of the present invention, the thickness of the second doped microcrystalline silicon layer is d2, wherein d2 satisfies: 35nm≤d2≤45nm; and / or the thickness of the first intrinsic amorphous silicon layer is d3, wherein d3 satisfies: 4nm≤d3≤6nm.

[0009] According to some embodiments of the present invention, it also includes: a second intrinsic amorphous silicon layer, which is arranged on the other side of the silicon wafer in the thickness direction; a third doped microcrystalline silicon layer, which is arranged on the side of the second intrinsic amorphous silicon layer in the thickness direction away from the silicon wafer; preferably, the third doped microcrystalline silicon layer is a phosphorus-doped microcrystalline silicon layer.

[0010] According to some embodiments of the present invention, the thickness of the third doped microcrystalline silicon layer is d4, wherein d4 satisfies: 35nm≤d4≤45nm; and / or the thickness of the second intrinsic amorphous silicon layer is d5, wherein d5 satisfies: 4nm≤d5≤6nm.

[0011] According to some embodiments of the present invention, the thickness of the tunnel oxide layer is d6, wherein d6 satisfies: 1nm≤d6≤2nm; preferably, 1.3nm≤d6≤1.8nm.

[0012] According to some embodiments of the present invention, the silicon wafer is an n-type 182 half-wafer; and / or the resistivity of the silicon wafer is 0.9Ω / cm 2 ~4Ω / cm 2 .

[0013] According to some embodiments of the present invention, the present invention further includes: a transparent conductive oxide layer, wherein the transparent conductive oxide layer is disposed on a side of the second doped microcrystalline silicon layer away from the silicon wafer in the thickness direction.

[0014] According to some embodiments of the present invention, the transparent conductive oxide layer is an ITO layer and / or a VTTO layer; preferably, the transparent conductive oxide layer is an ITO layer doped with hydrogen and / or a VTTO layer doped with hydrogen.

[0015] According to an embodiment of the second aspect of the utility model, the utility model provides a photovoltaic component, including: a back contact cell according to the embodiment of the first aspect of the utility model.

[0016] Additional aspects and advantages of the present invention will be given in part in the following description, and in part will become apparent from the following description, or will be learned through the practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0018] Figure 1 It is a schematic structural diagram of a back contact battery according to an embodiment of the utility model.

[0019] Reference numerals:

[0020] 100: back contact battery;

[0021] 1: silicon wafer; 2: tunneling oxide layer; 3: first doped polysilicon layer; 4: first intrinsic amorphous silicon layer; 5: second doped microcrystalline silicon layer; 6: second intrinsic amorphous silicon layer; 7: third doped microcrystalline silicon layer; 8: transparent conductive oxide layer; 9: silicon nitride anti-reflection film; 10: metal cathode; 11: metal anode. DETAILED DESCRIPTION

[0022] The embodiments of the present invention are described in detail below. The embodiments described with reference to the accompanying drawings are exemplary. Figure 1 A back contact cell 100 according to a specific embodiment of the present invention is described.

[0023] like Figure 1 As shown, the back contact cell 100 of the specific embodiment of the utility model includes a silicon wafer 1, a tunneling oxide layer 2 and a first doped polysilicon layer 3, and the tunneling oxide layer 2 is provided on a part of the surface of one side of the silicon wafer 1 in the thickness direction. Here, the tunneling oxide layer 2 can be a silicon dioxide layer. Among them, the tunneling oxide layer 2 and the first doped polysilicon layer 3 can be obtained by chemical vapor deposition (PECVD) furnace tube deposition respectively. Optionally, the deposition power of the tunneling oxide layer 2 is 10000W~13500W. Optionally, the first doped polysilicon layer 3 of the utility model obtained by chemical vapor deposition can also include a high temperature annealing step. The annealing temperature can be controlled at 900℃~1000℃, and the annealing time is 500S~800S. After annealing, it is set to perform gradient cooling every 10℃ / S, and the time is controlled to be 1000S~1200S. In this way, the preparation process of the first doped polysilicon layer 3 of the utility model can prevent a large amount of phosphorus source from penetrating the tunnel oxide layer 2 to reach the surface of the silicon wafer 1 due to annealing by matching the appropriate annealing temperature and time, resulting in an increase in the SiOx / c-Si interface recombination, and also a large number of pinholes (pinholes) in the SiOx layer, thereby affecting the passivation effect. The thickness of the phosphorus silicon glass (PSG) layer can also be controlled to be 80nm to 100nm, and the formed PSG layer can be used as a subsequent mask, without the need to deposit silicon nitride as a mask separately through PECVD equipment, which greatly simplifies the process flow, and can also avoid the subsequent difficult-to-clean local silicon nitride mask, resulting in appearance color difference. However, the selection of process and process steps is not limited to this.

[0024] Wherein, the thickness of the first doped polysilicon layer 3 is d1, wherein d1 satisfies: 60nm≤d1≤80nm. In this way, if d1 is less than 60nm, the thickness of the first doped polysilicon layer 3 is small, the safety may be low, and the safe use of the back contact battery 100 may be affected; if d1 is greater than 80nm, the thickness of the first doped polysilicon layer 3 is large, which may cause the first doped polysilicon layer 3 to have a large light absorption effect and a small short-circuit current, thereby affecting the efficiency of the back contact battery 100. By setting, so that d1 satisfies 60nm≤d1≤80nm, the thickness of the first doped polysilicon layer 3 is appropriate, and the back contact battery 100 is safe to use and has high conversion efficiency. Optionally, the thickness of the first doped polysilicon layer 3 is 60nm, 65nm, 70nm, 75nm or 80nm. But it is not limited to this.

[0025] In addition, the first doped polysilicon layer 3 has an effective doping concentration of 1e20 cm -3 ~1.5e21cm -3 Doped polysilicon layer. In this way, by setting a suitable effective doping concentration, the effective doping concentration of the first doped polysilicon layer 3 matches the thickness of the first doped polysilicon layer 3, while ensuring the contact performance and excellent passivation effect of the first doped polysilicon layer 3. In this way, the light absorption effect of the first doped polysilicon layer 3 can be reduced, thereby greatly improving the short-circuit current of the back contact battery 100.

[0026] According to the back contact cell 100 of the specific embodiment of the present invention, a specific thickness (60nm-80nm) and a specific effective doping concentration (1e20cm -3 ~1.5e21cm -3 ) of the first doped polysilicon layer 3, so that the effective doping concentration of the first doped polysilicon layer 3 matches the thickness of the first doped polysilicon layer 3, while ensuring the contact performance and excellent passivation effect of the first doped polysilicon layer 3. In this way, the light absorption effect of the first doped polysilicon layer 3 can be reduced, thereby greatly improving the short-circuit current of the back-contact battery 100, and then improving the conversion efficiency of the back-contact battery 100. In addition, in the present utility model, one side of the silicon wafer 1 in the thickness direction corresponds to the back side of the back contact battery 100, and the other side of the silicon wafer 1 in the thickness direction corresponds to the front side of the back contact battery 100.

[0027] According to some embodiments of the present invention, it further comprises: a first intrinsic amorphous silicon layer 4 and a second doped microcrystalline silicon layer 5, wherein the first intrinsic amorphous silicon layer 4 is at least arranged on one side of the first doped polycrystalline silicon layer 3 in the thickness direction, and the second doped microcrystalline silicon layer 5 is arranged on the side away from the silicon wafer 1 in the thickness direction of the first intrinsic amorphous silicon layer 4. Such an arrangement is conducive to improving the passivation and tunneling contact performance of one side (back side) of the back contact cell 100.

[0028] Furthermore, the second doped microcrystalline silicon layer 5 is a boron doped microcrystalline silicon layer. This configuration is beneficial to reducing the resistance of the back side of the back contact cell 100 , thereby improving the conversion efficiency of the back contact cell 100 .

[0029] According to some embodiments of the utility model, the thickness of the second doped microcrystalline silicon layer 5 is d2, wherein d2 satisfies: 35nm≤d2≤45nm. In this way, if d2 is less than 35nm, the thickness of the second doped microcrystalline silicon layer 5 is small, the safety may be low, and the safe use of the back contact battery 100 may be affected; if d2 is greater than 45nm, the thickness of the second doped microcrystalline silicon layer 5 is large, which may cause the second doped microcrystalline silicon layer 5 to have a large light absorption effect and a small short-circuit current, thereby affecting the efficiency of the back of the back contact battery 100. By setting so that d2 satisfies 35nm≤d2≤45nm, the thickness of the second doped microcrystalline silicon layer 5 is appropriate, the back contact battery 100 is safe to use, and the conversion efficiency of the back of the back contact battery 100 is high. Optionally, the thickness of the second doped microcrystalline silicon layer 5 is 35nm, 38nm, 40nm, 42nm or 45nm. But it is not limited to this.

[0030] According to some other embodiments of the utility model, the thickness of the first intrinsic amorphous silicon layer 4 is d3, wherein d3 satisfies: 4nm≤d3≤6nm. In this way, if d3 is less than 4nm, the thickness of the first intrinsic amorphous silicon layer 4 is small, the safety may be low, and the safe use of the back contact battery 100 may be affected; if d3 is greater than 6nm, the thickness of the first intrinsic amorphous silicon layer 4 is large, which may cause the first intrinsic amorphous silicon layer 4 to have a large light absorption effect and a small short-circuit current, thereby affecting the efficiency of the back side of the back contact battery 100. By setting so that d3 satisfies 4nm≤d3≤6nm, the thickness of the first intrinsic amorphous silicon layer 4 is appropriate, the back contact battery 100 is safe to use, and the conversion efficiency of the back side of the back contact battery 100 is high. Optionally, the thickness of the first intrinsic amorphous silicon layer 4 is 4nm, 4.5nm, 5nm, 5.5nm or 6nm. But it is not limited thereto.

[0031] According to some embodiments of the present invention, it further comprises: a second intrinsic amorphous silicon layer 6 and a third doped microcrystalline silicon layer 7, wherein the second intrinsic amorphous silicon layer 6 is arranged on the other side of the thickness direction of the silicon wafer 1 (i.e., the front side of the back contact battery 100), and the third doped microcrystalline silicon layer 7 is arranged on the side of the second intrinsic amorphous silicon layer 6 in the thickness direction away from the silicon wafer 1. This is beneficial to improving the passivation and tunneling contact performance of the other side (front side) of the back contact battery 100.

[0032] Preferably, the third doped microcrystalline silicon layer 7 is a phosphorus doped microcrystalline silicon layer. This arrangement further improves the passivation performance of the front side of the back contact cell 100.

[0033] Optionally, the first intrinsic amorphous silicon layer 4 , the second intrinsic amorphous silicon layer 6 , the second doped microcrystalline silicon layer 5 , and the third doped microcrystalline silicon layer 7 are respectively obtained by plate-type chemical vapor deposition.

[0034] According to some embodiments of the utility model, the thickness of the third doped microcrystalline silicon layer 7 is d4, wherein d4 satisfies: 35nm≤d4≤45nm. In this way, if d4 is less than 35nm, the thickness of the third doped microcrystalline silicon layer 7 is small, the safety may be low, and the safe use of the back contact battery 100 may be affected; if d4 is greater than 45nm, the thickness of the third doped microcrystalline silicon layer 7 is large, which may cause the third doped microcrystalline silicon layer 7 to have a large light absorption effect and a small short-circuit current, thereby affecting the photoelectric conversion efficiency of the front of the back contact battery 100. By setting, so that d4 satisfies 35nm≤d4≤45nm, the thickness of the third doped microcrystalline silicon layer 7 is appropriate, the back contact battery 100 is safe to use, and the conversion efficiency of the third doped microcrystalline silicon layer 7 of the back contact battery 100 is high. Optionally, the thickness of the third doped microcrystalline silicon layer 7 is 35nm, 38nm, 40nm, 42nm or 45nm. But it is not limited to this.

[0035] According to some other embodiments of the utility model, the thickness of the second intrinsic amorphous silicon layer 6 is d5, wherein d5 satisfies: 4nm≤d5≤6nm. In this way, if d5 is less than 4nm, the thickness of the second intrinsic amorphous silicon layer 6 is small, the safety may be low, and the safe use of the back contact battery 100 may be affected; if d5 is greater than 6nm, the thickness of the second intrinsic amorphous silicon layer 6 is large, which may cause the second intrinsic amorphous silicon layer 6 to have a large light absorption effect and a small short-circuit current, thereby affecting the photoelectric conversion efficiency of the front side of the back contact battery 100. By setting, so that d3 satisfies 4nm≤d3≤6nm, the thickness of the second intrinsic amorphous silicon layer 6 is appropriate, the back contact battery 100 is safe to use, and the conversion efficiency of the front side of the back contact battery 100 is high. Optionally, the thickness of the second intrinsic amorphous silicon layer 6 is 4nm, 4.5nm, 5nm, 5.5nm or 6nm. But it is not limited to this.

[0036] According to some embodiments of the utility model, the thickness of the tunneling oxide layer 2 is d6, wherein d6 satisfies: 1nm≤d6≤2nm. In this way, if d6 is less than 1nm, the thickness of the tunneling oxide layer 2 is small, which may lead to poor passivation performance of the tunneling oxide layer 2; if d6 is greater than 2nm, the thickness of the tunneling oxide layer 2 is large, which may lead to poor contact performance of the tunneling oxide layer 2. By setting, so that d6 satisfies 1nm≤d6≤2nm, the thickness of the tunneling oxide layer 2 is appropriate, the back contact battery 100 is safe to use, the short-circuit current of the back contact battery 100 is large, and the photoelectric conversion efficiency is high. Optionally, the thickness of the tunneling oxide layer 2 is 1nm, 1.3nm, 1.6nm, 1.8nm or 2.0nm. But not limited to this. Preferably, 1.3nm≤d6≤1.8nm, so that the thickness of the tunneling oxide layer 2 is more suitable, and optionally, the thickness of the tunneling oxide layer 2 is 1.3nm, 1.6nm or 1.8nm. But it is not limited to this.

[0037] According to some embodiments of the present invention, the silicon wafer 1 is an n-type 182 half-wafer 1. In this way, the size of the silicon wafer 1 is suitable, which facilitates the preparation of the back contact cell 100.

[0038] According to some other embodiments of the present invention, the resistivity of the silicon wafer 1 is 0.9Ω / cm 2 ~4Ω / cm 2 With such configuration, the resistivity of the silicon wafer 1 is suitable, which is beneficial to ensure the short-circuit current of the back-contact battery 100. The silicon wafer 1 is double-sided polished and cleaned when preparing the back-contact battery 100.

[0039] According to some embodiments of the present invention, it further includes: a transparent conductive oxide layer 8, which is arranged on a side of the second doped microcrystalline silicon layer 5 in the thickness direction away from the silicon wafer 1. Such an arrangement can provide a protective effect for the back side of the back contact battery 100. Optionally, the transparent conductive oxide layer 8 of the present invention is formed by magnetron sputtering.

[0040] According to some embodiments of the present invention, the transparent conductive oxide layer 8 is an ITO (tin-doped indium oxide, i.e., IndiumTin Oxide) layer and / or a VTTO (a material that VTTO mainly includes important elements such as uranium, tungsten, copper, and other auxiliary elements such as aluminum, iron, carbon, tin, and chromium) layer. In this way, by introducing ITO or VTTO, the electrical performance of the back contact battery 100 can be improved. According to other embodiments of the present invention, the transparent conductive oxide layer 8 is an ITO layer doped with hydrogen and / or a VTTO layer doped with hydrogen. In this way, the introduction of hydrogen will further improve the electrical performance of the back contact battery 100. Taking the hydrogen-doped ITO layer as an example, the introduction of hydrogen will replace the oxygen element position in the In2O3 lattice, and as a shallow donor in the transparent conductive oxide layer 8, hydrogen can release resistance, so that the carrier concentration increases, and thus the resistivity decreases; on the other hand, hydrogen can also react with oxygen to generate oxygen vacancies to reduce the resistivity. At the same time, hydrogen can promote the growth of grains and increase the mobility. Correspondingly, the resistivity of the transparent conductive oxide layer 8 will also decrease. Therefore, the introduction of an appropriate amount of hydrogen will improve the electrical properties of the deposited ITO film. At the same time, the passivation performance of the polysilicon film will be weakened in the subsequent metallization process. In this way, the ITO film doped with hydrogen can improve the passivation quality.

[0041] According to some optional embodiments of the utility model, it also includes: a silicon nitride anti-reflection film 9, which is arranged on the side of the third doped microcrystalline silicon layer 7 away from the silicon wafer 1 in the thickness direction; an electrode, the electrode includes a metal negative electrode 11 and a metal negative electrode 10, and the metal negative electrode 11 and the metal negative electrode 10 are respectively formed on one side of the silicon wafer 1 in the thickness direction (that is, the side corresponding to the back side of the back contact battery 100).

[0042] According to an embodiment of the second aspect of the utility model, the utility model provides a photovoltaic module, including the back contact cell 100 according to the embodiment of the first aspect of the utility model.

[0043] According to the photovoltaic module of the present invention, the back contact cell 100 has high photoelectric conversion efficiency and is safe to use, thereby ensuring the power of the photovoltaic module.

[0044] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the utility model. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example.

[0045] Although the embodiments of the present invention have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the claims and their equivalents.

Claims

1. A back contact battery, characterized in that: include: Silicon wafer; A tunneling oxide layer, wherein the tunneling oxide layer is provided on a portion of a surface of one side in a thickness direction of the silicon wafer; a first doped polysilicon layer, wherein the first doped polysilicon layer is disposed on a side of the tunnel oxide layer away from the silicon wafer in a thickness direction of the tunnel oxide layer, The thickness of the first doped polysilicon layer is d1, wherein d1 satisfies: 60nm≤d1≤80nm; The first doped polysilicon layer has an effective doping concentration of 1e20 cm -3 ~1.5e21cm -3 Doping the polysilicon layer.

2. The back contact cell according to claim 1, characterized in that: Also includes: a first intrinsic amorphous silicon layer, wherein the first intrinsic amorphous silicon layer is at least provided on one side in a thickness direction of the first doped polysilicon layer; A second doped microcrystalline silicon layer is provided on a side of the first intrinsic amorphous silicon layer away from the silicon wafer in a thickness direction.

3. The back contact battery according to claim 2, characterized in that: The second doped microcrystalline silicon layer is a boron doped microcrystalline silicon layer.

4. The back contact cell according to claim 2, characterized in that: The thickness of the second doped microcrystalline silicon layer is d2, wherein d2 satisfies: 35nm≤d2≤45nm; and / or The thickness of the first intrinsic amorphous silicon layer is d3, wherein d3 satisfies: 4nm≤d3≤6nm.

5. The back contact cell according to claim 1, characterized in that: Also includes: a second intrinsic amorphous silicon layer, wherein the second intrinsic amorphous silicon layer is disposed on the other side of the silicon wafer in a thickness direction; A third doped microcrystalline silicon layer is disposed on a side of the second intrinsic amorphous silicon layer in a thickness direction away from the silicon wafer.

6. The back contact cell according to claim 5, characterized in that: The third doped microcrystalline silicon layer is a phosphorus-doped microcrystalline silicon layer.

7. The back contact battery according to claim 5, characterized in that: The thickness of the third doped microcrystalline silicon layer is d4, wherein d4 satisfies: 35nm≤d4≤45nm; and / or The thickness of the second intrinsic amorphous silicon layer is d5, wherein d5 satisfies: 4nm≤d5≤6nm.

8. The back contact cell according to claim 1, characterized in that The thickness of the tunnel oxide layer is d6, wherein d6 satisfies: 1nm≤d6≤2nm.

9. The back contact cell according to claim 8, characterized in that: The d6 further satisfies: 1.3nm≤d6≤1.8nm.

10. The back contact cell according to claim 1, characterized in that: The silicon wafer is an n-type 182 half-wafer; and / or The resistivity of the silicon wafer is 0.9Ω / cm 2 ~4Ω / cm 2 .

11. The back contact cell according to any one of claims 2 to 4, characterized in that: Also includes: A transparent conductive oxide layer is provided on a side of the second doped microcrystalline silicon layer away from the silicon wafer in a thickness direction.

12. The back contact cell according to claim 11, characterized in that: The transparent conductive oxide layer is an ITO layer and / or a VTTO layer.

13. The back contact cell according to claim 12, characterized in that: The transparent conductive oxide layer is a hydrogen-doped ITO layer and / or a hydrogen-doped VTTO layer.

14. A photovoltaic module, characterized in that: Comprising a back contact cell according to any one of claims 1-13.

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