Back contact battery and photovoltaic module

Abstract

The utility model discloses a back contact cell and a photovoltaic assembly, and the back contact cell comprises a silicon substrate which is provided with a front surface and a back surface which are opposite to each other; the first doped crystalline silicon region and the second doped crystalline silicon region are both arranged on the back surface of the silicon substrate, and a first surface, far away from the silicon substrate, of the first doped crystalline silicon region and a second surface, far away from the silicon substrate, of the second doped crystalline silicon region are both polished surfaces; the isolation groove is used for separating the first doped crystalline silicon region from the second doped crystalline silicon region, the bottom of the isolation groove is provided with a pyramid-like first suede structure, and the distribution density of spire of the pyramid-like structure is 25 / 100 square micrometers to 80 / 100 square micrometers; and the back surface of the silicon substrate comprises overlapping areas corresponding to the first doped crystal silicon area and the second doped crystal silicon area, and the overlapping areas are polished surfaces. In the embodiment of the utility model, the flatness of the first surface and the second surface is high, the surface roughness is low, passivation is facilitated, and the passivation effect of a polished surface is obviously higher than that of a suede surface.

Description

Technical Field

[0001] The utility model relates to the technical field of photovoltaics, in particular to a back contact battery and a photovoltaic component. Background Art

[0002] Back-contact cells are cells with both positive and negative electrodes located on the back. In order to achieve higher efficiency, one way is to use tunneling oxide passivation combined with doped polysilicon to prepare efficient back-contact cells with P-type and N-type regions.

[0003] At present, when preparing the above-mentioned back contact battery, the back surface is usually textured first, and then the junction area is processed to form a cross-type BC (Back Contact) structure. The surface of the doped polysilicon area in the prepared back contact battery is a textured structure, and different doped polysilicon areas are isolated by isolation grooves.

[0004] However, the surface of the doped polysilicon region is a velvet structure, which will lead to insufficient coverage of the passivation film layer in the subsequent surface passivation process, and cannot form excellent surface passivation, and the passivation effect is poor. In addition, when the P-type and N-type doped polysilicon regions and isolation grooves are formed by the current etching process, the isolation effect and light trapping effect of the isolation grooves are poor. Utility Model Content

[0005] The utility model provides a back contact cell and a photovoltaic module, aiming at least to solve the technical problem of poor passivation effect of the back contact cell in the prior art.

[0006] In a first aspect, an embodiment of the utility model provides a back contact battery, comprising:

[0007] a silicon substrate having opposing front and back surfaces;

[0008] a first doped crystalline silicon region and a second doped crystalline silicon region, wherein the first doped crystalline silicon region and the second doped crystalline silicon region are both arranged on the back side of the silicon substrate, and a first surface of the first doped crystalline silicon region away from the silicon substrate and a second surface of the second doped crystalline silicon region away from the silicon substrate are both polished surfaces;

[0009] An isolation groove is used to separate the first doped crystalline silicon region from the second doped crystalline silicon region, the bottom of the isolation groove is provided with a first pyramid-like velvet structure, and the distribution density of the pyramid-like apex is 25 / 100 square microns to 80 / 100 square microns;

[0010] The back side of the silicon substrate includes an overlapping region corresponding to the first doped crystalline silicon region and the second doped crystalline silicon region, and the overlapping region is a polished surface.

[0011] Optionally, along the thickness direction of the back contact cell, a distance between the first doped crystalline silicon region away from the first surface of the silicon substrate and the bottom of the isolation trench is 3 microns to 6 microns.

[0012] Optionally, along the thickness direction of the back contact cell, the distance between the second doped crystalline silicon region away from the second surface of the silicon substrate and the bottom of the isolation trench is 1 micron-5 microns.

[0013] Optionally, a plurality of isolation grooves are provided, and along the arrangement direction of the plurality of isolation grooves, the width of the isolation grooves is 20 microns-150 microns.

[0014] Optionally, the isolation trench penetrates into the silicon substrate, and the depth of the isolation trench penetrating into the silicon substrate is 2.5 micrometers to 5.8 micrometers.

[0015] Optionally, the thickness of the first doped crystalline silicon region is 100 nanometers to 500 nanometers; the thickness of the second doped crystalline silicon region is 100 nanometers to 500 nanometers.

[0016] Optionally, the cross-sectional shape of the isolation groove is rectangular or trapezoidal.

[0017] Optionally, a tunneling oxide layer is further included, wherein the tunneling oxide layer is located between the silicon substrate and the first doped crystalline silicon region, and between the silicon substrate and the second doped crystalline silicon region; the thickness of the tunneling oxide layer is 0.5 nanometers to 3 nanometers.

[0018] Optionally, a second pyramid-like velvet structure is provided on the front side of the silicon substrate.

[0019] In a second aspect, an embodiment of the utility model provides a photovoltaic module, comprising a back contact cell as described in any one of the above items.

[0020] In the embodiment of the utility model, the first surface and the second surface are both polished surfaces, that is, the first surface and the second surface are both non-velvet structures. The first surface and the second surface have high flatness and low surface roughness, which is conducive to passivation. The passivation effect of the polished surface is significantly higher than the passivation effect of the velvet surface, which enhances the surface passivation performance of the PN junction area in the final back-contact battery. The polished surface can provide better protection and blocking effect during alkaline corrosion, enhances the corrosion blocking performance, and the structure of the first doped crystalline silicon area and the second doped crystalline silicon area formed is denser. In addition, after the passivation effect is improved, a certain voltage gain can be obtained, thereby improving the efficiency of the back-contact battery.

[0021] In addition, under the same wet etching process, when the distribution density of the pyramid-like spires is 25 / 100 square microns-80 / 100 square microns, the depth of the finally formed isolation groove is deeper, so as to achieve effective isolation of the first doped crystalline silicon region and the second doped crystalline silicon region, and reduce the risk of short circuit leakage in the PN junction region. In addition, when the distribution density of the pyramid-like spires at the bottom of the isolation groove is 25 / 100 square microns-80 / 100 square microns, it has a better light trapping effect, which is beneficial to improve battery efficiency. The above description is only an overview of the technical solution of the utility model. In order to more clearly understand the technical means of the utility model, it can be implemented in accordance with the contents of the specification, and in order to make the above and other purposes, features and advantages of the utility model more obvious and easy to understand, the specific implementation methods of the utility model are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 A schematic diagram of the structure of a back contact battery provided by an embodiment of the utility model;

[0023] Figure 2 A schematic diagram of the structure of an intermediate component 1 in the process of preparing a back contact battery;

[0024] Figure 3 A schematic diagram of the structure of the intermediate component 2 in the process of preparing a back contact battery;

[0025] Figure 4 A schematic diagram of the structure of the intermediate component 3 in the process of preparing a back contact battery;

[0026] Figure 5 A schematic diagram of the structure of the intermediate component 4 in the process of preparing a back contact battery;

[0027] Figure 6 Schematic diagram of the structure of intermediate component 5 in the process of preparing back contact battery.

[0028] Reference numerals:

[0029] 10-silicon substrate, 11-back side, 111-overlapping region, 12-front side, 121-second velvet structure, 20-tunneling oxide layer, 30-first doped crystalline silicon region, 31-first surface, 40-second doped crystalline silicon region, 41-second surface, 50-isolation groove, 51-first velvet structure, 60-polycrystalline silicon layer, 70-boron-doped polycrystalline silicon, 80-phosphorus-doped polycrystalline silicon, 90-laser. DETAILED DESCRIPTION

[0030] The exemplary embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be limited by the embodiments described herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present invention and to fully convey the scope of the present invention to those skilled in the art.

[0031] First, refer to Figure 1 The utility model discloses a back contact battery, comprising:

[0032] A silicon substrate 10 having a front side 12 and a back side 11 opposite to each other;

[0033] A first doped crystalline silicon region 30 and a second doped crystalline silicon region 40, both of which are arranged on the back side 11 of the silicon substrate 10, and both of which are polished surfaces.

[0034] The isolation groove 50 is used to separate the first doped crystalline silicon region 30 from the second doped crystalline silicon region 40. The bottom of the isolation groove 50 is provided with a first pyramid-like velvet structure 51. The distribution density of the pyramid-like apex is 25 / 100 square microns to 80 / 100 square microns.

[0035] The back side 11 of the silicon substrate 10 includes an overlapping region 111 corresponding to the first doped crystalline silicon region 30 and the second doped crystalline silicon region 40 , and the overlapping region 111 is a polished surface.

[0036] It should be noted that the distribution density of the above-mentioned pyramid-like spires is 25 / 100 square microns, which means that there are 25 spires distributed on every 100 square microns of the bottom area of ​​the isolation groove; the distribution density of the above-mentioned pyramid-like spires is 80 / 100 square microns, which means that there are 80 spires distributed on every 100 square microns of the bottom area of ​​the isolation groove.

[0037] Specifically, the silicon substrate 10 may be an N-type single crystal silicon wafer or a P-type single crystal silicon wafer. The back side 11 of the silicon substrate 10 is also the backlight side, and the front side 12 of the silicon substrate 10 is also the light-facing side. The first doped crystalline silicon region 30 and the second doped crystalline silicon region 40 both include polycrystalline silicon. The first doped crystalline silicon region 30 may be a P-type doped crystalline silicon region, and the P-type doped crystalline silicon region includes boron, and the concentration of boron may be 3×10 18 / cm 3 -3×10 20 / cm 3 The second doped crystalline silicon region 40 may be an N-type doped crystalline silicon region, and the N-type doped crystalline silicon region includes phosphorus, and the concentration of phosphorus may be 2×1020 / cm 3 -2×10 21 / cm 3 .

[0038] When preparing a back contact battery, a tunneling oxide layer 20 and a polysilicon layer 60 can be first deposited on the back side 11 of the silicon substrate 10, and then boron is doped in the polysilicon layer 60 to form boron-doped polysilicon 70. After laser treatment, chemical etching and other processes, a first doped crystalline silicon region 30 is finally formed. The polysilicon layer 60 can be deposited by processes such as chemical vapor deposition (CVD) or low-pressure chemical vapor deposition (LPCVD). Before depositing the polysilicon layer 60 on the back side of the silicon substrate 10, the silicon substrate 10 can be first subjected to an alkali polishing treatment to make the surface of the silicon substrate 10 smooth and clean, so that the back side 11 of the silicon substrate 10 is already a polished surface before the polysilicon layer 60 is deposited, and the overlapping area 111 in the back side 11 is a polished surface. The overlapping area 111 is specifically Figure 1 The area on the middle back surface 11 that contacts the tunnel oxide layer 20. When performing the alkali polishing treatment, an alkali solution with an alkali concentration of 10%-40% can be used.

[0039] Both the first surface 31 and the second surface 41 are polished surfaces, that is, both the first surface 31 and the second surface 41 are non-velvet structures. The first surface 31 and the second surface 41 have high flatness and low surface roughness, which is conducive to passivation. The passivation effect of the polished surface is significantly higher than the passivation effect of the velvet surface, which enhances the surface passivation performance of the PN junction region in the final back-contact battery. The polished surface can provide better protection and barrier effect during alkaline corrosion, enhances the corrosion barrier performance, and the structure of the first doped crystalline silicon region 30 and the second doped crystalline silicon region 40 formed is more compact. In addition, after the passivation effect is improved, a certain voltage gain can be obtained, thereby improving the efficiency of the back-contact battery.

[0040] The isolation groove 50 is located between the first doped crystalline silicon region 30 and the second doped crystalline silicon region 40, and is used to separate the first doped crystalline silicon region 30 from the second doped crystalline silicon region 40. The distribution density of the pyramid-like spires is 25 / 100 square microns to 80 / 100 square microns, and can be specifically 25 / 100 square microns, 30 / 100 square microns, 40 / 100 square microns, 50 / 100 square microns, 70 / 100 square microns, 80 / 100 square microns, etc. In the embodiment of the utility model, under the same wet etching process, the distribution density of the pyramid-like spires in the first velvet structure 51 is larger, and accordingly, the depth of the finally formed isolation groove 50 is deeper, so as to achieve effective isolation of the first doped crystalline silicon region 30 and the second doped crystalline silicon region 40, and reduce the risk of short circuit leakage in the PN junction region. In addition, when the distribution density of the pyramid-like spires at the bottom of the isolation groove is 25 / 100 square microns to 80 / 100 square microns, it has a good light trapping effect, which is beneficial to improving the battery efficiency.

[0041] The isolation groove 50 may be formed by a wet etching process. The etching solution used in the wet etching process includes an alkali and an auxiliary additive. The concentration of the alkali may be 2%-15%, and the alkali may specifically be potassium hydroxide, sodium hydroxide, etc. The volume ratio of the auxiliary additive is 0.5%-4%, and the components of the auxiliary additive include sodium benzoate, a defoaming agent, a surfactant, etc. The auxiliary additive plays a role in protecting the area not scanned by the laser.

[0042] Along the thickness direction of the back contact cell, the distance between the first doped crystalline silicon region 30 away from the first surface 31 of the silicon substrate 10 and the bottom of the isolation trench 50 is 3 micrometers to 6 micrometers.

[0043] Specifically, the thickness direction of the back contact battery can refer to Figure 1 In the direction indicated by the arrow, the distance between the first surface 31 and the bottom of the isolation groove 50 can be referred to Figure 1 As shown in H1, the distance H1 between the first surface 31 and the bottom of the isolation groove 50 is 3 microns-6 microns, and can be specifically 3 microns, 3.5 microns, 4 microns, 5 microns, 5.5 microns, 6 microns, etc. When the distance between the first surface 31 of the first doped crystalline silicon region 30 and the bottom of the isolation groove 50 is within the above range, the depth of the isolation groove 50 can be guaranteed, so that the first doped crystalline silicon region 30 and the second doped crystalline silicon region 40 can be better isolated.

[0044] Along the thickness direction of the back contact cell, the distance between the second doped crystalline silicon region 40 away from the second surface 41 of the silicon substrate 10 and the bottom of the isolation trench 50 is 1 micrometer to 5 micrometers.

[0045] Specifically, the distance between the second surface 41 and the bottom of the isolation groove 50 can be referred to Figure 1The distance H2 shown in FIG. 1 between the second surface 41 and the bottom of the isolation trench 50 may be 1 μm to 5 μm.

[0046] Specifically, it can be 1 micron, 2 microns, 3 microns, 3.5 microns, 4 microns, 5 microns, etc. When the distance between the second surface 41 of the second doped crystalline silicon region 40 and the bottom of the isolation groove 50 is within the above range, the depth of the isolation groove 50 can be guaranteed, so that the first doped crystalline silicon region 30 and the second doped crystalline silicon region 40 can be better isolated.

[0047] A plurality of isolation grooves 50 are provided, and along the arrangement direction of the plurality of isolation grooves 50 , the width of the isolation grooves 50 is 20 micrometers to 150 micrometers.

[0048] Specifically, the arrangement direction of the plurality of isolation grooves 50 can refer to Figure 1 In the direction indicated by the arrow B, the width of the isolation groove 50 can be referred to Figure 1 As shown in FIG. 1 , the width W1 of the isolation trench 50 is specifically the width of the bottom of the isolation trench 50. The width W1 of the isolation trench 50 is 20 micrometers to 150 micrometers, and specifically can be 20 micrometers, 25 micrometers, 39 micrometers, 63 micrometers, 100 micrometers, 150 micrometers, etc. When the width of the isolation trench 50 is within the above range, effective isolation of the first doped crystalline silicon region 30 and the second doped crystalline silicon region 40 can be ensured.

[0049] The isolation trench 50 penetrates into the silicon substrate 10 , and the depth of the isolation trench 50 penetrating into the silicon substrate 10 is 2.5 micrometers to 5.8 micrometers.

[0050] Specifically, the depth of penetration is the distance between the bottom of the isolation groove 50 and the back surface 11 of the silicon substrate 10 along the thickness direction of the back contact cell. The depth of the isolation groove 50 penetrating into the silicon substrate 10 is 2.5 microns to 5.8 microns, and can be 2.5 microns, 3 microns, 3.5 microns, 4 microns, 4.5 microns, 5.8 microns, etc. When the depth of the isolation groove 50 penetrating into the silicon substrate 10 is within the above range, the depth of the isolation groove 50 can be guaranteed, so that the first doped crystalline silicon region 30 and the second doped crystalline silicon region 40 can be better isolated.

[0051] The thickness of the first doped crystalline silicon region 30 is 100 nanometers to 500 nanometers, and the thickness of the second doped crystalline silicon region 40 is 100 nanometers to 500 nanometers. The thickness of the second doped crystalline silicon region 40 may be equal to or different from the thickness of the first doped crystalline silicon region 30 .

[0052] The cross-sectional shape of the isolation groove 50 is rectangular or trapezoidal. The cross-sectional shape of the isolation groove 50 is preferably trapezoidal. The cross-sectional shape of the isolation groove 50 specifically refers to the cross-sectional shape perpendicular to the extension direction of the isolation groove 50. When the cross-sectional shape of the isolation groove 50 is rectangular or trapezoidal, the shape is simple and easy to prepare.

[0053] The back contact cell provided by the embodiment of the utility model further includes a tunneling oxide layer 20, which is located between the silicon substrate 10 and the first doped crystalline silicon region 30, and between the silicon substrate 10 and the second doped crystalline silicon region 40; the thickness of the tunneling oxide layer 20 is 0.5 nanometers to 3 nanometers.

[0054] Specifically, when preparing a back contact cell, a tunnel oxide layer 20 is first deposited on the back side 11 of the silicon substrate 10, and then a polysilicon layer 60 is deposited. The thickness of the tunnel oxide layer 20 can be 0.5 nm, 1 nm, 1.2 nm, 1.8 nm, 2.5 nm, 3 nm, etc.

[0055] The front surface 12 of the silicon substrate 10 is provided with a second pyramid-like textured structure 121 .

[0056] Specifically, during preparation, the front surface 12 of the silicon substrate 10 can be firstly subjected to acid etching to remove the oxide layer on the front surface 12. After the oxide layer is removed, a wet etching process is used to form the second velvet structure 121. The second velvet structure 121 can reduce the reflectivity of the front surface 12 of the silicon substrate 10.

[0057] The specific preparation process of the back contact battery provided by the embodiment of the utility model is, for example:

[0058] S1, providing a silicon substrate 10. The silicon substrate 10 may be an N-type single crystal silicon wafer or a P-type single crystal silicon wafer.

[0059] S2, polishing the silicon substrate 10. Specifically, an alkali solution with an alkali concentration of 10%-40% can be used to perform alkali polishing on the silicon substrate 10 to make the surface of the silicon substrate 10 smooth and clean.

[0060] S3, depositing a tunnel oxide layer 20 and a polysilicon layer 60 on the polished silicon substrate 10, and the structure after deposition is as shown in FIG. Figure 2 The intermediate component 1 is shown in FIG. 1 , wherein the thickness of the deposited tunnel oxide layer 20 is 0.5 nanometers to 3 nanometers, and the thickness of the deposited polysilicon layer 60 is 100 nanometers to 500 nanometers.

[0061] S4, doping the deposited polysilicon layer 60, the doped elements are not limited to acceptor impurities such as boron and phosphorus and donor impurities, the boron doping concentration can be 3×10 18 / cm 3 -3×10 20 / cm 3 , the phosphorus doping concentration is 2×10 20 / cm 3 -2×10 21 / cm 3In this step, boron is preferably doped to form boron-doped polysilicon 70 .

[0062] S5, laser film opening is performed. Laser film opening is to use laser energy to perform graphic processing on the surface of a specific silicon wafer. The position of the laser 90 scanning can be referred to Figure 3 The laser 90 is obtained by a laser, which may be a nanosecond, picosecond, or femtosecond laser, the power of the laser may be 10W-60W, and the diameter of the laser spot may be 50 microns-300 microns.

[0063] S6, perform wet etching treatment, wherein the position scanned by the laser 90 will be corroded, and the position not scanned by the laser 90 will not be corroded. The etching solution used in this step includes alkali and auxiliary additives, and the concentration of the alkali can be 4%-20%. The alkali can be specifically potassium hydroxide, sodium hydroxide, etc. The volume ratio of the auxiliary additives is 0.5%-5%, and the components of the auxiliary additives include sodium benzoate, defoaming agent, surfactant, etc. The auxiliary additives play a role in protecting the areas that have not been scanned by the laser to ensure the polishing of the surface. The wet etching process is carried out in sections in different liquid tanks with different chemical formulas and different cleaning functions. During the wet etching process, the temperature can be 65℃-85℃, the process time can be 50s-300s, and the corrosion depth can be 0.5 microns-3 microns. The structure after wet etching refers to Figure 4 The middle piece three shown in FIG. 1 has a slot formed therein.

[0064] S7, preparing another different doped polysilicon. When boron is doped in S4, phosphorus-doped polysilicon is prepared in this step. When preparing phosphorus-doped polysilicon, a tunnel oxide layer and a polysilicon layer can be deposited again, and then the deposited polysilicon layer is doped with phosphorus, thereby preparing phosphorus-doped polysilicon 80. The phosphorus doping concentration is 2×10 20 / cm 3 -2×10 21 / cm 3 Another different structure of doped polysilicon after preparation is shown in Figure 2. Figure 5 The middleware four is shown in FIG.

[0065] S8 , performing acid etching on the front surface 12 of the silicon substrate 10 to remove the oxide layer on the front surface 12 .

[0066] S9, laser film opening is performed again. The position of the laser 90 scanning can be referred to Figure 6 The laser 90 is obtained by a laser, which may be a nanosecond, picosecond, or femtosecond laser, the power of the laser may be 10W-100W, and the diameter of the laser spot may be 50 microns-350 microns.

[0067] S10, wet etching is performed on the front and back sides to form a velvet surface on the front side, a polished surface on the doped crystalline silicon area on the back side, and a first velvet structure similar to a pyramid is formed at the bottom of the isolation groove on the back side. The distribution density of the pyramid-like spires is 25 / 100 square microns to 80 / 100 square microns. Among them, the position scanned by the laser 90 will be corroded, and the position not scanned by the laser 90 will not be corroded or will be more corrosion-resistant. The etching liquid used for the velvet and wet etching in this step includes alkali and auxiliary additives. The concentration of the alkali can be 2%-15%, and the alkali can be specifically potassium hydroxide, sodium hydroxide, etc. The volume ratio of the auxiliary additive is 0.5%-4%, and the components of the auxiliary additive include sodium benzoate, defoaming agent, surfactant, etc. The auxiliary additive plays a role in protecting the area not scanned by the laser to ensure the polishing of the phosphorus-doped polysilicon surface. The wet etching process is carried out in sections in different liquid tanks with different chemical formulas and different cleaning functions. During the wet etching process, the temperature may be 55°C-85°C, the process time may be 40s-400s, and the etching depth may be 1 micron-5 microns to ensure the depth of the finally formed isolation groove 50 and the distribution density of the pyramid-like spires at the bottom of the isolation groove 50. Figure 1 The structure shown in .

[0068] S11, performing subsequent surface passivation and metallization processes to prepare a back contact battery.

[0069] In a second aspect, the embodiment of the utility model further discloses a photovoltaic module, comprising any of the above-mentioned back-contact batteries. Since the photovoltaic module comprises the above-mentioned back-contact batteries, it also has the beneficial effects of the above-mentioned back-contact batteries, which will not be described in detail here.

[0070] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0071] The embodiments of the utility model are described above in conjunction with the accompanying drawings, but the utility model is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the enlightenment of the utility model, ordinary technicians in this field can also make many forms without departing from the scope of protection of the utility model and the claims, which all fall within the protection of the utility model.

Claims

1. A back contact battery, characterized in that: include: a silicon substrate having opposing front and back surfaces; a first doped crystalline silicon region and a second doped crystalline silicon region, wherein the first doped crystalline silicon region and the second doped crystalline silicon region are both arranged on the back side of the silicon substrate, and a first surface of the first doped crystalline silicon region away from the silicon substrate and a second surface of the second doped crystalline silicon region away from the silicon substrate are both polished surfaces; An isolation groove is used to separate the first doped crystalline silicon region from the second doped crystalline silicon region, the bottom of the isolation groove is provided with a first pyramid-like velvet structure, and the distribution density of the pyramid-like apex is 25 / 100 square microns to 80 / 100 square microns; The back side of the silicon substrate includes an overlapping region corresponding to the first doped crystalline silicon region and the second doped crystalline silicon region, and the overlapping region is a polished surface.

2. The back contact cell according to claim 1, characterized in that: Along the thickness direction of the back contact cell, the distance between the first doped crystalline silicon region away from the first surface of the silicon substrate and the bottom of the isolation trench is 3 microns to 6 microns.

3. The back contact cell according to claim 1, characterized in that: Along the thickness direction of the back contact cell, the distance between the second doped crystalline silicon region away from the second surface of the silicon substrate and the bottom of the isolation trench is 1 micron to 5 microns.

4. The back contact cell according to claim 1, characterized in that: A plurality of isolation grooves are provided, and along the arrangement direction of the plurality of isolation grooves, the width of the isolation grooves is 20 micrometers to 150 micrometers.

5. The back contact cell according to claim 1, characterized in that: The isolation groove penetrates into the silicon substrate, and the depth of the isolation groove penetrating into the silicon substrate is 2.5 micrometers to 5.8 micrometers.

6. The back contact cell according to claim 1, characterized in that: The thickness of the first doped crystalline silicon region is 100 nanometers to 500 nanometers; the thickness of the second doped crystalline silicon region is 100 nanometers to 500 nanometers.

7. The back contact cell according to claim 1, characterized in that: The cross-sectional shape of the isolation groove is rectangular or trapezoidal.

8. The back contact cell according to claim 1, characterized in that: It also includes a tunneling oxide layer, which is located between the silicon substrate and the first doped crystalline silicon region, and between the silicon substrate and the second doped crystalline silicon region; the thickness of the tunneling oxide layer is 0.5 nanometers to 3 nanometers.

9. The back contact cell according to claim 1, characterized in that: A second pyramid-like velvet structure is provided on the front side of the silicon substrate.

10. A photovoltaic module, characterized in that: A back contact battery comprising the battery described in any one of claims 1 to 9.

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