Integrated mainboard supporting on-line nuclear power voltage adjustment

Abstract

An integrated mainboard supporting on-line nuclear power voltage adjustment comprises a SW SW-WY831 processor, a complex programmable logic device, an IO expansion chip and a PCIe switch, the PCIe switch is electrically connected with the IO expansion chip, the SW SW-WY831 processor and a network controller through different PCIe 3.0 buses, the SW SW-WY831 processor is electrically connected with the complex programmable logic device through a UART bus, and the complex programmable logic device is electrically connected with the IO expansion chip. The SW SW-WY831 processor is further electrically connected with the complex programmable logic device, the electrically erasable programmable read-only memory and the real-time clock through different IIC buses, the SW SW-WY831 processor is further electrically connected with the memory particles through a DDR4 bus, and the SW SW-WY831 processor is further electrically connected with the BIOS storage chip through an SPI bus. And the complex programmable logic device is electrically connected with the nuclear power control chip through a power management bus. According to the invention, the monitoring of the voltage and current of the nuclear power control chip and the online modification of the nuclear power voltage are realized, the equipment package does not need to be disassembled, the efficiency is improved, and the debugging cost is reduced.

Description

Technical Field

[0001] One or more embodiments of this specification relate to component equipment technology, and more particularly, to an integrated motherboard that supports online adjustment of nuclear power voltage. Background Art

[0002] With the development of the times and the expansion of application services, integrated motherboards often need to improve CPU performance through overclocking. However, the system architecture of many integrated motherboards has not been updated with the change of demand and cannot support overclocking. In addition, for some integrated motherboards, although they can support overclocking, if you want to adjust the overclocked hertz, you need to adjust the nuclear power voltage at the same time. The integrated motherboards that currently support overclocking cannot adjust the nuclear power voltage online. You need to disassemble the equipment to directly connect and adjust the nuclear power voltage chip on the integrated motherboard, which is very cumbersome and time-consuming. Frequent disassembly will also reduce the life of the equipment and increase costs. Utility Model Content

[0003] In order to solve the above problems, one or more embodiments of this specification describe an integrated motherboard that supports online adjustment of nuclear power voltage.

[0004] According to a first aspect, an integrated motherboard supporting online adjustment of nuclear power voltage is provided, the integrated motherboard comprising: a Shenwei SW-WY831 processor, a complex programmable logic device, an IO expansion chip and a PCIe switch, the PCIe switch being electrically connected to the IO expansion chip, the Shenwei SW-WY831 processor and the network controller through different PCIe3.0 buses, the Shenwei SW-WY831 processor being electrically connected to the complex programmable logic device through a UART bus, the Shenwei SW-WY831 processor being electrically connected to the complex programmable logic device, the electrically erasable programmable read-only memory and the real-time clock through different IIC buses, the Shenwei SW-WY831 processor being electrically connected to memory particles through a DDR4 bus, the Shenwei SW-WY831 processor being electrically connected to a BIOS storage chip through an SPI bus, the Shenwei SW-WY831 processor being electrically connected to a graphics card through a PCIe3.0 bus, and the complex programmable logic device being electrically connected to a nuclear power control chip through a power management bus.

[0005] Preferably, the PCIe switch is electrically connected to the network controller and the IO expansion chip respectively through the PCIe3.0 buses set on different PCIex4 slots, and the Shenwei SW-WY831 processor is electrically connected to the PCIe switch and the graphics card respectively through the PCIe3.0 buses set on different PCIex8 slots.

[0006] Preferably, the PCIe switch is electrically connected to the M.2 Key E interface and the MINI PCIe interface respectively through the PCIe3.0 bus set on different PCIex1 slots, and the PCIe switch is electrically connected to the first M.2 Key M interface through the PCIe3.0 bus set on the PCIex8 slot.

[0007] Preferably, the network controller is also electrically connected to the RJ45 network interface via an MDI bus.

[0008] Preferably, the IO expansion chip is electrically connected to the Audio chip and the USB2.0 interface through different USB2.0 buses, the IO expansion chip is also electrically connected to the USB3.0 interface through a USB3.0 bus, and the IO expansion chip is also electrically connected to the second M.2 Key M interface and the SATA3.0 interface through different SATA3.0 buses.

[0009] Preferably, the Audio chip is also electrically connected to the power amplifier chip and the headset through different L / R buses.

[0010] Preferably, the complex programmable logic device is also electrically connected to the RS232 transceiver chip via a UART bus.

[0011] Preferably, the complex programmable logic device is also electrically connected to the temperature measurement chip via an IIC bus, and the complex programmable logic device is also electrically connected to the controller via an IO bus.

[0012] Preferably, the integrated mainboard also includes a monitoring management chip, and the monitoring management chip is arranged on the PCB board.

[0013] The motherboard provided in the embodiment of this specification uses the Shenwei SW-WY831 processor that supports the overclocking function as the CPU. In addition to the UART bus, the Shenwei SW-WY831 processor is electrically connected to the complex programmable logic device through the IIC bus, and the complex programmable logic device is electrically connected to the nuclear power control chip through the power management bus, so that the user can directly interact with the complex programmable logic device online by accessing the development function of the CPU, realize the monitoring of the voltage and current of the nuclear power control chip and modify the nuclear power voltage online without disassembling the equipment package, thereby improving efficiency and reducing debugging costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0015] Figure 1 It is a schematic diagram of the architecture of an integrated mainboard supporting online adjustment of nuclear power voltage in one embodiment of this specification. DETAILED DESCRIPTION

[0016] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application.

[0017] In the following introduction, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance. The following introduction provides multiple embodiments of the present application, and different embodiments can be replaced or combined, so the present application can also be considered to include all possible combinations of the same and / or different embodiments recorded. Therefore, if one embodiment includes features A, B, and C, and another embodiment includes features B and D, then the present application should also be considered to include embodiments containing one or more of all other possible combinations of A, B, C, and D, although the embodiment may not be clearly recorded in the following text.

[0018] The following description provides examples and does not limit the scope, applicability or examples set forth in the claims. Changes may be made to the functions and arrangements of the elements described without departing from the scope of the present application. Various processes or components may be appropriately omitted, substituted or added to each example. For example, the described method may be performed in an order different from the order described, and various steps may be added, omitted or combined. In addition, features described in some examples may be combined in other examples.

[0019] See also Figure 1 , Figure 1It is a schematic diagram of the architecture of an integrated motherboard supporting online adjustment of nuclear power voltage provided by an embodiment of the present application. In an embodiment of the present application, the integrated motherboard includes: a Shenwei SW-WY831 processor, a complex programmable logic device, an IO expansion chip and a PCIe switch, the PCIe switch is electrically connected to the IO expansion chip, the Shenwei SW-WY831 processor and the network controller through different PCIe3.0 buses, the Shenwei SW-WY831 processor is electrically connected to the complex programmable logic device through the UART bus, the Shenwei SW-WY831 processor is also electrically connected to the complex programmable logic device, the electrically erasable programmable read-only memory and the real-time clock through different IIC buses, the Shenwei SW-WY831 processor is also electrically connected to the memory particles through the DDR4 bus, the Shenwei SW-WY831 processor is also electrically connected to the BIOS storage chip through the SPI bus, the Shenwei SW-WY831 processor is also electrically connected to the graphics card through the PCIe3.0 bus, and the complex programmable logic device is electrically connected to the nuclear power control chip through the power management bus.

[0020] In the embodiments of this specification, the CPU will use the Shenwei SW-WY831 processor, which supports overclocking function, with a main frequency of not less than 2.5GHz, and has 8 computing cores integrated inside, which can be overclocked to 3.0GHz at most to improve CPU performance. The PCIe switch (Peripheral Component Interconnect Express Switch, PCIe Switch) is connected to the CPU and is used for PCIe3.0 bus expansion. Specifically, Shenzhen Guowei Electronics SM8748 can be used. SM8748 is a PCIe 3.0 switch with 48 channels and up to 12 ports, which can realize data exchange between ports. The IO expansion chip is used for IO expansion. Specifically, Shanghai Zhaoxin ZX-200 can be used. ZX-200 is connected to SM8748 uplink, and the downlink can be expanded according to different needs, such as USB3.0, USB2.0, SATA3.0, etc. Complex Programmable Logic Device (CPLD) is used for fan control, power-on timing control, chip reset control, level conversion, power status monitoring and other functions. Specifically, you can choose Shenzhen Ziguang Tongchuang PGC4KD-6C MBG324. The number of user IOs of PGC4KD-6C MBG324 is 280pin, and the logic resources are equivalent to 4761 LUT4s, supporting different types of IO interfaces and a variety of embedded hard cores. The graphics card can be Changsha Jingjiawei's JM7200 and JM9230 series graphics cards, which are connected to the CPU through the PCIe3.0 bus. Choosing this series of graphics cards can enable the GPU chip inside to support VGA / HDMI / DVI video output. The memory particles can be specifically Hefei Changxin storage particles CXDQ3A8AM-IJ-A. There are two DDR4 controllers integrated in the Shenwei SW-WY831 processor. Each controller corresponds to a DDR4 storage interface with a 64-bit data width. The interface supports "64-bit data + 8-bit check code" ECC check (can correct single errors and detect double errors), and the maximum data transmission rate can reach 3200Mbps. The capacity of a single particle of CXDQ3A8AM-IJ-A is 8Gb. Each DDR4 channel of the CPU is connected to 8 CXDQ3A8AM-IJ-A, and 1 CXDQ3A8AM-IJ-A is used for ECC check to achieve a single-board memory capacity of 16GB.The Electrically Erasable Programmable Read-Only Memory (EEPROM) can be selected from Shanghai Belling BL24C02A, with a storage capacity of 2k bit, which is used to store memory SPD (Serial Presence Detect) information, including memory manufacturer, operating frequency, operating voltage, speed, capacity, row address, column address and other information. The CPU reads information from the EEPROM through the IIC interface. The Basic Input Output System (BIOS) memory chip can be selected from GigaDevice GD25LB64C, with a storage capacity of 64Mbit. The CPU reads the startup information from the BIOS chip through the SPI interface. The network controller can be selected from Wuxi Muchuang N500L-AM2, which is connected to the CPU through the PCIe3.0 bus uplink, and can expand 2 Gigabit network ports downlink. The Real-Time Clock (RTC) can be selected from Guangdong Dapu Technology INS5902A, which has a built-in 32.768KHz crystal. The CPU reads the real-time clock from the RTC chip through the IIC interface. The nuclear power control chip may specifically be an Intel control chip, through which the current nuclear power voltage can be determined.

[0021] The CPU and CPLD will be connected through the IIC bus and UART bus respectively. The IIC bus uses a synchronous communication protocol to ensure the synchronization of data transmission. The UART bus uses an asynchronous serial communication protocol. Both parties synchronize data transmission through a pre-agreed baud rate. According to actual needs and different transmission data, different buses can be selected for data transmission. In the acquisition of nuclear power voltage, in order to ensure real-time effectiveness, the IIC bus will be preferred for data transmission. After the CPLD is connected to the nuclear power control chip through the Power Management Bus (PMBUS), it can monitor the voltage and current of the nuclear power control chip. The CPU is connected to the CPLD through the IIC bus, so that users can interact with the CPLD online in the development function under the CPU system, and then complete the function of modifying the nuclear power voltage online.

[0022] It should be noted that the specific process of obtaining voltage and current, as well as the process of regulating voltage through control instructions, are well-known technologies familiar to technical personnel in this field, and the focus of this application is not the algorithm / program itself involved in the above-mentioned technology, but the system as a whole that can realize these functions through the above-mentioned connection relationship. Therefore, the specific implementation process of the above-mentioned algorithm / program will not be described in detail here.

[0023] In one possible implementation, the PCIe switch is electrically connected to the network controller and the IO expansion chip respectively through the PCIe3.0 bus set on different PCIex4 slots, and the Shenwei SW-WY831 processor is electrically connected to the PCIe switch and the graphics card respectively through the PCIe3.0 bus set on different PCIex8 slots.

[0024] In the embodiments of this specification, PCIe slots are set on both the PCIe switch and the CPU, which can be divided into PCIex1, PCIex2, PCIex4, PCIex8, etc. according to the number of data channels provided. Different configurations provide different bandwidths, which will affect the data transmission rate of the connected devices. According to the actual specific bandwidth usage requirements, the network controller and IO expansion chip will be connected through PCIex4, and the PCIe switch and graphics card will be connected through PCIex8.

[0025] In one possible implementation, the PCIe switch is electrically connected to the M.2 Key E interface and the MINI PCIe interface respectively through the PCIe3.0 bus set on different PCIex1 slots, and the PCIe switch is electrically connected to the first M.2 Key M interface through the PCIe3.0 bus set on the PCIex8 slot.

[0026] In the embodiments of this specification, the M.2 Key M interface is an interface mainly used for high-performance solid-state drives (SSDs), especially SSDs that support the NVMe protocol. The Key M interface can provide a PCIe ×4 connection, which can theoretically achieve higher data transfer speeds and is very suitable for application scenarios that require high-speed storage. The first M.2 Key M interface can specifically use the NVMe high-speed storage protocol to achieve low-latency and high-bandwidth data transfer. The M.2 Key E interface is mainly used for wireless network cards and other similar wireless connection devices, such as Wi-Fi, Bluetooth, NFC or GNSS modules.

[0027] In one possible implementation, the network controller is also electrically connected to the RJ45 network interface via an MDI bus.

[0028] In the embodiment of this specification, the network controller is also externally connected to an RJ45 network interface to connect to an external network, and the specific model thereof can be AVIC Optronics JHC116601.

[0029] In one possible implementation, the IO expansion chip is electrically connected to the Audio chip and the USB2.0 interface respectively through different USB2.0 buses, the IO expansion chip is also electrically connected to the USB3.0 interface through a USB3.0 bus, and the IO expansion chip is also electrically connected to the second M.2 Key M interface and the SATA3.0 interface respectively through different SATA3.0 buses.

[0030] In the embodiment of this specification, the downstream of the IO expansion chip can expand 5 USB3.0, 6 USB2.0, and 4 SATA3.0. Specifically, in addition to being used for external USB2.0 interfaces, the USB2.0 bus will also be connected to an Audio chip to output audio signals. The Audio chip can be Wuhan Guanghuaxin CJC6811A. The USB3.0 bus will be mainly used for external USB3.0 interfaces. In addition to external SATA3.0 interfaces, the SATA3.0 bus will also be connected to the second M.2 Key M interface. The second M.2 Key M interface can specifically adopt the SATA protocol.

[0031] In one possible implementation manner, the Audio chip is also electrically connected to the power amplifier chip and the headset through different L / R buses.

[0032] In the embodiments of this specification, the audio chip outputs audio signals to connect to headphones and microphone sockets, and can also be switched to the Naxinwei NS4252 amplifier chip to drive the speakers.

[0033] In one possible implementation, the complex programmable logic device is also electrically connected to the RS232 transceiver chip via a UART bus.

[0034] In the embodiments of this specification, the RS232 transceiver chip can specifically be Hunan Xinlite SIT3232E, which is used for CPU serial port debugging.

[0035] In one possible implementation, the complex programmable logic device is also electrically connected to the temperature measurement chip via an IIC bus, and the complex programmable logic device is also electrically connected to the controller via an IO bus.

[0036] In the embodiments of this specification, the temperature measurement chip can be specifically selected from Nanochip NST175, and the CPLD reads the temperature data of NS175 through IIC to make the fan strategy of the whole board. The controller can be a PLC controller. The CPLD is connected to the controller through IO, and can realize monitoring functions such as monitoring the health status, temperature, voltage, fan, etc. of various levels of power supply, and can upload the monitoring data to the CPU system through the UART bus.

[0037] In one possible implementation, the integrated mainboard further includes a monitoring management chip, and the monitoring management chip is disposed on a PCB board.

[0038] In the embodiment of this specification, the monitoring management chip is soldered on the PCB board. The model of the monitoring management chip may be W83795G, which is used to provide an abnormal alarm function for the monitoring signal to improve stability.

[0039] The above is only an exemplary embodiment of the present disclosure, and the scope of the present disclosure cannot be limited thereto. That is, any equivalent changes and modifications made according to the teachings of the present disclosure are still within the scope of the present disclosure. After considering the specification and practicing the disclosure here, those skilled in the art will easily think of the implementation scheme of the present disclosure. This application is intended to cover any modification, use or adaptation of the present disclosure, which follows the general principles of the present disclosure and includes common knowledge or customary technical means in the technical field not recorded in the present disclosure. The description and examples are regarded as exemplary only, and the scope and spirit of the present disclosure are defined by the claims.

Claims

1. An integrated motherboard supporting online adjustment of nuclear power voltage, characterized in that: The integrated motherboard includes: a Shenwei SW-WY831 processor, a complex programmable logic device, an IO expansion chip and a PCIe switch. The PCIe switch is electrically connected to the IO expansion chip, the Shenwei SW-WY831 processor and the network controller through different PCIe3.0 buses. The Shenwei SW-WY831 processor is electrically connected to the complex programmable logic device through a UART bus. The Shenwei SW-WY831 processor is also electrically connected to the complex programmable logic device, the electrically erasable programmable read-only memory and the real-time clock through different IIC buses. The Shenwei SW-WY831 processor is also electrically connected to the memory particles through a DDR4 bus. The Shenwei SW-WY831 processor is also electrically connected to the BIOS storage chip through an SPI bus. The Shenwei SW-WY831 processor is also electrically connected to the graphics card through a PCIe3.0 bus. The complex programmable logic device is electrically connected to the nuclear power control chip through a power management bus.

2. The integrated motherboard according to claim 1, characterized in that: The PCIe switch is electrically connected to the network controller and the IO expansion chip respectively through the PCIe3.0 bus set on different PCIex4 slots, and the Shenwei SW-WY831 processor is electrically connected to the PCIe switch and the graphics card respectively through the PCIe3.0 bus set on different PCIex8 slots.

3. The integrated motherboard according to claim 1, characterized in that: The PCIe switch is electrically connected to the M.2 Key E interface and the MINI PCIe interface respectively through the PCIe3.0 bus set on different PCIex1 slots, and the PCIe switch is electrically connected to the first M.2 Key M interface through the PCIe3.0 bus set on the PCIex8 slot.

4. The integrated motherboard according to claim 1, characterized in that: The network controller is also electrically connected to the RJ45 network interface via the MDI bus.

5. The integrated motherboard according to claim 1, characterized in that: The IO expansion chip is electrically connected to the Audio chip and the USB2.0 interface through different USB2.0 buses, the IO expansion chip is also electrically connected to the USB3.0 interface through a USB3.0 bus, and the IO expansion chip is also electrically connected to the second M.2 Key M interface and the SATA3.0 interface through different SATA3.0 buses.

6. The integrated motherboard according to claim 5, characterized in that: The Audio chip is also electrically connected to the power amplifier chip and the headset through different L / R buses.

7. The integrated motherboard according to claim 1, characterized in that: The complex programmable logic device is also electrically connected to the RS232 transceiver chip via a UART bus.

8. The integrated motherboard according to claim 1, characterized in that: The complex programmable logic device is also electrically connected to the temperature measurement chip through the IIC bus, and the complex programmable logic device is also electrically connected to the controller through the IO bus.

9. The integrated motherboard according to claim 1, characterized in that: The integrated mainboard also includes a monitoring management chip, and the monitoring management chip is arranged on the PCB board.

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