Semiconductor structure
By designing the interlaced comb tooth structure and the semiconductor structure of the entire row of test holes, the problem of difficult detection of metal bridge defects in integrated circuits is solved, and higher detection accuracy and faster testing efficiency are achieved.
Patent Information
- Application Number
- CN202420908593.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-04-28
- Publication Date
- 2025-03-14
- Estimated Expiration
- 2034-04-28
AI Technical Summary
In the metal interconnect structure of integrated circuits, the dielectric layer between the trenches caused by the double Damascus process becomes thinner, making metal bridge defects prone to occur, but the existing test structures are difficult to accurately detect these defects.
A semiconductor structure is designed, including a first and a second test piece, including a plurality of first and second comb tooth structures, respectively, arranged interlacedly, and a test hole structure is arranged in the entire row on these comb tooth structures. This structure can accurately detect metal bridge defects by adjusting the shape and proportion of comb teeth and test holes.
This semiconductor structure can effectively detect metal bridge defects, reduce detection randomness, improve detection accuracy, and speed up the testing efficiency of the chip.
Smart Images
Figure CN222619760U_ABST
Abstract
Description
Technical Field
[0001] The utility model belongs to the technical field of semiconductors, and particularly relates to a semiconductor structure. Background Art
[0002] With the advancement of technology, the requirements for integrated circuit manufacturing processes are increasing day by day. A key parameter that characterizes the integrated circuit manufacturing process is the minimum feature size, namely the critical dimension (CD). The reduction of the critical dimension indicates that the integration of the integrated circuit increases and the size of the integrated circuit decreases.
[0003] As the critical dimensions shrink, the dual damascene process is used to make the back-end metal layer in the metal interconnect structure of integrated circuits. When forming the dual damascene structure, the process characteristics of etching the trench first and then the via hole are required, which leads to the thinning of the dielectric layer between the trenches, and the metal bridge defect is prone to occur. Conventional test structures are difficult to detect such defects and determine the location of the defects. Utility Model Content
[0004] The purpose of the utility model is to provide a semiconductor structure. Through the semiconductor structure provided by the utility model, metal bridge defects in a structure containing through holes can be detected, the randomness of the detection can be reduced, and the test efficiency of the chip can be accelerated.
[0005] In order to solve the above technical problems, the utility model provides a semiconductor structure, comprising:
[0006] A first test piece, comprising a plurality of first comb tooth structures;
[0007] A second test piece, comprising a plurality of second comb tooth structures, wherein the second comb tooth structures are arranged alternately with the first comb tooth structures; and
[0008] The test hole structure is arranged in a row on the first comb tooth structure and the second comb tooth structure.
[0009] In an embodiment of the present invention, the first comb tooth structure and the second comb tooth structure are equal in shape and size.
[0010] In an embodiment of the present invention, the ratio of the width of the first comb-tooth structure to the width of the testing hole structure is 1.4:1 to 2:1.
[0011] In an embodiment of the present invention, the ratio of the length of the first comb tooth structure to the length of the testing hole structure is 1.1:1 to 1.3:1.
[0012] In an embodiment of the present invention, the area ratio of a single test hole structure to a single first comb tooth structure or a single second comb tooth structure is 45% to 70%.
[0013] In an embodiment of the present invention, the ratio of the thickness of the first comb-tooth structure or the second comb-tooth structure to the thickness of the testing hole structure is 0.8:1 to 1.3:1.
[0014] In an embodiment of the present invention, the first test piece further includes a first handle, and a plurality of the first comb tooth structures are vertically arranged on the first handle.
[0015] In one embodiment of the present invention, the second test piece further includes a second handle, and a plurality of the second comb tooth structures are vertically arranged on the second handle.
[0016] In an embodiment of the present invention, the openings of the first test piece and the second test piece are opposite to each other, and the second handle is arranged in parallel with the first handle.
[0017] In an embodiment of the present invention, a first test pad is provided on the end of the first handle, and a second test pad is provided on the end of the second handle. The first test pad and the second test pad are centrally symmetrically distributed.
[0018] In summary, the utility model provides a semiconductor structure. The unexpected technical effect of the present application is that it solves the problem of being unable to measure the metal bridging defects that may occur in the dual Damascus structure due to the through-hole problem, reduces the randomness of the detection, can detect the defects caused by the weakest point, and improves the detection accuracy; the entire semiconductor structure tests the types of defects that may exist in the chip in the analysis area and the severity of the defects, and can be widely used in various chips to speed up the testing efficiency of the chip.
[0019] Of course, any product implementing the present invention does not necessarily need to achieve all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] In order to more clearly illustrate the technical solutions of the embodiments of the utility model, the drawings required for describing the embodiments are briefly introduced below. Obviously, the drawings described below are only some embodiments of the utility model. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0021] Figure 1 FIG. 1 is a schematic diagram of a semiconductor structure in an embodiment of the present invention.
[0022] Figure 2 for Figure 1Cross-sectional view along the AA direction.
[0023] Figure 3 for Figure 1 Cross-sectional view along direction BB.
[0024] Figure 4 for Figure 3 Cross-sectional view when the groove is formed.
[0025] Figure 5 for Figure 3 A cross-sectional view that defines the location of the vias in the trench.
[0026] Description of labels:
[0027] 100, substrate; 101, dielectric layer; 110, first photoresist; 120, groove; 130, second photoresist; 10, first test piece; 11, first handle; 12, first comb tooth structure; 13, first test pad; 20, second test piece; 21, second handle; 22, second comb tooth structure; 23, second test pad; 30, test hole structure. DETAILED DESCRIPTION
[0028] The following will be combined with the drawings in the embodiments of the utility model to clearly and completely describe the technical solutions in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments of the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.
[0029] It should be noted that the illustrations provided in this embodiment are only used to schematically illustrate the basic concept of the present invention. Therefore, the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.
[0030] In the present invention, it should be noted that, if the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. appear, the orientation or position relationship indicated is based on the orientation or position relationship shown in the drawings, which is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. In addition, if the terms "first" and "second" appear, they are only used for description and distinction purposes, and cannot be understood as indicating or implying relative importance.
[0031] See also Figure 1As shown, in one embodiment of the utility model, the semiconductor structure includes a first test piece 10, a second test piece 20 and a test hole structure 30, wherein the first test piece 10 includes a first comb tooth structure 12, the second test piece 20 includes a second comb tooth structure 22, the second comb tooth structure 22 is staggered with the first comb tooth structure 12, and the test hole structure 30 is arranged in a row on the first comb tooth structure 12 and the second comb tooth structure 22. By arranging the test hole structure 30 in a row on the comb teeth, the defects and positions of the metal bridge can be accurately detected. The semiconductor structure provided by the utility model can be applied to various chips for chip detection.
[0032] See also Figure 1 As shown, in one embodiment of the utility model, the semiconductor structure is arranged on the substrate 100, and for example, is arranged on the cutting path between different chips (not shown in the figure) on the substrate 100, and is made synchronously with the chip on the substrate 100. Among them, the substrate 100 can be any material suitable for forming a chip, such as silicon carbide (SiC), gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), indium phosphide (InP), gallium arsenide (GaAs), silicon germanium (GeSi), sapphire, silicon wafer or other semiconductor materials formed by III / V compounds, etc., and also includes a stacked structure composed of these semiconductor materials, or silicon on insulator, stacked silicon on insulator, silicon germanium on insulator, and germanium on insulator. In this embodiment, the substrate 100 is, for example, a silicon wafer semiconductor substrate, which is specifically selected according to the type of chip to be manufactured. After the chip is manufactured, the semiconductor structure of the present application is used to test the types of defects and the severity of defects that may exist in the chip in the analysis area, which can be widely used in various chips to speed up the test efficiency of the chip.
[0033] See also Figure 1 As shown, in one embodiment of the utility model, the first test piece 10 includes a first handle 11 and a plurality of first comb tooth structures 12, the first handle 11 and the first comb tooth structure 12 are, for example, rectangular, and the plurality of first comb tooth structures 12 are, for example, arranged in parallel on the first handle 11, and the first handle 11 and the first comb tooth structure 12 are, for example, arranged vertically. Among them, the material filled in the first handle 11 and the first comb tooth structure 12 is, for example, metal copper. In other embodiments, the material filled in the first handle 11 and the first comb tooth structure 12 can also be other metals, which will not be elaborated here.
[0034] See also Figure 1As shown, in one embodiment of the utility model, the second test piece 20 includes a second handle 21 and a plurality of second comb tooth structures 22, the second handle 21 and the second comb tooth structure 22 are, for example, rectangular, and the plurality of second comb tooth structures 22 are, for example, arranged in parallel on the second handle 21, and the second handle 21 and the second comb tooth structure 22 are, for example, arranged vertically. Among them, the material filled in the second handle 21 and the second comb tooth structure 22 is, for example, metal copper. In other embodiments, the material filled in the second handle 21 and the second comb tooth structure 22 can also be other metals, which will not be elaborated here. In one embodiment of the present application, the number of the second comb tooth structures 22 is the same as the number of the first comb tooth structures 12, and in other embodiments, they may not be the same. The number of the first comb tooth structure 12 and the second comb tooth structure 22 in the drawings of the present application is only for example and is not intended to limit the present application. The specific number is selected according to the manufacturing requirements.
[0035] See also Figure 1 As shown, in one embodiment of the present invention, the first test piece 10 and the second test piece 20 have the same structure and the same size, which are defined according to the spatial positions of the two test pieces, one of which is defined as the first test piece 10 and the other as the second test piece 20. The openings of the first test piece 10 and the second test piece 20 are opposite, the second handle 21 and the first handle 11 are arranged in parallel, and the second comb tooth structure 22 and the first comb tooth structure 12 are arranged alternately, that is, the first test piece 10 and the second test piece 20 are centrally symmetrical about the center of the semiconductor structure. And the first test piece 10 and the second test piece 20 are located on the same plane and do not contact each other. In one embodiment of the present invention, the first test piece 10 and the second test piece 20 are separated by a dielectric layer.
[0036] See also Figure 1 As shown, in one embodiment of the utility model, the first comb tooth structure 12 and the second comb tooth structure 22 are equal in shape and size, the test hole structure 30 is arranged on the first comb tooth structure 12 and the second comb tooth structure 22, and the shape and size of the test hole structure 30 on the first comb tooth structure 12 and the second comb tooth structure 22 are equal. In this embodiment, the shape of the test hole structure 30 is, for example, a rectangle or a rounded rectangle. Among them, the material filled in the test hole structure 30 is, for example, the same as the material in the first handle 11 and the first comb tooth structure 12, and is, for example, metal copper. In other embodiments, the material filled in the test hole structure 30 can also be other metals, which will not be elaborated here.
[0037] See also Figures 1 to 3As shown, in one embodiment of the utility model, the ratio of the width of the first comb tooth structure 12 or the second comb tooth structure 22 to the width of the test hole structure 30 is, for example, 1.4:1 to 2:1, the ratio of the length of the first comb tooth structure 12 or the second comb tooth structure 22 to the length of the test hole structure 30 is, for example, 1.1:1 to 1.3:1, and the ratio of the thickness of the first comb tooth structure 12 or the second comb tooth structure 22 to the thickness of the test hole structure 30 is, for example, 0.8:1 to 1.3:1. The test hole structure 30 is arranged in a row on the comb teeth, and the area ratio of a single test hole structure 30 to a single comb tooth structure is, for example, 45% to 70%. By arranging a row of test hole structures 30, the test range is increased, the randomness of single-point test holes is avoided, and the detection accuracy is improved.
[0038] See also Figures 3 to 5 As shown, in one embodiment of the utility model, the semiconductor structure is arranged in a dielectric layer 101 on a substrate 100, and the dielectric layer 101 is composed of dielectric materials such as silicon dioxide (SiO2), silicon fluoride (SiF), silicon oxycarbide (SiOC) or silicon oxyfluoride (SiOF), and the present application does not make specific restrictions. In the present embodiment, the dielectric layer 101 is, for example, silicon dioxide. When forming the comb tooth structure and the test hole structure 30, for example, they are formed by two-step etching. Specifically, the position of the comb tooth structure is first defined by the first photoresist 110 on the dielectric layer 101, and the groove 120 is etched to form the test hole structure 30, and then the second photoresist 130 is formed on the groove 120 and the dielectric layer 101 where the test hole structure 30 is required to be formed, and the position of the test hole structure 30 is defined, and then a through hole is etched to form (not shown in the figure), and finally a metal material is deposited to form the comb tooth structure and the test hole structure 30. There is no specific limit on the number of dielectric layers, grooves, and through holes. The number of layers in the semiconductor structure is increased synchronously according to the number of metal layers on the chip. When forming a through hole, the second photoresist 130 in the groove 120 may be completely etched, and part of the dielectric layer 101 on both sides of the groove 120 may be etched, resulting in a reduction in the size of the dielectric layer 101 between adjacent grooves 120. In this embodiment, the size of the dielectric layer 101 between adjacent comb structures is different, for example, S2 <S3<S1。
[0039] See also Figure 1 and Figure 3As shown, in one embodiment of the utility model, a first test pad 13 is also provided on the first handle 11, and the first test pad 13 is provided at one end of the first handle 11. A second test pad 23 is also provided on the second handle 21, and the second test pad 23 is provided at one end of the second handle 21, and the first test pad 13 and the second test pad 23 are centrally symmetrically distributed. Among them, the first test pad 13, for example, includes forming a metal contact point on the first handle 11 or marking a test point on the first handle 11, and the second test pad 23, for example, includes forming a metal contact point on the second handle 21 or marking a test point on the second handle 21. The present application does not limit the shapes of the first test pad 13 and the second test pad 23, such as cylindrical or prismatic.
[0040] See also Figure 1 and Figure 3 As shown, in one embodiment of the utility model, when testing the semiconductor structure, the first test pad 13 and the second test pad 23 are respectively connected to the voltage source, and the current between the first test pad 13 and the second test pad 23 is tested. If the current does not exceed the preset value, it is determined that the metal bridge test has passed. When the semiconductor structure containing the test hole structure 30 has a metal bridging problem, the test current will increase, and if it exceeds the preset value, it is determined that the metal bridge test has not passed. The problem that the metal bridging defects that may occur due to the through-hole problem in the dual Damascus structure cannot be measured is solved, and the test hole structure 30 is improved to reduce the randomness of the detection. The entire row of test hole structures 30 can detect defects caused by the weakest point, that is, the smallest size of the dielectric layer 101 between adjacent comb tooth structures, in this embodiment, that is, S2. The semiconductor structure provided by the present application can improve the detection accuracy and speed up the test efficiency of the chip.
[0041] In summary, the utility model provides a semiconductor structure. By improving the structure of the semiconductor structure, the unexpected technical effect of the present application is that it solves the problem of being unable to measure the metal bridging defects that may occur in the dual Damascus structure due to the through-hole problem, reduces the randomness of the detection, can detect the defects caused by the weakest point, and improves the detection accuracy; the entire semiconductor structure tests the types of defects that may exist in the chip in the analysis area and the severity of the defects, and can be widely used in various chips to speed up the testing efficiency of the chip.
[0042] The embodiments of the utility model disclosed above are only used to help illustrate the utility model. The embodiments do not describe all the details in detail, nor do they limit the utility model to the specific implementation methods described. Obviously, many modifications and changes can be made according to the content of this specification. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the utility model, so that technicians in the relevant technical field can well understand and use the utility model. The utility model is limited only by the claims and their full scope and equivalents.
Claims
1. A semiconductor structure, characterized in that: include: A first test piece, comprising a plurality of first comb tooth structures; A second test piece, comprising a plurality of second comb tooth structures, wherein the second comb tooth structures are arranged alternately with the first comb tooth structures; as well as The test hole structure is arranged in a row on the first comb tooth structure and the second comb tooth structure.
2. The semiconductor structure according to claim 1, characterized in that: The first comb tooth structure and the second comb tooth structure are equal in shape and size.
3. The semiconductor structure according to claim 2, characterized in that: The ratio of the width of the first comb-tooth structure to the width of the test hole structure is 1.4:1 to 2:
1.
4. The semiconductor structure according to claim 2, characterized in that: The ratio of the length of the first comb tooth structure to the length of the testing hole structure is 1.1:1 to 1.3:
1.
5. The semiconductor structure according to claim 1, characterized in that: The area ratio of a single test hole structure to a single first comb tooth structure or a single second comb tooth structure is 45% to 70%.
6. The semiconductor structure according to claim 1, characterized in that The ratio of the thickness of the first comb-tooth structure or the second comb-tooth structure to the thickness of the test hole structure is 0.8:1 to 1.3:
1.
7. The semiconductor structure according to claim 1, characterized in that: The first test piece also includes a first handle, and a plurality of the first comb tooth structures are vertically arranged on the first handle.
8. The semiconductor structure according to claim 7, characterized in that: The second test piece also includes a second handle, and a plurality of the second comb tooth structures are vertically arranged on the second handle.
9. The semiconductor structure according to claim 8, characterized in that: The openings of the first test piece and the second test piece are opposite to each other, and the second handle is arranged in parallel with the first handle.
10. The semiconductor structure according to claim 9, characterized in that: A first test pad is also arranged on the end of the first handle, and a second test pad is also arranged on the end of the second handle. The first test pad and the second test pad are centrally symmetrically distributed.