Integrated circuit

Abstract

The utility model provides an integrated circuit. Some embodiments relate to an integrated circuit including a semiconductor substrate. In a cross-sectional view, the silicide structure is disposed over the semiconductor substrate. In a cross-sectional view, the dielectric structure directly contacts an upper surface of the silicide structure. In a cross-sectional view, the metal structure directly contacts an upper surface of the dielectric layer such that the silicide structure and the metal structure establish a bottom electrode and a top electrode spaced apart from each other by the dielectric structure, respectively, to establish a metal-insulator-silicide capacitor over the semiconductor substrate.

Description

Technical Field

[0001] The utility model relates to an integrated circuit. Background Art

[0002] Modern integrated chips include millions or billions of transistor devices that are configured to achieve the logic functions of the integrated chip (e.g., to form a processor configured to perform the logic functions). Often, the integrated chip may also include passive devices, such as capacitors, resistors, inductors, varactors, etc. Metal-insulator-metal (MIM) capacitors are a common type of passive device that are often integrated into the back-end-of-the-line metal interconnect layer of the integrated chip. For example, MIM capacitors can be used as decoupling capacitors that are configured to mitigate power supply noise or switching noise (e.g., switching of input / output (I / O) circuits and core circuits) caused by changes in current flowing through various parasitic inductance components associated with the integrated chip and the package in which the integrated chip is located. Utility Model Content

[0003] An embodiment of the utility model provides an integrated circuit, comprising: a semiconductor substrate; a silicide structure, which is arranged on the semiconductor substrate in a cross-sectional view; a dielectric structure, which directly contacts the upper surface of the silicide structure in the cross-sectional view; and a metal structure, which directly contacts the upper surface of the dielectric structure in the cross-sectional view, so that the silicide structure, the dielectric structure and the metal structure establish a metal-insulator-silicide capacitor on the semiconductor substrate.

[0004] In some embodiments, the utility model provides another integrated circuit, including: a semiconductor substrate; a gate electrode extending above the semiconductor substrate; a first silicide structure disposed on the gate electrode; a first dielectric structure directly disposed on the first silicide structure; and a first conductive structure directly contacting the upper surface of the first dielectric structure, so that the first silicide structure and the first conductive structure respectively establish a first bottom electrode and a first top electrode separated from each other by the first dielectric structure, so as to establish a first conductor-insulator-silicide capacitor above the gate electrode.

[0005] In some embodiments, the present invention provides a method for manufacturing an integrated circuit, comprising: forming a silicide layer on a substrate, the silicide layer comprising a first silicide structure and a second silicide structure; forming a capacitor dielectric layer on the silicide layer; forming a metal layer on the capacitor dielectric layer; patterning the metal layer to form a first metal structure on the first silicide structure and a second metal structure on the second silicide structure; forming an interlayer dielectric on the first metal structure and the second metal structure; and forming a first contact and a second contact reaching the first metal structure and the second metal structure and a third contact and a fourth contact reaching the first silicide structure and the second silicide structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The aspects of the embodiments of the present invention will be best understood when the following detailed description is read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the size of various features may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1A to Figure 1B Perspective views of some embodiments of integrated circuits including metal-insulator-silicide capacitors according to embodiments of the present invention are shown.

[0008] Figure 2A and Figure 2B Some embodiments of integrated circuits including metal-insulator-silicide capacitors are shown in cross-sectional and top views, respectively.

[0009] Figure 3A and Figure 3B Some embodiments of integrated circuits including metal-insulator-silicide capacitors are shown in cross-sectional and top views, respectively.

[0010] Figure 4A and Figure 4B Some embodiments of integrated circuits including metal-insulator-silicide capacitors are shown in cross-sectional and top views, respectively.

[0011] Figure 5A and Figure 5B Some embodiments of integrated circuits including metal-insulator-silicide capacitors are shown in cross-sectional and top views, respectively.

[0012] Fig. 6A and Figure 6B Some embodiments of integrated circuits including metal-insulator-silicide capacitors are shown in cross-sectional and top views, respectively.

[0013] Fig. 7A and Figure 7BSome embodiments of integrated circuits including metal-insulator-silicide capacitors are shown in cross-sectional and top views, respectively.

[0014] Figures 8 to 11 A series of incremental cross-sectional views illustrating a method of manufacturing according to some embodiments.

[0015] Figures 12 to 15 A series of incremental cross-sectional views illustrating a method of manufacturing according to some embodiments.

[0016] Figures 16 to 19 A series of incremental cross-sectional views illustrating a method of manufacturing according to some embodiments.

[0017] Fig. 20 A method is presented in the form of a flow chart illustrating some embodiments of the present concepts. DETAILED DESCRIPTION

[0018] The utility model embodiment provides many different embodiments or examples for implementing the different features of the utility model embodiment. The specific examples of components and arrangements are described below to simplify the utility model embodiment. Of course, these are only examples and are not intended to be limiting. For example, the following description may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which an additional feature can be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the utility model embodiment may reuse reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself represent the relationship between the various embodiments and / or configurations discussed.

[0019] Additionally, for ease of description, spatially relative terms such as "beneath," "below," "lower," "above," "upper," etc. may be used herein to describe the relationship of one component or feature to another (other) component or feature as depicted in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be in other orientations (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0020] An integrated circuit or "chip" typically includes a substrate and an interconnect structure located on the substrate. The substrate includes devices each having multiple terminals, and the interconnect structure includes multiple metal layers stacked on top of each other. Generally, consecutive numbers are used to refer to the metal layers (for example, the bottom metal layer is called the 1st metal layer, the next metal layer is called the 2nd metal layer, the next metal layer is called the 3rd metal layer, and so on, until the Nth (top) metal layer, where N is any integer). Contacts extend from the bottom metal layer to the device terminals, and through-holes extend in a vertical direction between the wiring segments of each metal layer, so that the entire interconnect structure connects the terminals of the device to each other and to the bonding pads in the top metal layer to achieve a predetermined circuit configuration. The interconnect structure can also couple the device to a MIM capacitor, which is traditionally included in the top metal layer within the interconnect structure. For example, a MIM capacitor may have an upper electrode corresponding to an Nth metal layer and a lower electrode corresponding to an N-1th metal layer, with a capacitor dielectric between the upper electrode and the lower electrode (and / or the upper electrode and / or the lower electrode may be located between the N-1th layer and the Nth metal layer). Some aspects of the present invention recognize that a relatively long electrical path between a device terminal and such a MIM capacitor represents a relatively high resistance and high manufacturing cost due to several depositions and a large number of masks for patterning.

[0021] In order to reduce the total wiring length and correspondingly reduce the resistance between the device and the MIM capacitor, embodiments of the present invention provide a metal-insulator-silicide structure that may have a lower electrode corresponding to the silicide. The silicide may be disposed on the upper surface of the substrate, or on a polysilicon feature extending above the substrate (e.g., a polysilicon gate or a polysilicon line). Compared to the conventional method of positioning the lower MIM electrode in the upper metal layer, the use of silicide as the lower electrode reduces the resistance between the device and the capacitor, and also reduces the number of masks involved in the fabrication, thereby providing an improved device at a lower cost.

[0022] Reference Figure 1A, a perspective view of an integrated circuit (IC) 100a according to some embodiments can be seen. IC 100a includes a semiconductor substrate 102 having a first device region 104a and a second device region 104b. A first metal-insulator-silicide capacitor 106a is disposed on the first device region 104a, and a second metal-insulator-silicide capacitor 106b is disposed on the second device region 104b. Depending on the implementation, the metal-insulator-silicide capacitor can be represented in a variety of different ways, and several examples are now described below. Semiconductor substrate 102 can be a single crystal silicon substrate, a semiconductor-on-insulator (SOI) substrate, a silicon-on-insulator (SOI) substrate, a sapphire substrate, or some other substrate.

[0023] The first metal-insulator-silicide capacitor 106a includes a first silicide structure 108a, which is directly disposed on the first device region 104a of the semiconductor substrate 102. A first dielectric structure 110a is directly disposed on the first silicide structure 108a. The first metal structure 112a directly contacts the upper surface of the first dielectric structure 110a. Therefore, the first silicide structure 108a and the first metal structure 112a respectively establish a first bottom electrode and a first top electrode separated from each other by the first dielectric structure 110a, thereby establishing the first metal-insulator-silicide capacitor 106a. Figure 1A In the embodiment, the first device region 104a may be an independent region of the substrate 102 and / or may correspond to a terminal of a semiconductor device, and may be a doped region or an undoped region of a semiconductor material (eg, single crystal silicon).

[0024] The second metal-insulator-silicide capacitor 106b is disposed on a polysilicon feature 114 extending on the second device region 104b of the semiconductor substrate 102. The second metal-insulator-silicide capacitor 106b includes a second silicide structure 108b disposed directly on the polysilicon feature 114. The second dielectric structure 110b is disposed directly on the second silicide structure 108b, and the second metal structure 112b directly contacts the upper surface of the second dielectric structure 110b. In this way, the second silicide structure 108b and the second metal structure 112b respectively establish a second bottom electrode and a second top electrode separated from each other by the second dielectric structure 110b, thereby establishing the second metal-insulator-silicide capacitor 106b.

[0025] The first metal-insulator-silicide capacitor 106a and the second metal-insulator-silicide capacitor 106b may be used as decoupling capacitors and / or may help stabilize voltage, reduce noise, and / or shift direct current (DC) phase in the IC 100a. The first silicide structure 108a is arranged at a first silicide height above the upper surface of the substrate (e.g., due to the Figure 1A to Figure 1B The substrate 102 is in direct contact with the first silicide structure 108a, and the first silicide height is zero, so the first silicide height is not marked), and the second silicide structure 108b is arranged at a second silicide height h measured perpendicular to the upper surface of the substrate. s2 The second silicide height is greater than the first silicide height. Similarly, the first metal structure 112a is arranged at a first metal height h measured perpendicular to the upper surface of the substrate. m1 The second metal structure 112b is arranged at a second metal height h above the upper surface of the substrate. m2 The second metal height h m2 Greater than the first metal height h m1 , and the second silicide height h s2 Greater than the first metal height h m1 It should be understood that the first metal height h m1 and the second metal height h m2 Each is less than the contact height h corresponding to the interface where the upper surface of the contact 116 / 118 meets the lower surface of the first metal layer 121 c .

[0026] In some cases, the first silicide structure 108a and the second silicide structure 108b may have the same composition as each other, and may be made of, for example, cobalt silicide (e.g., Co-silicide), nickel silicide (e.g., Ni-silicide), tantalum silicide (e.g., Ta-silicide), or the like. Similarly, the first dielectric structure 110a and the second dielectric structure 110b may have the same composition as each other, and may be made of, for example, oxides (e.g., silicon dioxide, SiO2), nitrides (e.g., silicon nitride, Si3N4), carbides (e.g., silicon carbide, SiC), oxynitrides (e.g., silicon oxynitride, SiO x N y ), carbon oxides (e.g., silicon oxycarbide), carbon nitrides (e.g., silicon carbonitride), polymers, and the like. In addition, the first metal structure 112a and the second metal structure 112b may have the same composition as each other, and may be made of, for example, metals or metal alloys including copper, aluminum, nickel, tungsten, tantalum, titanium, and / or combinations thereof. Using the same material composition for each layer enables streamlined processing.

[0027] In some embodiments, the upper surface of the first silicide structure 108a has a first surface area, and the upper surface of the first metal structure 112a has a second surface area. The first surface area of ​​the first silicide structure 108a is greater than the second surface area of ​​the first metal structure 112a, so that the first metal structure 112a covers a first portion of the upper surface of the first silicide structure 108a, but does not cover a second portion (e.g., 115) of the upper surface of the first silicide structure 108a. This arrangement enables the first contacts 116a and 116b to extend from the first portion of the upper surface of the metal structures 112a and 112b to the first metal features 120a and 120b, respectively, through an interlayer dielectric 123 (e.g., a low-k dielectric) disposed between the upper surface of the substrate 102 and the lower surface of the first metal layer 121. The second contacts 118a, 118b extend from the silicide structures 108a, 108b through the interlayer dielectric 123 to the second metal features 122a, 122b, respectively. The second metal features 122a, 122b may have the same height as the first metal features 120a, 120b (the height is measured perpendicular to the upper surface of the semiconductor substrate 102), and in some cases may be referred to as the first metal layer 121 or other conductive layer in the interconnect structure above the substrate 102.

[0028] exist Figure 1A In the embodiment, the polysilicon feature 114 is directly disposed on a shallow trench isolation (STI) region 124 made of a dielectric material in the substrate 102. Figure 1A, the second metal-insulator-silicide capacitor 106b is coupled to the polysilicon feature 114 and is spaced apart from the first metal-insulator-silicide capacitor 106a in the lateral direction and the vertical direction. Therefore, the outer edge of the metal structure 112a and the outer edge of the metal structure 112b can be spaced apart from each other, and the outer edge of the silicide structure 108a and the outer edge of the silicide structure 108b can also be spaced apart from each other, and the outer edge of the metal structure 112a and the outer edge of the metal structure 112b can be aligned with the outer edge of the dielectric structure 110a and the outer edge of the dielectric structure 110b. The polysilicon feature 114 can include doped polysilicon and can be a linear segment or a curved segment extending laterally above the upper surface of the semiconductor substrate. In some cases, the polysilicon feature 114 can extend between the terminals of two devices (e.g., between the gates of two metal-oxide-semiconductor field-effect-transistors (MOSFETs)) and / or can be a resistor. In some cases, gate dielectric 128 may separate the lower surface of polysilicon feature 114 from STI region 124, and there may also be sidewall spacers including inner spacer layer 134 and outer spacer layer 136. Inner spacer layer 134 may be silicon nitride, silicon oxide, silicon oxynitride, or the like, and outer spacer layer 136 may have a different composition than the inner spacer layer or the same composition and may include silicon nitride, silicon oxide, or silicon oxynitride.

[0029] Compared to the conventional method in which the MIM capacitor has a lower electrode located at the top metal layer of the interconnect structure, the use of Figure 1A The silicide shown as the lower electrode (where each silicide structure 108a, 108b may be below the lowermost metal layer 121) reduces the resistance between the device and the lower electrode. This approach can reduce the number of masks involved in the fabrication, thereby providing an improved device at a lower cost.

[0030] Figure 1B Another IC 100b is shown, which includes a first metal-insulator-silicide capacitor 106a disposed on a first device region 104a and a second metal-insulator-silicide capacitor 106b disposed on a second device region 104b. Although IC 100b shares many features with IC 100a, Figure 1B In FIG. 1 , the polysilicon feature 114 corresponds to the gate of a metal oxide semiconductor field effect transistor (MOSFET); and in FIG. Figure 1A In FIG. 1 , polysilicon feature 114 is located above STI region 124. Figure 1B, the MOSFET includes a channel region 126 having a first conductivity (e.g., n-type) disposed in a substrate. A polysilicon feature 114 extends over the channel region 126 and is separated from the channel region 126 by a gate dielectric 128. A source 130 and a drain 132, each having a second conductivity type opposite to the first conductivity type, are disposed in the substrate on opposite sides of the polysilicon feature 114. A first silicide structure 108a directly contacts an upper surface of the source 130; and a second silicide structure 108b directly contacts an upper surface of the polysilicon feature 114. Sidewall spacers including an inner spacer layer 134 and an outer spacer layer 136 may also be present.

[0031] also, Figure 1B An example is shown in which the first dielectric structure 110a and the second dielectric structure 110b of the first metal-insulator-silicide capacitor 106a and the second metal-insulator-silicide capacitor 106b are disposed in a single layer of dielectric material, the single layer extending continuously over different heights between the first metal-insulator-silicide capacitor 106a and the second metal-insulator-silicide capacitor 106b. However, it should be understood that Figure 1B Alternatively include Figure 1A The first dielectric structure and the second dielectric structure are separated, and / or Figure 1A Alternatively include Figure 1B A single layer of dielectric material is shown similar to a single layer.

[0032] although Figure 1A to Figure 1B Some examples are shown, but it should be understood that the lower electrode of the metal-insulator-silicide capacitor of the present invention can be coupled to any doped or any undoped single crystal region and / or doped or undoped polysilicon region or any conductive feature. Figure 1B Although the example in the context of MOSFET is shown, the metal-insulator-silicide capacitor of the present invention is also applicable to other semiconductor devices, such as FinFET, bipolar junction transistor, junction FET, high voltage FET and / or diode, etc. Figure 1A to Figure 1B An example is shown in which the upper surface of the semiconductor substrate is a continuous plane, but in other embodiments, the upper surface of the semiconductor substrate may have a varying height. For example, when FinFET is used instead of Figure 1B In the embodiment of the MOSFET shown in the figure, the source / drain region of the FinFET can be an epitaxial source / drain having an upper surface higher than the base surface of the substrate, and the polysilicon gate feature can have an upper surface located above the upper surface of the epitaxial source / drain, and when a metal-insulator-silicide capacitor is used in such a FinFET, the metal-insulator-silicide capacitor can still be similar to Figure 1A to Figure 1BFurthermore, although metal electrodes are shown, other conductive materials may be used.

[0033] Figure 2A and Figure 2B 2 and 3 show a cross-sectional view and a top view, respectively, of another example of an IC 200 according to some embodiments. FIG. 2A to FIG. 2B In the embodiment of the present invention, a polysilicon feature 114 extends over a device region of a semiconductor substrate 102, the device region including an STI region 124 made of a dielectric material. A silicide structure 108 is disposed on the polysilicon feature 114. A dielectric structure 110 is disposed directly on the silicide structure 108, and a metal structure 112 directly contacts an upper surface of the dielectric structure 110. In this manner, the silicide structure 108 and the metal structure 112 respectively establish a bottom electrode and a top electrode separated from each other by the dielectric structure 110 to establish a metal-insulator-silicide capacitor 106 over the polysilicon feature 114.

[0034] FIG. 3A to FIG. 3B A cross-sectional view and a top view are respectively shown of another example of an IC 300 according to some embodiments. The IC includes a MOSFET having a gate, a source 130, and a drain 132 corresponding to a polysilicon feature 114. The source 130 and the drain 132 have a first conductivity type (e.g., n-type) and are separated from each other by a channel region 126 having a second conductivity type opposite to the first conductivity type. The polysilicon feature 114 extends over the channel region 126 and is separated from the channel region 126 by a gate dielectric 128. A silicide region is formed over the source 130, the drain 132, and the polysilicon feature 114. The silicide structure 108 located over the polysilicon feature 114 together with the dielectric structure 110 and the metal structure 112 establishes a metal-insulator-silicide capacitor 106. The metal-insulator-silicide capacitor 106 is disposed over the upper surface of the polysilicon feature 114 and under the lower surface of the first metal layer 121. However, in other cases, the polysilicon features 114 and the silicide structure 108 may also be located in higher layers of the interconnect structure, such that the metal-insulator-silicide capacitor 106 is located above the first metal layer 121 but below the uppermost metal layer of the interconnect structure.

[0035] Figure 4A and Figure 4B 4 and 5 show a cross-sectional view and a top view, respectively, of another example of an IC 400 according to some embodiments. FIG. 4A to FIG. 4B In FIG. 1 , polysilicon features 114 extend over a device region of semiconductor substrate 102. This device region may include STI regions 124 (e.g., similar to FIG. 2A to FIG. 2B ) or may include MOSFET features (e.g., similar to FIG. 3A to FIG. 3B). A metal structure 112 (and optionally a dielectric structure 110) is disposed on the STI region 124. The silicide structure 108 is aligned along the edge of the STI region 124 on the upper surface of the semiconductor substrate 102. Therefore, the silicide structure 108 can directly contact the sidewalls of the STI region 124. In this way, the silicide structure 108 and the metal structure 112 respectively establish a bottom electrode and a top electrode separated from each other by the STI region 124 and / or the interlayer dielectric 123 to establish a metal-insulator-silicide capacitor 106.

[0036] Figure 5A and Figure 5B 5 and 6 show a cross-sectional view and a top view, respectively, of another example of an IC 500 according to some embodiments. FIG. 5A to FIG. 5B In the embodiment, the silicide structure 108 is continuously extended from above the source 130 to outside the outer edge of the source 130 on the upper surface of the substrate 102. The dielectric structure 110 and the metal structure 112 are disposed on the silicide structure 108.

[0037] Fig. 6A and Figure 6B 1 and 2 show a cross-sectional view and a top view of another example of an IC 600 according to some embodiments. A dielectric structure 110a and a metal structure 112a are disposed on the silicide structure 108a. FIG. 6A to FIG. 6B In the embodiment, the portion of the substrate over which the silicide structure 108a extends may be intrinsic silicon, or may have a lower doping concentration (e.g., less than or equal to 10^16 defects / cm3), and may, for example, correspond to a well region.

[0038] Fig. 7A and Figure 7B A cross-sectional view and a top view, respectively, are shown of another example of an IC 700 in accordance with some embodiments. FIG. 7A to FIG. 7B and FIG. 6A to FIG. 6B Same, except in FIG. 7A to FIG. 7B In the embodiment of the present invention, the portion 702 of the substrate over which the silicide structure 108a extends may have a high doping concentration (eg, greater than 10^16 defects / cm3) and may thus correspond to a source / drain region or other device terminal.

[0039] Reference Figures 8 to 11 , cross-sectional views of some embodiments of a method of manufacturing an integrated circuit including a metal-insulator-silicide capacitor at different stages of manufacture are provided. Figures 8 to 11It is described as a series of actions, but it should be understood that these actions are not limited to the order of actions that can be changed in other embodiments, and the disclosed method can also be applied to other structures. In other embodiments, some actions shown and / or described can be omitted in whole or in part.

[0040] exist Figure 8 In the embodiment of the present invention, polysilicon feature 114 has been patterned over dielectric 128, and inner spacer layer 134 and outer spacer layer 136 are formed along the sidewalls of polysilicon feature 114. Then, silicide is formed directly on the upper surface of the polysilicon feature and on the device region of the semiconductor substrate simultaneously. In some embodiments, silicide is formed over the entire upper surface of polysilicon feature 114 and over the entire upper surface of silicon substrate 102, and then the silicide is patterned (e.g., etched back) to establish first silicide structure 108a and second silicide structure 108b. In other cases, a dielectric material is formed over the polysilicon feature 114 and over the upper surface of the substrate 102, and then openings are formed in the dielectric material over the polysilicon feature 114 and over the upper surface of the substrate 102, and silicide is self-alignedly formed in these openings to create a first silicide structure 108a and a second silicide structure 108b (which in this case may be referred to as a salicide structure). After the first silicide structure 108a and the second silicide structure 108b have been formed, a dielectric layer 110 is formed over the first silicide structure and the second silicide structure, and a metal layer 112 is formed over the dielectric layer. The dielectric layer 110 may be formed by a deposition process such as chemical vapor deposition, atomic layer deposition, or other deposition processes; and the metal layer 112 may be formed by sputtering, electroplating, or other deposition processes. In some embodiments, the dielectric layer 110 and the metal layer 112 may be formed as a continuous layer over the substrate. Then, a hard mask 800 is formed over the metal layer 112 , and a photoresist mask layer is formed over the hard mask and patterned (eg, using a photoresist and a developer), thereby providing a patterned photomask 802 .

[0041] In some embodiments, the substrate 102 may be a bulk silicon substrate or a semiconductor-on-insulator (SOI) substrate (e.g., a silicon-on-insulator substrate). For example, the substrate 102 may also be a binary semiconductor substrate (e.g., GaAs), a ternary semiconductor substrate (e.g., AlGaAs), or a higher-order semiconductor substrate. In many cases, the substrate is a semiconductor wafer and may have, for example, the following diameters: 1 inch (25 mm); 2 inches (51 mm); 3 inches (76 mm); 4 inches (100 mm); 5 inches (130 mm) or 125 mm (4.9 inches); 150 mm (5.9 inches, commonly referred to as "6 inches"); 200 mm (7.9 inches, commonly referred to as "8 inches"); 300 mm (11.8 inches, commonly referred to as "12 inches"); 450 mm (17.7 inches, commonly referred to as "18 inches").

[0042] exist Fig. 9 In the embodiment of the present invention, a first etch is performed to etch the hard mask 800 according to the patterned photomask 802. Thus, the first etch removes the exposed portions of the hard mask and generally leaves other portions of the hard mask covered by the photomask in place. The first etch can be a wet etch or a dry etch.

[0043] exist Fig.10 In the embodiment of the present invention, a second etch is performed to etch the metal layer 112 according to the hard mask. Thus, the second etch removes the exposed portion of the metal layer and generally leaves the first metal structure 112a and the second metal structure 112b covered by the hard mask 800 in place. The second etch can be a wet etch or a dry etch and can have a different chemistry than the first etch. The photomask 802 can also be removed, for example, by an ashing process or plasma etching. In an alternative embodiment (not shown), in Fig.10 The hard mask 800 may also be removed.

[0044] exist Fig.11 In the embodiment of the present invention, an interlayer dielectric (ILD) 123 is formed on the dielectric layer 110 (and optionally on the hard mask 800 if the hard mask 800 is still in place). A contact opening and a first metal line opening are formed in the interlayer dielectric 123. The contact opening extends downward through the hard mask 800 to expose the upper surface of the first metal structure 112a and the second metal structure 112b. Metal contacts 118a, 118b and first metal lines 122a, 122b are then formed in the openings. A chemical mechanical planarization (CMP) process is then performed to obtain Fig.11 The structure shown.

[0045] Reference Figures 12 to 15, cross-sectional views of some embodiments of an alternative method of manufacturing an integrated circuit including a metal-insulator-silicide capacitor at different stages of manufacture are provided. Figures 12 to 15 It is described as a series of actions, but it should be understood that these actions are not limited to the order of actions that can be changed in other embodiments, and the disclosed method can also be applied to other structures. In other embodiments, some actions shown and / or described can be omitted in whole or in part.

[0046] exist Fig.12 1 , a polysilicon feature 114 has been patterned over a dielectric 128, and an inner spacer layer 134 and an outer spacer layer 136 are formed along the sidewalls of the polysilicon feature 114. A dielectric material 123 is formed over the polysilicon feature 114 and over the upper surface of the substrate 102, and then an opening is formed in the dielectric material over the polysilicon feature 114 and over the upper surface of the substrate 102. For example, silicide is formed by forming a metal layer over the polysilicon feature 114 and the exposed upper surface of the substrate 102, wherein the metal layer reacts with the underlying silicon to form a first silicide structure 108a and a second silicide structure 108b. Thus, the first silicide structure 108a and the second silicide structure 108b are self-aligned in the opening.

[0047] exist Fig.13 , after the first silicide structure 108a and the second silicide structure 108b have been formed, a dielectric layer 110 is formed on the first silicide structure and the second silicide structure, and a metal layer 112 is formed on the dielectric layer 110. The dielectric layer 110 may be formed by a deposition process such as chemical vapor deposition, atomic layer deposition, or other deposition processes; and the metal layer 112 may be formed by sputtering, electroplating, or other deposition processes. In some embodiments, the dielectric layer 110 and the metal layer 112 may be formed as a continuous layer on the substrate. Then, a hard mask 800 is formed on the metal layer 112, and a photoresist mask layer is formed on the hard mask and patterned (for example, using a photoresist and a developer), thereby providing a patterned photomask 802.

[0048] exist Fig.14 In the embodiment of the present invention, a first etch is performed to etch the hard mask 800 according to the patterned photomask 802. Thus, the first etch removes the exposed portions of the hard mask 800 and generally leaves other portions of the hard mask covered by the photomask in place. The first etch can be a wet etch or a dry etch.

[0049] exist Fig.14In the embodiment of the present invention, a second etch is performed to etch the metal layer 112 according to the hard mask. Thus, the second etch removes the exposed portion of the metal layer and generally leaves the first metal structure 112a and the second metal structure 112b covered by the hard mask 800 in place. The second etch can be a wet etch or a dry etch and can have a different chemistry than the first etch. The photomask 802 can also be removed, for example, by an ashing process or plasma etching. In an alternative embodiment (not shown), in Fig.14 The hard mask 800 may also be removed.

[0050] exist Fig.15 In the embodiment of the present invention, a second interlayer dielectric (ILD) structure 1502 is formed on the dielectric layer 110 (and optionally on the hard mask 800 if the hard mask 800 is still in place). A contact opening and a first metal line opening are formed in the second ILD structure 1502. The contact opening extends downward through the hard mask 800 to expose the upper surfaces of the first metal structure 112a and the second metal structure 112b. Then, metal contacts 118a, 118b and first metal lines 122a, 122b are formed in the openings. Then, a chemical mechanical planarization (CMP) process is performed to obtain Fig.15 The structure shown.

[0051] Figures 16 to 19 Shown with Figures 12 to 15 Another method similar to the one shown, except Figures 16 to 19 The illustrated method has a wider (eg, larger) silicide structure on the substrate 102. Figures 16 to 19 In FIG. 1 , metal structure 112 a is a planar feature located on a lower portion of dielectric layer 110 ; and Figures 12 to 15 The metal structure 112a has a U-shaped cross-sectional profile.

[0052] Fig. 20 A flow chart 2000 for fabricating an integrated circuit is shown in accordance with some embodiments.

[0053] In act 2002, a silicide layer is formed on a substrate. In some cases, the silicide layer may include a first silicide structure and a second silicide structure located at different heights above the substrate. In some embodiments, act 2002 may correspond to, for example Figure 8 , Fig.12 or Fig.16 .

[0054] In act 2004, a capacitor dielectric layer is formed over the silicide layer. In some embodiments, the capacitor dielectric layer includes separate dielectric structures located over the first silicide structure and the second silicide structure, respectively; however, in other cases, the capacitor dielectric layer is a continuous dielectric layer extending between the first silicide structure and the second silicide structure. In some embodiments, act 2004 may correspond to, for example, Figure 8 , Fig.13 or Fig.17 .

[0055] In act 2006, a metal layer is formed over the capacitor dielectric layer. In some embodiments, act 2006 may correspond to, for example, Figure 8 , Fig.13 or Fig.17 .

[0056] In act 2008, the metal layer is patterned to form a first metal structure over the first silicide structure and a second metal structure over the second silicide structure. In some embodiments, act 2008 may correspond to, for example, Fig. 9 , Fig.14 or Fig.18 .

[0057] In act 2010, an interlayer dielectric is formed over the first metal structure and the second metal structure. In some embodiments, act 2010 may correspond to, for example, Fig.11 , Fig.15 or Fig.19 .

[0058] In act 2012, a first contact and a second contact are formed to contact the first metal structure and the second metal structure, and a third contact and a fourth contact are formed to contact the first silicide structure and the second silicide structure. In some cases, the first contact, the second contact, the third contact, and the fourth contact are formed simultaneously. In some embodiments, act 2012 may correspond to, for example, Fig.11 , Fig.15 or Fig.19 .

[0059] Some embodiments relate to an integrated circuit including a semiconductor substrate. In a cross-sectional view, a silicide structure is disposed on the semiconductor substrate. In a cross-sectional view, a dielectric structure directly contacts an upper surface of the silicide structure. In a cross-sectional view, a metal structure directly contacts an upper surface of a dielectric layer, such that the silicide structure and the metal structure respectively establish a bottom electrode and a top electrode separated from each other by the dielectric structure to establish a metal-insulator-silicide capacitor on the semiconductor substrate.

[0060] Other embodiments relate to an integrated circuit (IC) including a semiconductor substrate including a first device region and a second device region. A first silicide structure is disposed on the first device region of the semiconductor substrate. A first dielectric structure is disposed directly on the first silicide structure. A first metal structure directly contacts an upper surface of the first dielectric structure such that the first silicide structure and the first metal structure respectively establish a first bottom electrode and a first top electrode spaced apart from each other by the first dielectric structure to establish a first metal-insulator-silicide capacitor over the first device region. A polysilicon feature extends over the second device region of the semiconductor substrate. A second silicide structure is disposed on the polysilicon feature. A second dielectric structure is disposed directly on the second silicide structure. A second metal structure directly contacts an upper surface of the second dielectric structure such that the second silicide structure and the second metal structure respectively establish a second bottom electrode and a second top electrode spaced apart from each other by the second dielectric structure to establish a second metal-insulator-silicide capacitor over the polysilicon feature.

[0061] Still other embodiments relate to a method. In the method, a silicide layer is formed on a substrate. The silicide layer includes a first silicide structure and a second silicide structure. A capacitor dielectric layer is formed on the silicide layer. A metal layer is formed on the capacitor dielectric layer. The metal layer is patterned to form a first metal structure on the first silicide structure and a second metal structure on the second silicide structure. An interlayer dielectric is formed on the first metal structure and the second metal structure. A first contact and a second contact are formed to reach the first metal structure and the second metal structure, and a third contact and a fourth contact are formed to reach the first silicide structure and the second silicide structure.

[0062] Some embodiments are related to an integrated circuit, including a semiconductor substrate, a silicide structure, a dielectric structure, and a metal structure. The silicide structure is disposed on the semiconductor substrate in a cross-sectional view. The dielectric structure directly contacts the upper surface of the silicide structure in the cross-sectional view. The metal structure directly contacts the upper surface of the dielectric structure in the cross-sectional view, so that the silicide structure, the dielectric structure, and the metal structure establish a metal-insulator-silicide capacitor on the semiconductor substrate. In some embodiments, the silicide structure and the metal structure respectively establish a bottom electrode and a top electrode separated from each other by the dielectric structure to establish a metal-insulator-silicide capacitor on the semiconductor substrate. In some embodiments, the upper surface of the silicide structure has a first surface area, and the upper surface of the metal structure has a second surface area; and wherein the first surface area is greater than the second surface area. In some embodiments, the metal structure covers a first portion of the upper surface of the silicide structure, but does not cover a second portion of the upper surface of the silicide structure. In some embodiments, the integrated circuit further includes a first metal feature, a first contact, a second metal feature, and a second contact. The first metal feature is arranged on the second portion of the upper surface of the silicide structure and is separated from the second portion of the upper surface of the silicide structure by a dielectric. The first contact extends from the first metal feature through the dielectric and contacts the second portion of the upper surface of the silicide structure. The second metal feature is arranged on the metal structure and is separated from the metal structure by the dielectric, the second metal feature having the same height as the first metal feature and is laterally separated from the first metal feature, the height being measured perpendicular to the upper surface of the semiconductor substrate. The second contact extends from the second metal feature through the dielectric and contacts the metal structure. In some embodiments, the integrated circuit further includes a shallow trench isolation (STI) region formed by a dielectric material and a polysilicon feature. The shallow trench isolation (STI) region formed by a dielectric material is disposed in the semiconductor substrate. The polysilicon feature extends above the shallow trench isolation region. The silicide structure directly contacts the upper surface of the polysilicon feature and is disposed directly above the shallow trench isolation region. In some embodiments, the integrated circuit further comprises a channel region having a first conductivity, a polysilicon feature, a gate dielectric, a source region having a second conductivity, and a drain region having a second conductivity. The channel region is disposed in a semiconductor substrate. The polysilicon feature extends over the channel region. The gate dielectric separates the polysilicon feature from the channel region. The source region is disposed in the semiconductor substrate to a first side of the polysilicon feature. The second conductivity is opposite to the first conductivity. The drain region is disposed in the semiconductor substrate to a second side of the polysilicon feature, the second side being opposite to the first side. The silicide structure directly contacts an upper surface of the polysilicon feature. In some embodiments, the integrated circuit further comprises a channel region having a first conductivity, a polysilicon feature, a gate dielectric, a source region having a second conductivity, and a drain region having a second conductivity. The channel region is disposed in a semiconductor substrate. The polysilicon feature extends over the channel region.The gate dielectric separates the polysilicon feature from the channel region. The source region is disposed in the semiconductor substrate to a first side of the polysilicon feature. The second conductivity is opposite to the first conductivity. The drain region is disposed in the semiconductor substrate to a second side of the polysilicon feature, the second side being opposite to the first side. The silicide structure directly contacts an upper surface of the source region or an upper surface of the drain region. In some embodiments, the silicide structure is disposed on the semiconductor substrate. In some embodiments, the integrated circuit further includes a shallow trench isolation (STI) region formed of a dielectric material, which is disposed in the semiconductor substrate. The silicide structure directly contacts a sidewall of the shallow trench isolation region.

[0063] Some other embodiments are related to another integrated circuit, including a semiconductor substrate, a gate electrode, a first silicide structure, a first dielectric structure, and a first conductive structure. The gate electrode extends above the semiconductor substrate. The first silicide structure is disposed on the gate electrode. The first dielectric structure is directly disposed on the first silicide structure. The first conductive structure directly contacts the upper surface of the first dielectric structure, so that the first silicide structure and the first conductive structure respectively establish a first bottom electrode and a first top electrode spaced apart from each other by the first dielectric structure to establish a first conductor-insulator-silicide capacitor above the gate electrode. In some embodiments, the integrated circuit further includes a dielectric layer and a contact. The dielectric layer laterally surrounds the gate electrode and the first conductive structure and extends above the first conductive structure. The contact extends through the dielectric layer and extends beside the first conductive structure and the first dielectric structure to contact the upper surface of the first silicide structure. In some embodiments, the integrated circuit further includes a second silicide structure, a second dielectric structure, and a second conductive structure. The second silicide structure is disposed on the semiconductor substrate and is laterally spaced apart from the gate electrode. The second dielectric structure is directly disposed on the second silicide structure. The second conductive structure directly contacts the upper surface of the second dielectric structure, so that the second silicide structure and the second conductive structure respectively establish a second bottom electrode and a second top electrode separated from each other by the second dielectric structure to establish a second conductor-insulator-silicide capacitor. In some embodiments, the first silicide structure is disposed at a first silicide height above the semiconductor substrate, and the second silicide structure is disposed at a second silicide height above the semiconductor substrate, and the second silicide height is less than the first silicide height. In some embodiments, the first dielectric structure and the second dielectric structure are portions of a single dielectric layer that continuously extends from above the first silicide structure to above the second silicide structure.

[0064] Some embodiments are related to a method for manufacturing an integrated circuit including the following steps. A silicide layer is formed on a substrate, the silicide layer including a first silicide structure and a second silicide structure. A capacitor dielectric layer is formed on the silicide layer. A metal layer is formed on the capacitor dielectric layer. The metal layer is patterned to form a first metal structure on the first silicide structure and a second metal structure on the second silicide structure. An interlayer dielectric is formed on the first metal structure and the second metal structure. A first contact and a second contact are formed to reach the first metal structure and the second metal structure, and a third contact and a fourth contact are formed to reach the first silicide structure and the second silicide structure. In some embodiments, the first silicide structure and the second silicide structure are arranged at different heights above the substrate. In some embodiments, the capacitor dielectric layer is a continuous dielectric layer extending between the first silicide structure and the second silicide structure. In some embodiments, the first contact and the second contact are formed simultaneously with the third contact and the fourth contact. In some embodiments, the first silicide structure and the second silicide structure include cobalt, nickel or tantalum; and the capacitor dielectric layer includes oxide, nitride, carbide, oxynitride, oxycarbide, carbonitride or polymer; and the first metal structure and the second metal structure have the same composition as each other and include metal or metal alloy.

[0065] It should be understood that in this written description and in the claims that follow, the terms "first," "second," "third," etc., are merely general identifiers used for ease of description to distinguish different components of a figure or series of figures. By themselves, these terms do not imply any temporal order or structural proximity of the components and are not intended to describe corresponding components in different illustrated embodiments and / or non-illustrated embodiments. For example, a "first dielectric layer" described in conjunction with a first figure may not necessarily correspond to a "first dielectric layer" described in conjunction with another figure and may not necessarily correspond to a "first dielectric layer" in a non-illustrated embodiment.

[0066] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of the embodiments of the present invention. Those skilled in the art should understand that they can easily use the embodiments of the present invention as a basis for designing or modifying other processes and structures to implement the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of the embodiments of the present invention, and they can make various changes, substitutions and modifications to them herein without departing from the spirit and scope of the embodiments of the present invention.

Claims

1. An integrated circuit, characterized in that: include: Semiconductor substrate; a silicide structure disposed on the semiconductor substrate in the cross-sectional view; a dielectric structure directly contacting an upper surface of the silicide structure in the cross-sectional view; as well as A metal structure directly contacts an upper surface of the dielectric structure in the cross-sectional view such that the silicide structure, the dielectric structure, and the metal structure establish a metal-insulator-silicide capacitor on the semiconductor substrate.

2. The integrated circuit according to claim 1, characterized in that The upper surface of the silicide structure has a first surface area, and the upper surface of the metal structure has a second surface area; and wherein the first surface area is greater than the second surface area.

3. The integrated circuit according to claim 1, characterized in that The metal structure covers a first portion of the upper surface of the silicide structure but does not cover a second portion of the upper surface of the silicide structure.

4. The integrated circuit according to claim 3, characterized in that Also includes: a first metal feature disposed over the first portion of the upper surface of the silicide structure and spaced apart from the first portion of the upper surface of the silicide structure by a dielectric; a first contact extending from the first metal feature through the dielectric and contacting the metal structure; a second metal feature disposed on the second portion of the upper surface of the silicide structure and spaced apart from the metal structure by the dielectric, the second metal feature having the same height as the first metal feature and spaced apart laterally from the first metal feature, the height being measured perpendicular to the upper surface of the semiconductor substrate; and A second contact extends from the second metal feature through the dielectric and contacts the second portion of the upper surface of the silicide structure.

5. The integrated circuit according to claim 1, characterized in that Also includes: A channel region having a first conductivity, disposed in the semiconductor substrate; a polysilicon feature extending over the channel region; a gate dielectric separating the polysilicon feature from the channel region; a source region having a second conductivity disposed in the semiconductor substrate to a first side of the polysilicon feature, the second conductivity being opposite to the first conductivity; a drain region having the second conductivity disposed in the semiconductor substrate to a second side of the polysilicon feature, the second side being opposite to the first side; and The silicide structure directly contacts an upper surface of the source region or an upper surface of the drain region.

6. The integrated circuit according to claim 1, characterized in that Also includes: A shallow trench isolation region formed of a dielectric material is disposed in the semiconductor substrate; The silicide structure directly contacts the sidewall of the shallow trench isolation region.

7. An integrated circuit, characterized in that: include: Semiconductor substrate; a gate electrode extending above the semiconductor substrate; A first silicide structure is disposed on the gate electrode; A first dielectric structure is directly disposed on the first silicide structure; as well as The first conductive structure directly contacts the upper surface of the first dielectric structure, so that the first silicide structure and the first conductive structure respectively establish a first bottom electrode and a first top electrode separated from each other by the first dielectric structure to establish a first conductor-insulator-silicide capacitor above the gate electrode.

8. The integrated circuit according to claim 7, characterized in that Also includes: a second silicide structure disposed on the semiconductor substrate and laterally spaced apart from the gate electrode; a second dielectric structure disposed directly on the second silicide structure; as well as The second conductive structure directly contacts the upper surface of the second dielectric structure, so that the second silicide structure and the second conductive structure respectively establish a second bottom electrode and a second top electrode separated from each other by the second dielectric structure to establish a second conductor-insulator-silicide capacitor.

9. The integrated circuit according to claim 8, characterized in that The first silicide structure is disposed at a first silicide height above the semiconductor substrate, and the second silicide structure is disposed at a second silicide height above the semiconductor substrate, wherein the second silicide height is smaller than the first silicide height.

10. The integrated circuit according to claim 8, characterized in that The first dielectric structure and the second dielectric structure are portions of a single dielectric layer that continuously extends from above the first silicide structure to above the second silicide structure.

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